1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef AMD_GENOA_POC_IOMAP_H 4 #define AMD_GENOA_POC_IOMAP_H 5 6 #define I2C_MASTER_DEV_COUNT 6 7 #define I2C_PERIPHERAL_DEV_COUNT 0 8 #define I2C_CTRLR_COUNT (I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT) 9 10 #define SPI_BASE_ADDRESS 0xfec10000 11 12 /* @Todo : Check these values for Genoa */ 13 14 /* I/O Ranges */ 15 #define ACPI_IO_BASE 0x0400 16 #define ACPI_CSTATE_CONTROL (ACPI_IO_BASE + 0x10) 17 18 /* FCH AL2AHB Registers */ 19 #define ALINK_AHB_ADDRESS 0xfedc0000 20 21 #define APU_I2C0_BASE 0xfedc2000 22 #define APU_I2C1_BASE 0xfedc3000 23 #define APU_I2C2_BASE 0xfedc4000 24 #define APU_I2C3_BASE 0xfedc5000 25 #define APU_I2C4_BASE 0xfedc6000 26 #define APU_I2C5_BASE 0xfedcb000 27 28 #define APU_UART0_BASE 0xfedc9000 29 #define APU_UART1_BASE 0xfedca000 30 #define APU_UART2_BASE 0xfedce000 31 32 #define APU_I3C0_BASE 0xfedd2000 33 #define APU_I3C1_BASE 0xfedd3000 34 #define APU_I3C2_BASE 0xfedd4000 35 #define APU_I3C3_BASE 0xfedd6000 36 37 #endif /* AMD_GENOA_POC_IOMAP_H */ 38