1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_MEDIATEK_MT8186_INCLUDE_SOC_ADDRESSMAP_H__ 4 #define __SOC_MEDIATEK_MT8186_INCLUDE_SOC_ADDRESSMAP_H__ 5 6 enum { 7 MCUSYS_BASE = 0x0C530000, 8 IO_PHYS = 0x10000000, 9 }; 10 11 enum { 12 MCUCFG_BASE = MCUSYS_BASE + 0x00008000, 13 }; 14 15 enum { 16 CKSYS_BASE = IO_PHYS + 0x00000000, 17 INFRACFG_AO_BASE = IO_PHYS + 0x00001000, 18 IOCFG_LT_BASE = IO_PHYS + 0x00002000, 19 IOCFG_LM_BASE = IO_PHYS + 0x00002200, 20 IOCFG_LB_BASE = IO_PHYS + 0x00002400, 21 IOCFG_BL_BASE = IO_PHYS + 0x00002600, 22 IOCFG_RB_BASE = IO_PHYS + 0x00002A00, 23 IOCFG_RT_BASE = IO_PHYS + 0x00002C00, 24 PERICFG_BASE = IO_PHYS + 0x00003000, 25 GPIO_BASE = IO_PHYS + 0x00005000, 26 SPM_BASE = IO_PHYS + 0x00006000, 27 RGU_BASE = IO_PHYS + 0x00007000, 28 GPT_BASE = IO_PHYS + 0x00008000, 29 EINT_BASE = IO_PHYS + 0x0000B000, 30 APMIXED_BASE = IO_PHYS + 0x0000C000, 31 PWRAP_BASE = IO_PHYS + 0x0000D000, 32 /* Add PMICSPI_MST_BASE and PMIF_SPI_BASE to solve the build error */ 33 PMICSPI_MST_BASE = IO_PHYS + 0x0000D000, 34 PMIF_SPI_BASE = IO_PHYS + 0x0000D000, 35 DEVAPC_AO_INFRA_PERI_BASE = IO_PHYS + 0x0000E000, 36 DEVAPC_AO_MM_BASE = IO_PHYS + 0x0000F000, 37 PMIF_SPMI_BASE = IO_PHYS + 0x00015000, 38 SYSTIMER_BASE = IO_PHYS + 0x00017000, 39 SPMI_MST_BASE = IO_PHYS + 0x0001B000, 40 I2C0_DMA_BASE = IO_PHYS + 0x00200100, 41 I2C1_DMA_BASE = IO_PHYS + 0x00200200, 42 I2C2_DMA_BASE = IO_PHYS + 0x00200300, 43 I2C3_DMA_BASE = IO_PHYS + 0x00200480, 44 I2C4_DMA_BASE = IO_PHYS + 0x00200580, 45 I2C5_DMA_BASE = IO_PHYS + 0x00200700, 46 I2C6_DMA_BASE = IO_PHYS + 0x00200800, 47 I2C7_DMA_BASE = IO_PHYS + 0x00200900, 48 I2C8_DMA_BASE = IO_PHYS + 0x00200A80, 49 I2C9_DMA_BASE = IO_PHYS + 0x00200C00, 50 DEVAPC_BASE = IO_PHYS + 0x00207000, 51 DBG_TRACKER_BASE = IO_PHYS + 0x00208000, 52 EMI0_BASE = IO_PHYS + 0x00219000, 53 EMI0_MPU_BASE = IO_PHYS + 0x0021B000, 54 DRAMC_CHA_AO_BASE = IO_PHYS + 0x00220000, 55 SSPM_SRAM_BASE = IO_PHYS + 0x00400000, 56 SSPM_CFG_BASE = IO_PHYS + 0x00440000, 57 SCP_CLK_BASE = IO_PHYS + 0x005C4000, 58 AUDIODSP_BASE = IO_PHYS + 0x00680000, 59 DEVAPC_AO_AUD_BASE = IO_PHYS + 0x0069C000, 60 SFLASH_REG_BASE = IO_PHYS + 0x01000000, 61 AUXADC_BASE = IO_PHYS + 0x01001000, 62 UART0_BASE = IO_PHYS + 0x01002000, 63 I2C7_BASE = IO_PHYS + 0x01004000, 64 I2C8_BASE = IO_PHYS + 0x01005000, 65 I2C0_BASE = IO_PHYS + 0x01007000, 66 I2C1_BASE = IO_PHYS + 0x01008000, 67 I2C2_BASE = IO_PHYS + 0x01009000, 68 SPI0_BASE = IO_PHYS + 0x0100A000, 69 I2C6_BASE = IO_PHYS + 0x0100D000, 70 I2C3_BASE = IO_PHYS + 0x0100F000, 71 SPI1_BASE = IO_PHYS + 0x01010000, 72 I2C4_BASE = IO_PHYS + 0x01011000, 73 SPI2_BASE = IO_PHYS + 0x01012000, 74 SPI3_BASE = IO_PHYS + 0x01013000, 75 SPI4_BASE = IO_PHYS + 0x01014000, 76 SPI5_BASE = IO_PHYS + 0x01015000, 77 I2C5_BASE = IO_PHYS + 0x01016000, 78 I2C9_BASE = IO_PHYS + 0x01019000, 79 /* IPPC_BASE is for USB2 port1, IPPC_BASE_P0 is for USB2 port0 */ 80 SSUSB_IPPC_BASE_P0 = IO_PHYS + 0x01203E00, 81 SSUSB_IPPC_BASE = IO_PHYS + 0x01283E00, 82 MSDC0_BASE = IO_PHYS + 0x01230000, 83 /* SIF_BASE is for USB2 port1, SIF_BASE_P0 is for USB2 port0 */ 84 SSUSB_SIF_BASE = IO_PHYS + 0x01C80300, 85 SSUSB_SIF_BASE_P0 = IO_PHYS + 0x01CA0300, 86 EFUSEC_BASE = IO_PHYS + 0x01CB0000, 87 MIPITX_BASE = IO_PHYS + 0x01CC0000, 88 MSDC0_TOP_BASE = IO_PHYS + 0x01CD0000, 89 MMSYS_BASE = IO_PHYS + 0x04000000, 90 DISP_MUTEX_BASE = IO_PHYS + 0x04001000, 91 SMI_BASE = IO_PHYS + 0x04002000, 92 SMI_LARB0 = IO_PHYS + 0x04003000, 93 DISP_OVL0_BASE = IO_PHYS + 0x04005000, 94 DISP_OVL1_BASE = IO_PHYS + 0x04006000, 95 DISP_RDMA0_BASE = IO_PHYS + 0x04007000, 96 DISP_COLOR0_BASE = IO_PHYS + 0x04009000, 97 DISP_CCORR0_BASE = IO_PHYS + 0x0400B000, 98 DISP_AAL0_BASE = IO_PHYS + 0x0400C000, 99 DISP_GAMMA0_BASE = IO_PHYS + 0x0400D000, 100 DISP_POSTMASK0_BASE = IO_PHYS + 0x0400E000, 101 DISP_DITHER0_BASE = IO_PHYS + 0x0400F000, 102 DSI0_BASE = IO_PHYS + 0x04013000, 103 }; 104 #endif 105