1 /* 2 * Copyright (c) 2024, Rockchip, Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLAT_DEF_H__ 8 #define __PLAT_DEF_H__ 9 10 #define SIZE_K(n) ((n) * 1024) 11 12 #define WITH_16BITS_WMSK(bits) (0xffff0000 | (bits)) 13 14 /* Special value used to verify platform parameters from BL2 to BL3-1 */ 15 #define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 16 17 #define UMCTL0_BASE 0xf7000000 18 #define UMCTL1_BASE 0xf8000000 19 #define UMCTL2_BASE 0xf9000000 20 #define UMCTL3_BASE 0xfa000000 21 22 #define GIC600_BASE 0xfe600000 23 #define GIC600_SIZE SIZE_K(64) 24 25 #define DAPLITE_BASE 0xfd100000 26 #define PMU0SGRF_BASE 0xfd580000 27 #define PMU1SGRF_BASE 0xfd582000 28 #define BUSSGRF_BASE 0xfd586000 29 #define DSUSGRF_BASE 0xfd587000 30 #define PMU0GRF_BASE 0xfd588000 31 #define PMU1GRF_BASE 0xfd58a000 32 33 #define SYSGRF_BASE 0xfd58c000 34 #define BIGCORE0GRF_BASE 0xfd590000 35 #define BIGCORE1GRF_BASE 0xfd592000 36 #define LITCOREGRF_BASE 0xfd594000 37 #define DSUGRF_BASE 0xfd598000 38 #define DDR01GRF_BASE 0xfd59c000 39 #define DDR23GRF_BASE 0xfd59d000 40 #define CENTERGRF_BASE 0xfd59e000 41 #define GPUGRF_BASE 0xfd5a0000 42 #define NPUGRF_BASE 0xfd5a2000 43 #define USBGRF_BASE 0xfd5ac000 44 #define PHPGRF_BASE 0xfd5b0000 45 #define PCIE3PHYGRF_BASE 0xfd5b8000 46 #define USB2PHY0_GRF_BASE 0xfd5d0000 47 #define USB2PHY1_GRF_BASE 0xfd5d4000 48 #define USB2PHY2_GRF_BASE 0xfd5d8000 49 #define USB2PHY3_GRF_BASE 0xfd5dc000 50 51 #define PMU0IOC_BASE 0xfd5f0000 52 #define PMU1IOC_BASE 0xfd5f4000 53 #define BUSIOC_BASE 0xfd5f8000 54 #define VCCIO1_4_IOC_BASE 0xfd5f9000 55 #define VCCIO3_5_IOC_BASE 0xfd5fa000 56 #define VCCIO2_IOC_BASE 0xfd5fb000 57 #define VCCIO6_IOC_BASE 0xfd5fc000 58 59 #define SRAM_BASE 0xff000000 60 #define PMUSRAM_BASE 0xff100000 61 #define PMUSRAM_SIZE SIZE_K(128) 62 #define PMUSRAM_RSIZE SIZE_K(64) 63 64 #define CRU_BASE 0xfd7c0000 65 #define PHP_CRU_BASE 0xfd7c8000 66 #define SCRU_BASE 0xfd7d0000 67 #define BUSSCRU_BASE 0xfd7d8000 68 #define PMU1SCRU_BASE 0xfd7e0000 69 #define PMU1CRU_BASE 0xfd7f0000 70 71 #define DDR0CRU_BASE 0xfd800000 72 #define DDR1CRU_BASE 0xfd804000 73 #define DDR2CRU_BASE 0xfd808000 74 #define DDR3CRU_BASE 0xfd80c000 75 76 #define BIGCORE0CRU_BASE 0xfd810000 77 #define BIGCORE1CRU_BASE 0xfd812000 78 #define LITCRU_BASE 0xfd814000 79 #define DSUCRU_BASE 0xfd818000 80 81 #define I2C0_BASE 0xfd880000 82 #define UART0_BASE 0xfd890000 83 #define GPIO0_BASE 0xfd8a0000 84 #define PWM0_BASE 0xfd8b0000 85 #define PMUPVTM_BASE 0xfd8c0000 86 #define TIMER_HP_BASE 0xfd8c8000 87 #define PMU0_BASE 0xfd8d0000 88 #define PMU1_BASE 0xfd8d4000 89 #define PMU2_BASE 0xfd8d8000 90 #define PMU_BASE PMU0_BASE 91 #define PMUWDT_BASE 0xfd8e0000 92 #define PMUTIMER_BASE 0xfd8f0000 93 #define OSC_CHK_BASE 0xfd9b0000 94 #define VOP_BASE 0xfdd90000 95 #define HDMIRX_BASE 0xfdee0000 96 97 #define MSCH0_BASE 0xfe000000 98 #define MSCH1_BASE 0xfe002000 99 #define MSCH2_BASE 0xfe004000 100 #define MSCH3_BASE 0xfe006000 101 #define FIREWALL_DSU_BASE 0xfe010000 102 #define FIREWALL_DDR_BASE 0xfe030000 103 #define FIREWALL_SYSMEM_BASE 0xfe038000 104 #define DDRPHY0_BASE 0xfe0c0000 105 #define DDRPHY1_BASE 0xfe0d0000 106 #define DDRPHY2_BASE 0xfe0e0000 107 #define DDRPHY3_BASE 0xfe0f0000 108 #define TIMER_DDR_BASE 0xfe118000 109 #define KEYLADDER_BASE 0xfe380000 110 #define CRYPTO_S_BASE 0xfe390000 111 #define OTP_S_BASE 0xfe3a0000 112 #define DCF_BASE 0xfe3c0000 113 #define STIMER0_BASE 0xfe3d0000 114 #define WDT_S_BASE 0xfe3e0000 115 #define CRYPTO_S_BY_KEYLAD_BASE 0xfe420000 116 #define NSTIMER0_BASE 0xfeae0000 117 #define NSTIMER1_BASE 0xfeae8000 118 #define WDT_NS_BASE 0xfeaf0000 119 120 #define UART1_BASE 0xfeb40000 121 #define UART2_BASE 0xfeb50000 122 #define UART3_BASE 0xfeb60000 123 #define UART4_BASE 0xfeb70000 124 #define UART5_BASE 0xfeb80000 125 #define UART6_BASE 0xfeb90000 126 #define UART7_BASE 0xfeba0000 127 #define UART8_BASE 0xfebb0000 128 #define UART9_BASE 0xfebc0000 129 130 #define GPIO1_BASE 0xfec20000 131 #define GPIO2_BASE 0xfec30000 132 #define GPIO3_BASE 0xfec40000 133 #define GPIO4_BASE 0xfec50000 134 135 #define MAILBOX1_BASE 0xfec70000 136 #define OTP_NS_BASE 0xfecc0000 137 #define INTMUX0_DDR_BASE 0Xfecf8000 138 #define INTMUX1_DDR_BASE 0Xfecfc000 139 #define STIMER1_BASE 0xfed30000 140 141 /************************************************************************** 142 * sys sram allocation 143 **************************************************************************/ 144 #define SRAM_ENTRY_BASE SRAM_BASE 145 #define SRAM_PMUM0_SHMEM_BASE (SRAM_ENTRY_BASE + SIZE_K(3)) 146 #define SRAM_LD_BASE (SRAM_ENTRY_BASE + SIZE_K(4)) 147 #define SRAM_LD_SIZE SIZE_K(64) 148 149 #define SRAM_LD_SP (SRAM_LD_BASE + SRAM_LD_SIZE -\ 150 128) 151 152 /************************************************************************** 153 * share mem region allocation: 1M~2M 154 **************************************************************************/ 155 #define DDR_SHARE_MEM SIZE_K(1024) 156 #define DDR_SHARE_SIZE SIZE_K(64) 157 158 #define SHARE_MEM_BASE DDR_SHARE_MEM 159 #define SHARE_MEM_PAGE_NUM 15 160 #define SHARE_MEM_SIZE SIZE_K(SHARE_MEM_PAGE_NUM * 4) 161 162 #define SCMI_SHARE_MEM_BASE (SHARE_MEM_BASE + SHARE_MEM_SIZE) 163 #define SCMI_SHARE_MEM_SIZE SIZE_K(4) 164 165 #define SMT_BUFFER_BASE SCMI_SHARE_MEM_BASE 166 #define SMT_BUFFER0_BASE SMT_BUFFER_BASE 167 168 /************************************************************************** 169 * UART related constants 170 **************************************************************************/ 171 #define RK_DBG_UART_BASE UART2_BASE 172 #define RK_DBG_UART_BAUDRATE 1500000 173 #define RK_DBG_UART_CLOCK 24000000 174 175 /****************************************************************************** 176 * System counter frequency related constants 177 ******************************************************************************/ 178 #define SYS_COUNTER_FREQ_IN_TICKS 24000000 179 #define SYS_COUNTER_FREQ_IN_MHZ 24 180 181 /****************************************************************************** 182 * GIC-600 & interrupt handling related constants 183 ******************************************************************************/ 184 185 /* Base rk_platform compatible GIC memory map */ 186 #define PLAT_GICD_BASE GIC600_BASE 187 #define PLAT_GICC_BASE 0 188 #define PLAT_GICR_BASE (GIC600_BASE + 0x80000) 189 #define PLAT_GICITS0_BASE 0xfe640000 190 #define PLAT_GICITS1_BASE 0xfe660000 191 192 /****************************************************************************** 193 * sgi, ppi 194 ******************************************************************************/ 195 #define RK_IRQ_SEC_SGI_0 8 196 #define RK_IRQ_SEC_SGI_1 9 197 #define RK_IRQ_SEC_SGI_2 10 198 #define RK_IRQ_SEC_SGI_3 11 199 #define RK_IRQ_SEC_SGI_4 12 200 #define RK_IRQ_SEC_SGI_5 13 201 #define RK_IRQ_SEC_SGI_6 14 202 #define RK_IRQ_SEC_SGI_7 15 203 #define RK_IRQ_SEC_PHY_TIMER 29 204 205 /* 206 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 207 * terminology. On a GICv2 system or mode, the lists will be merged and treated 208 * as Group 0 interrupts. 209 */ 210 211 #define PLAT_RK_GICV3_G1S_IRQS \ 212 INTR_PROP_DESC(RK_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ 213 INTR_GROUP1S, GIC_INTR_CFG_LEVEL) 214 215 #define PLAT_RK_GICV3_G0_IRQS \ 216 INTR_PROP_DESC(RK_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ 217 INTR_GROUP0, GIC_INTR_CFG_LEVEL) 218 219 /****************************************************************************** 220 * pm reg region memory 221 ******************************************************************************/ 222 #define ROCKCHIP_PM_REG_REGION_MEM_SIZE SIZE_K(4) 223 224 #endif /* __PLAT_DEF_H__ */ 225