| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/M68k/ |
| D | M68kISelLowering.cpp | 2001 SDValue CCR = EmitCmp(Op0, Op1, M68kCC, DL, DAG); in LowerSETCC() local
3378 static SDValue getSETCC(M68k::CondCode Cond, SDValue CCR, const SDLoc &dl, in getSETCC()
3386 static SDValue combineCarryThroughADD(SDValue CCR) { in combineCarryThroughADD()
3411 static SDValue combineSetCCCCR(SDValue CCR, M68k::CondCode &CC, in combineSetCCCCR()
3426 SDValue CCR = N->getOperand(1); in combineM68kSetCC() local
3438 SDValue CCR = N->getOperand(3); in combineM68kBrCond() local
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 3564 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerXALUO() local
3595 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT() local
3630 SDValue CCR = Cond.getOperand(3); in LowerSELECT() local
3698 SDValue TrueVal, SDValue ARMcc, SDValue CCR, in getCMOV()
3901 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC() local
3927 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC() local
4039 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in OptimizeVFPBrcond() local
4083 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC() local
4102 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC() local
4540 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerShiftRightParts() local
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 4474 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSignedALUO() local
4594 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT() local
4629 SDValue CCR = Cond.getOperand(3); in LowerSELECT() local
4698 SDValue TrueVal, SDValue ARMcc, SDValue CCR, in getCMOV()
5046 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC() local
5081 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC() local
5188 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in OptimizeVFPBrcond() local
5237 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBRCOND() local
5291 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC() local
5300 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC() local
[all …]
|
| /external/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/ |
| D | core_cm0.h | 396 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
|
| D | core_cm0plus.h | 414 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
|
| D | core_sc000.h | 402 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
|
| D | core_cm3.h | 424 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
|
| D | core_sc300.h | 424 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
|
| D | core_cm4.h | 492 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
|
| D | core_cm7.h | 507 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
|
| /external/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/ |
| D | core_cm0.h | 396 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
|
| D | core_sc000.h | 402 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
|
| D | core_cm0plus.h | 414 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
|
| D | core_sc300.h | 424 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
|
| D | core_cm3.h | 424 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
|
| D | core_cm4.h | 492 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
|
| D | core_cm7.h | 507 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 4974 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSignedALUO() local
5119 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT() local
5154 SDValue CCR = Cond.getOperand(3); in LowerSELECT() local
5223 SDValue TrueVal, SDValue ARMcc, SDValue CCR, in getCMOV()
5518 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC() local
5553 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC() local
5660 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in OptimizeVFPBrcond() local
5709 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBRCOND() local
5763 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC() local
5772 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC() local
[all …]
|
| /external/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ |
| D | stm32l476xx.h | 240 …__IO uint32_t CCR; /*!< ADC common configuration register, Address offset: AD… member
360 …__IO uint32_t CCR; /*!< DAC calibration control register, Address o… member
423 __IO uint32_t CCR; /*!< DMA channel x configuration register */ member
687 …__IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset… member
994 …__IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 … member
|
| /external/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ |
| D | stm32l4a6xx.h | 250 …__IO uint32_t CCR; /*!< ADC common configuration register, Address offset: AD… member
399 …__IO uint32_t CCR; /*!< DAC calibration control register, Address o… member
462 __IO uint32_t CCR; /*!< DMA channel x configuration register */ member
758 …__IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset… member
1068 …__IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 … member
|