1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 3 #ifndef PLL_H 4 #define PLL_H 5 6 #include "mt8195.h" 7 8 /* for MTCMOS bus protection */ 9 //TODO 10 #define INFRA_TOPAXI_PROTECTEN (INFRACFG_AO_BASE + 0x0220) 11 #define INFRA_TOPAXI_PROTECTEN_SET (INFRACFG_AO_BASE + 0x02A0) 12 #define INFRA_TOPAXI_PROTECTEN_CLR (INFRACFG_AO_BASE + 0x02A4) 13 #define INFRA_TOPAXI_PROTECTEN_STA0 (INFRACFG_AO_BASE + 0x0224) 14 #define INFRA_TOPAXI_PROTECTEN_STA1 (INFRACFG_AO_BASE + 0x0228) 15 16 #define INFRA_TOPAXI_PROTECTEN_1 (INFRACFG_AO_BASE + 0x0250) 17 #define INFRA_TOPAXI_PROTECTEN_1_SET (INFRACFG_AO_BASE + 0x02A8) 18 #define INFRA_TOPAXI_PROTECTEN_1_CLR (INFRACFG_AO_BASE + 0x02AC) 19 #define INFRA_TOPAXI_PROTECTEN_STA0_1 (INFRACFG_AO_BASE + 0x0254) 20 #define INFRA_TOPAXI_PROTECTEN_STA1_1 (INFRACFG_AO_BASE + 0x0258) 21 22 #define INFRA_TOPAXI_PROTECTEN_MCU (INFRACFG_AO_BASE + 0x02C0) 23 #define INFRA_TOPAXI_PROTECTEN_MCU_STA0 (INFRACFG_AO_BASE + 0x02E0) 24 #define INFRA_TOPAXI_PROTECTEN_MCU_STA1 (INFRACFG_AO_BASE + 0x02E4) 25 #define INFRA_TOPAXI_PROTECTEN_MCU_SET (INFRACFG_AO_BASE + 0x02C4) 26 #define INFRA_TOPAXI_PROTECTEN_MCU_CLR (INFRACFG_AO_BASE + 0x02C8) 27 28 #define INFRA_TOPAXI_PROTECTEN_MM (INFRACFG_AO_BASE + 0x02D0) 29 #define INFRA_TOPAXI_PROTECTEN_MM_SET (INFRACFG_AO_BASE + 0x02D4) 30 #define INFRA_TOPAXI_PROTECTEN_MM_CLR (INFRACFG_AO_BASE + 0x02D8) 31 #define INFRA_TOPAXI_PROTECTEN_MM_STA0 (INFRACFG_AO_BASE + 0x02E8) 32 #define INFRA_TOPAXI_PROTECTEN_MM_STA1 (INFRACFG_AO_BASE + 0x02EC) 33 34 #define INFRA_TOPAXI_PROTECTEN_2 (INFRACFG_AO_BASE + 0x0710) 35 #define INFRA_TOPAXI_PROTECTEN_2_SET (INFRACFG_AO_BASE + 0x0714) 36 #define INFRA_TOPAXI_PROTECTEN_2_CLR (INFRACFG_AO_BASE + 0x0718) 37 #define INFRA_TOPAXI_PROTECTEN_STA0_2 (INFRACFG_AO_BASE + 0x0720) 38 #define INFRA_TOPAXI_PROTECTEN_STA1_2 (INFRACFG_AO_BASE + 0x0724) 39 40 #define INFRA_TOPAXI_PROTECTEN_MM_2 (INFRACFG_AO_BASE + 0x0DC8) 41 #define INFRA_TOPAXI_PROTECTEN_MM_2_SET (INFRACFG_AO_BASE + 0x0DCC) 42 #define INFRA_TOPAXI_PROTECTEN_MM_2_CLR (INFRACFG_AO_BASE + 0x0DD0) 43 #define INFRA_TOPAXI_PROTECTEN_MM_2_STA0 (INFRACFG_AO_BASE + 0x0DD4) 44 #define INFRA_TOPAXI_PROTECTEN_MM_2_STA1 (INFRACFG_AO_BASE + 0x0DD8) 45 46 #define INFRA_TOPAXI_PROTECTEN_INFRA_VDNR (INFRACFG_AO_BASE + 0x0B80) 47 #define INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_SET (INFRACFG_AO_BASE + 0x0B84) 48 #define INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_CLR (INFRACFG_AO_BASE + 0x0B88) 49 #define INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_STA0 (INFRACFG_AO_BASE + 0x0B8c) 50 #define INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_STA1 (INFRACFG_AO_BASE + 0x0B90) 51 52 #define INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_1 (INFRACFG_AO_BASE + 0x0BA0) 53 #define INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_1_SET (INFRACFG_AO_BASE + 0x0BA4) 54 #define INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_1_CLR (INFRACFG_AO_BASE + 0x0BA8) 55 #define INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_1_STA0 (INFRACFG_AO_BASE + 0x0BAc) 56 #define INFRA_TOPAXI_PROTECTEN_INFRA_VDNR_1_STA1 (INFRACFG_AO_BASE + 0x0BB0) 57 58 #define INFRA_TOPAXI_PROTECTEN_SUB_INFRA_VDNR (INFRACFG_AO_BASE + 0x0BB4) 59 #define INFRA_TOPAXI_PROTECTEN_SUB_INFRA_VDNR_SET (INFRACFG_AO_BASE + 0x0BB8) 60 #define INFRA_TOPAXI_PROTECTEN_SUB_INFRA_VDNR_CLR (INFRACFG_AO_BASE + 0x0BBC) 61 #define INFRA_TOPAXI_PROTECTEN_SUB_INFRA_VDNR_STA0 (INFRACFG_AO_BASE + 0x0BC0) 62 #define INFRA_TOPAXI_PROTECTEN_SUB_INFRA_VDNR_STA1 (INFRACFG_AO_BASE + 0x0BC4) 63 64 /* MCUCFG Register */ 65 #define CPU_PLLDIV_CFG0 (MCUCFG_BASE + 0xA2A0) 66 #define CPU_PLLDIV_CFG1 (MCUCFG_BASE + 0xA2A4) 67 #define BUS_PLLDIV_CFG (MCUCFG_BASE + 0xA2E0) 68 69 /* APMIXEDSYS Register */ 70 #define AP_PLL_CON0 (APMIXED_BASE + 0x0000) 71 72 #define PLLON_CON0 (APMIXED_BASE + 0x0050) 73 #define PLLON_CON1 (APMIXED_BASE + 0x0054) 74 #define PLLON_CON2 (APMIXED_BASE + 0x0058) 75 #define PLLON_CON3 (APMIXED_BASE + 0x005C) 76 77 #define ARMPLL_LL_CON0 (APMIXED_BASE + 0x0020) 78 #define ARMPLL_LL_CON1 (APMIXED_BASE + 0x0024) 79 #define ARMPLL_LL_CON2 (APMIXED_BASE + 0x0028) 80 #define ARMPLL_LL_CON3 (APMIXED_BASE + 0x002C) 81 #define ARMPLL_LL_CON4 (APMIXED_BASE + 0X0600) 82 83 #define ARMPLL_BL_CON0 (APMIXED_BASE + 0X0070) 84 #define ARMPLL_BL_CON1 (APMIXED_BASE + 0X0074) 85 #define ARMPLL_BL_CON2 (APMIXED_BASE + 0X0078) 86 #define ARMPLL_BL_CON3 (APMIXED_BASE + 0X007C) 87 #define ARMPLL_BL_CON4 (APMIXED_BASE + 0X0080) 88 89 #define CCIPLL_CON0 (APMIXED_BASE + 0X0030) 90 #define CCIPLL_CON1 (APMIXED_BASE + 0X0634) 91 #define CCIPLL_CON2 (APMIXED_BASE + 0X0638) 92 #define CCIPLL_CON3 (APMIXED_BASE + 0X063C) 93 #define CCIPLL_CON4 (APMIXED_BASE + 0X0640) 94 95 #define NNAPLL_CON0 (APMIXED_BASE + 0X0390) 96 #define NNAPLL_CON1 (APMIXED_BASE + 0X0394) 97 #define NNAPLL_CON2 (APMIXED_BASE + 0X0398) 98 #define NNAPLL_CON3 (APMIXED_BASE + 0X039C) 99 #define NNAPLL_CON4 (APMIXED_BASE + 0X03A0) 100 101 #define RESPLL_CON0 (APMIXED_BASE + 0X0190) 102 #define RESPLL_CON1 (APMIXED_BASE + 0X0194) 103 #define RESPLL_CON2 (APMIXED_BASE + 0X0198) 104 #define RESPLL_CON3 (APMIXED_BASE + 0X019C) 105 #define RESPLL_CON4 (APMIXED_BASE + 0X0320) 106 107 #define ETHPLL_CON0 (APMIXED_BASE + 0X0360) 108 #define ETHPLL_CON1 (APMIXED_BASE + 0X0364) 109 #define ETHPLL_CON2 (APMIXED_BASE + 0X0368) 110 #define ETHPLL_CON3 (APMIXED_BASE + 0X036C) 111 #define ETHPLL_CON4 (APMIXED_BASE + 0X0370) 112 113 #define MSDCPLL_CON0 (APMIXED_BASE + 0X0710) 114 #define MSDCPLL_CON1 (APMIXED_BASE + 0X0714) 115 #define MSDCPLL_CON2 (APMIXED_BASE + 0X0718) 116 #define MSDCPLL_CON3 (APMIXED_BASE + 0X071C) 117 #define MSDCPLL_CON4 (APMIXED_BASE + 0X0720) 118 119 #define TVDPLL1_CON0 (APMIXED_BASE + 0X00A0) 120 #define TVDPLL1_CON1 (APMIXED_BASE + 0X00A4) 121 #define TVDPLL1_CON2 (APMIXED_BASE + 0X00A8) 122 #define TVDPLL1_CON3 (APMIXED_BASE + 0X00AC) 123 #define TVDPLL1_CON4 (APMIXED_BASE + 0X00B0) 124 125 #define TVDPLL2_CON0 (APMIXED_BASE + 0X00C0) 126 #define TVDPLL2_CON1 (APMIXED_BASE + 0X00C4) 127 #define TVDPLL2_CON2 (APMIXED_BASE + 0X00C8) 128 #define TVDPLL2_CON3 (APMIXED_BASE + 0X00CC) 129 #define TVDPLL2_CON4 (APMIXED_BASE + 0X00D0) 130 131 #define MPLL_CON0 (APMIXED_BASE + 0X0800) 132 #define MPLL_CON1 (APMIXED_BASE + 0X0804) 133 #define MPLL_CON2 (APMIXED_BASE + 0X0808) 134 #define MPLL_CON3 (APMIXED_BASE + 0X080C) 135 #define MPLL_CON4 (APMIXED_BASE + 0X0810) 136 137 #define MMPLL_CON0 (APMIXED_BASE + 0X00E0) 138 #define MMPLL_CON1 (APMIXED_BASE + 0X00E4) 139 #define MMPLL_CON2 (APMIXED_BASE + 0X00E8) 140 #define MMPLL_CON3 (APMIXED_BASE + 0X00EC) 141 #define MMPLL_CON4 (APMIXED_BASE + 0X00F0) 142 143 #define MAINPLL_CON0 (APMIXED_BASE + 0X01D0) 144 #define MAINPLL_CON1 (APMIXED_BASE + 0X01D4) 145 #define MAINPLL_CON2 (APMIXED_BASE + 0X01D8) 146 #define MAINPLL_CON3 (APMIXED_BASE + 0X01DC) 147 #define MAINPLL_CON4 (APMIXED_BASE + 0X01E0) 148 149 #define VDECPLL_CON0 (APMIXED_BASE + 0X0890) 150 #define VDECPLL_CON1 (APMIXED_BASE + 0X0894) 151 #define VDECPLL_CON2 (APMIXED_BASE + 0X0898) 152 #define VDECPLL_CON3 (APMIXED_BASE + 0X089C) 153 #define VDECPLL_CON4 (APMIXED_BASE + 0X08A0) 154 155 #define IMGPLL_CON0 (APMIXED_BASE + 0X0100) 156 #define IMGPLL_CON1 (APMIXED_BASE + 0X0104) 157 #define IMGPLL_CON2 (APMIXED_BASE + 0X0108) 158 #define IMGPLL_CON3 (APMIXED_BASE + 0X010C) 159 #define IMGPLL_CON4 (APMIXED_BASE + 0X0110) 160 161 #define UNIVPLL_CON0 (APMIXED_BASE + 0X01F0) 162 #define UNIVPLL_CON1 (APMIXED_BASE + 0X01F4) 163 #define UNIVPLL_CON2 (APMIXED_BASE + 0X01F8) 164 #define UNIVPLL_CON3 (APMIXED_BASE + 0X01FC) 165 #define UNIVPLL_CON4 (APMIXED_BASE + 0X0700) 166 167 #define HDMIPLL1_CON0 (APMIXED_BASE + 0X08C0) 168 #define HDMIPLL1_CON1 (APMIXED_BASE + 0X08C4) 169 #define HDMIPLL1_CON2 (APMIXED_BASE + 0X08C8) 170 #define HDMIPLL1_CON3 (APMIXED_BASE + 0X08CC) 171 #define HDMIPLL1_CON4 (APMIXED_BASE + 0X08D0) 172 173 #define HDMIPLL2_CON0 (APMIXED_BASE + 0X0870) 174 #define HDMIPLL2_CON1 (APMIXED_BASE + 0X0874) 175 #define HDMIPLL2_CON2 (APMIXED_BASE + 0X0878) 176 #define HDMIPLL2_CON3 (APMIXED_BASE + 0X087C) 177 #define HDMIPLL2_CON4 (APMIXED_BASE + 0X0880) 178 179 #define HDMIRX_APLL_CON0 (APMIXED_BASE + 0X08E0) 180 #define HDMIRX_APLL_CON1 (APMIXED_BASE + 0X08E4) 181 #define HDMIRX_APLL_CON2 (APMIXED_BASE + 0X08E8) 182 #define HDMIRX_APLL_CON3 (APMIXED_BASE + 0X08EC) 183 #define HDMIRX_APLL_CON4 (APMIXED_BASE + 0X08F0) 184 #define HDMIRX_APLL_CON5 (APMIXED_BASE + 0X0DD4) 185 186 #define USB1PLL_CON0 (APMIXED_BASE + 0X01A0) 187 #define USB1PLL_CON1 (APMIXED_BASE + 0X01A4) 188 #define USB1PLL_CON2 (APMIXED_BASE + 0X01A8) 189 #define USB1PLL_CON3 (APMIXED_BASE + 0X01AC) 190 #define USB1PLL_CON4 (APMIXED_BASE + 0X01B0) 191 192 #define ADSPPLL_CON0 (APMIXED_BASE + 0X07E0) 193 #define ADSPPLL_CON1 (APMIXED_BASE + 0X07E4) 194 #define ADSPPLL_CON2 (APMIXED_BASE + 0X07E8) 195 #define ADSPPLL_CON3 (APMIXED_BASE + 0X07EC) 196 #define ADSPPLL_CON4 (APMIXED_BASE + 0X07F0) 197 198 #define APLL1_CON0 (APMIXED_BASE + 0X07C0) 199 #define APLL1_CON1 (APMIXED_BASE + 0X07C4) 200 #define APLL1_CON2 (APMIXED_BASE + 0X07C8) 201 #define APLL1_CON3 (APMIXED_BASE + 0X07CC) 202 #define APLL1_CON4 (APMIXED_BASE + 0X07D0) 203 #define APLL1_CON5 (APMIXED_BASE + 0X0DC0) 204 205 #define APLL2_CON0 (APMIXED_BASE + 0X0780) 206 #define APLL2_CON1 (APMIXED_BASE + 0X0784) 207 #define APLL2_CON2 (APMIXED_BASE + 0X0788) 208 #define APLL2_CON3 (APMIXED_BASE + 0X078C) 209 #define APLL2_CON4 (APMIXED_BASE + 0X0790) 210 #define APLL2_CON5 (APMIXED_BASE + 0X0DC4) 211 212 #define APLL3_CON0 (APMIXED_BASE + 0X0760) 213 #define APLL3_CON1 (APMIXED_BASE + 0X0764) 214 #define APLL3_CON2 (APMIXED_BASE + 0X0768) 215 #define APLL3_CON3 (APMIXED_BASE + 0X076C) 216 #define APLL3_CON4 (APMIXED_BASE + 0X0770) 217 #define APLL3_CON5 (APMIXED_BASE + 0X0DC8) 218 219 #define APLL4_CON0 (APMIXED_BASE + 0X0740) 220 #define APLL4_CON1 (APMIXED_BASE + 0X0744) 221 #define APLL4_CON2 (APMIXED_BASE + 0X0748) 222 #define APLL4_CON3 (APMIXED_BASE + 0X074C) 223 #define APLL4_CON4 (APMIXED_BASE + 0X0750) 224 #define APLL4_CON5 (APMIXED_BASE + 0X0DCC) 225 226 #define APLL5_CON0 (APMIXED_BASE + 0X07A0) 227 #define APLL5_CON1 (APMIXED_BASE + 0X07A4) 228 #define APLL5_CON2 (APMIXED_BASE + 0X07A8) 229 #define APLL5_CON3 (APMIXED_BASE + 0X07AC) 230 #define APLL5_CON4 (APMIXED_BASE + 0X07B0) 231 #define APLL5_CON5 (APMIXED_BASE + 0X0DD0) 232 233 #define MFGPLL_CON0 (APMIXED_BASE + 0X0340) 234 #define MFGPLL_CON1 (APMIXED_BASE + 0X0344) 235 #define MFGPLL_CON2 (APMIXED_BASE + 0X0348) 236 #define MFGPLL_CON3 (APMIXED_BASE + 0X034C) 237 #define MFGPLL_CON4 (APMIXED_BASE + 0X0350) 238 239 #define DGIPLL_CON0 (APMIXED_BASE + 0X0150) 240 #define DGIPLL_CON1 (APMIXED_BASE + 0X0154) 241 #define DGIPLL_CON2 (APMIXED_BASE + 0X0158) 242 #define DGIPLL_CON3 (APMIXED_BASE + 0X015C) 243 #define DGIPLL_CON4 (APMIXED_BASE + 0X0160) 244 245 #define APLL1_TUNER_CON0 (APMIXED_BASE + 0x0470) 246 #define APLL2_TUNER_CON0 (APMIXED_BASE + 0x0474) 247 #define APLL3_TUNER_CON0 (APMIXED_BASE + 0x0478) 248 #define APLL4_TUNER_CON0 (APMIXED_BASE + 0x047C) 249 #define APLL5_TUNER_CON0 (APMIXED_BASE + 0x0480) 250 251 /* TOPCKGEN Register */ 252 #define CLK_CFG_UPDATE (TOPCKGEN_BASE + 0x004) 253 #define CLK_CFG_UPDATE1 (TOPCKGEN_BASE + 0x008) 254 #define CLK_CFG_UPDATE2 (TOPCKGEN_BASE + 0x00C) 255 #define CLK_CFG_UPDATE3 (TOPCKGEN_BASE + 0x010) 256 #define CLK_CFG_UPDATE4 (TOPCKGEN_BASE + 0x014) 257 258 #define CLK_CFG_0_SET (TOPCKGEN_BASE + 0x024) 259 #define CLK_CFG_0_CLR (TOPCKGEN_BASE + 0x028) 260 #define CLK_CFG_1_SET (TOPCKGEN_BASE + 0x030) 261 #define CLK_CFG_1_CLR (TOPCKGEN_BASE + 0x034) 262 #define CLK_CFG_2_SET (TOPCKGEN_BASE + 0x03C) 263 #define CLK_CFG_2_CLR (TOPCKGEN_BASE + 0x040) 264 #define CLK_CFG_3_SET (TOPCKGEN_BASE + 0x048) 265 #define CLK_CFG_3_CLR (TOPCKGEN_BASE + 0x04C) 266 #define CLK_CFG_4_SET (TOPCKGEN_BASE + 0x054) 267 #define CLK_CFG_4_CLR (TOPCKGEN_BASE + 0x058) 268 #define CLK_CFG_5_SET (TOPCKGEN_BASE + 0x060) 269 #define CLK_CFG_5_CLR (TOPCKGEN_BASE + 0x064) 270 #define CLK_CFG_6_SET (TOPCKGEN_BASE + 0x06C) 271 #define CLK_CFG_6_CLR (TOPCKGEN_BASE + 0x070) 272 #define CLK_CFG_7_SET (TOPCKGEN_BASE + 0x078) 273 #define CLK_CFG_7_CLR (TOPCKGEN_BASE + 0x07C) 274 #define CLK_CFG_8_SET (TOPCKGEN_BASE + 0x084) 275 #define CLK_CFG_8_CLR (TOPCKGEN_BASE + 0x088) 276 #define CLK_CFG_9_SET (TOPCKGEN_BASE + 0x090) 277 #define CLK_CFG_9_CLR (TOPCKGEN_BASE + 0x094) 278 #define CLK_CFG_10_SET (TOPCKGEN_BASE + 0x09C) 279 #define CLK_CFG_10_CLR (TOPCKGEN_BASE + 0x0A0) 280 #define CLK_CFG_11_SET (TOPCKGEN_BASE + 0x0A8) 281 #define CLK_CFG_11_CLR (TOPCKGEN_BASE + 0x0AC) 282 #define CLK_CFG_12_SET (TOPCKGEN_BASE + 0x0B4) 283 #define CLK_CFG_12_CLR (TOPCKGEN_BASE + 0x0B8) 284 #define CLK_CFG_13_SET (TOPCKGEN_BASE + 0x0C0) 285 #define CLK_CFG_13_CLR (TOPCKGEN_BASE + 0x0C4) 286 #define CLK_CFG_14_SET (TOPCKGEN_BASE + 0x0CC) 287 #define CLK_CFG_14_CLR (TOPCKGEN_BASE + 0x0D0) 288 #define CLK_CFG_15_SET (TOPCKGEN_BASE + 0x0D8) 289 #define CLK_CFG_15_CLR (TOPCKGEN_BASE + 0x0DC) 290 #define CLK_CFG_16_SET (TOPCKGEN_BASE + 0x0E4) 291 #define CLK_CFG_16_CLR (TOPCKGEN_BASE + 0x0E8) 292 #define CLK_CFG_17_SET (TOPCKGEN_BASE + 0x0F0) 293 #define CLK_CFG_17_CLR (TOPCKGEN_BASE + 0x0F4) 294 #define CLK_CFG_18_SET (TOPCKGEN_BASE + 0x0FC) 295 #define CLK_CFG_18_CLR (TOPCKGEN_BASE + 0x0100) 296 #define CLK_CFG_19_SET (TOPCKGEN_BASE + 0x0108) 297 #define CLK_CFG_19_CLR (TOPCKGEN_BASE + 0x010C) 298 #define CLK_CFG_20_SET (TOPCKGEN_BASE + 0x0114) 299 #define CLK_CFG_20_CLR (TOPCKGEN_BASE + 0x0118) 300 #define CLK_CFG_21_SET (TOPCKGEN_BASE + 0x0120) 301 #define CLK_CFG_21_CLR (TOPCKGEN_BASE + 0x0124) 302 #define CLK_CFG_22_SET (TOPCKGEN_BASE + 0x012C) 303 #define CLK_CFG_22_CLR (TOPCKGEN_BASE + 0x0130) 304 #define CLK_CFG_23_SET (TOPCKGEN_BASE + 0x0138) 305 #define CLK_CFG_23_CLR (TOPCKGEN_BASE + 0x013C) 306 #define CLK_CFG_24_SET (TOPCKGEN_BASE + 0x0144) 307 #define CLK_CFG_24_CLR (TOPCKGEN_BASE + 0x0148) 308 #define CLK_CFG_25_SET (TOPCKGEN_BASE + 0x0150) 309 #define CLK_CFG_25_CLR (TOPCKGEN_BASE + 0x0154) 310 #define CLK_CFG_26_SET (TOPCKGEN_BASE + 0x015C) 311 #define CLK_CFG_26_CLR (TOPCKGEN_BASE + 0x0160) 312 #define CLK_CFG_27_SET (TOPCKGEN_BASE + 0x0168) 313 #define CLK_CFG_27_CLR (TOPCKGEN_BASE + 0x016C) 314 #define CLK_CFG_28_SET (TOPCKGEN_BASE + 0x0174) 315 #define CLK_CFG_28_CLR (TOPCKGEN_BASE + 0x0178) 316 #define CLK_CFG_29_SET (TOPCKGEN_BASE + 0x0180) 317 #define CLK_CFG_29_CLR (TOPCKGEN_BASE + 0x0184) 318 #define CLK_CFG_30_SET (TOPCKGEN_BASE + 0x018C) 319 #define CLK_CFG_30_CLR (TOPCKGEN_BASE + 0x0190) 320 #define CLK_CFG_31_SET (TOPCKGEN_BASE + 0x0198) 321 #define CLK_CFG_31_CLR (TOPCKGEN_BASE + 0x019C) 322 #define CLK_CFG_32_SET (TOPCKGEN_BASE + 0x01A4) 323 #define CLK_CFG_32_CLR (TOPCKGEN_BASE + 0x01A8) 324 #define CLK_CFG_33_SET (TOPCKGEN_BASE + 0x01B0) 325 #define CLK_CFG_33_CLR (TOPCKGEN_BASE + 0x01B4) 326 #define CLK_CFG_34_SET (TOPCKGEN_BASE + 0x01BC) 327 #define CLK_CFG_34_CLR (TOPCKGEN_BASE + 0x01C0) 328 #define CLK_CFG_35_SET (TOPCKGEN_BASE + 0x01C8) 329 #define CLK_CFG_35_CLR (TOPCKGEN_BASE + 0x01CC) 330 #define CLK_CFG_36_SET (TOPCKGEN_BASE + 0x01D4) 331 #define CLK_CFG_36_CLR (TOPCKGEN_BASE + 0x01D8) 332 #define CLK_CFG_37_SET (TOPCKGEN_BASE + 0x01E0) 333 #define CLK_CFG_37_CLR (TOPCKGEN_BASE + 0x01E4) 334 #define CLK_MISC_CFG_3 (TOPCKGEN_BASE + 0x0250) 335 336 #define CLK_DBG_CFG (TOPCKGEN_BASE + 0x020C) 337 #define CLK26CALI_0 (TOPCKGEN_BASE + 0x0218) 338 #define CLK26CALI_1 (TOPCKGEN_BASE + 0x021C) 339 #define CLK_MISC_CFG_0 (TOPCKGEN_BASE + 0x022C) 340 #define CLK_SCP_CFG_0 (TOPCKGEN_BASE + 0x0264) 341 342 #define INFRA_BUS_DCM_CTRL (INFRACFG_AO_BASE + 0x70) 343 #define VDNR_DCM_TOP_INFRA_CTRL0 (INFRA_AO_BCRM_BASE + 0x034) 344 345 #define TOPCKGEN_CLK_MISC_CFG_1 (TOPCKGEN_BASE + 0x238) 346 #define TOPCKGEN_CLK_MISC_CFG_3 (TOPCKGEN_BASE + 0x250) 347 #define INFRACFG_AO_MODULE_SW_CG_0_CLR (INFRACFG_AO_BASE + 0x84) 348 #define INFRACFG_AO_MODULE_SW_CG_1_CLR (INFRACFG_AO_BASE + 0x8c) 349 #define INFRACFG_AO_MODULE_SW_CG_2_CLR (INFRACFG_AO_BASE + 0xa8) 350 #define INFRACFG_AO_MODULE_SW_CG_3_CLR (INFRACFG_AO_BASE + 0xc4) 351 #define INFRACFG_AO_MODULE_SW_CG_4_CLR (INFRACFG_AO_BASE + 0xe4) 352 #define APMIXEDSYS_AP_PLL_CON2 (APMIXED_BASE + 0x8) 353 #define IPNNA_F26M_CK_CG (IPNNA_BASE + 0x104) 354 #define IPNNA_AXI_CK_CG (IPNNA_BASE + 0x110) 355 #define IPNNA_NNA0_CG_EN (IPNNA_BASE + 0x90) 356 #define IPNNA_NNA1_CG_EN (IPNNA_BASE + 0x94) 357 #define IPNNA_NNA0_EMI_CG_EN (IPNNA_BASE + 0x98) 358 #define IPNNA_NNA1_EMI_CG_EN (IPNNA_BASE + 0x9c) 359 #define IPNNA_NNA0_AXI_CG_EN (IPNNA_BASE + 0xa0) 360 #define IPNNA_NNA1_AXI_CG_EN (IPNNA_BASE + 0xa4) 361 #define SCP_PAR_TOP_AUDIODSP_CK_CG (SCP_PAR_TOP_BASE + 0x180) 362 #define AUDIO_AUDIO_TOP_0 (AUDIO_BASE + 0x0) 363 #define AUDIO_AUDIO_TOP_4 (AUDIO_BASE + 0x10) 364 #define AUDIO_AUDIO_TOP_5 (AUDIO_BASE + 0x14) 365 #define AUDIO_AUDIO_TOP_6 (AUDIO_BASE + 0x18) 366 #define AUDIO_AUDIO_TOP_1 (AUDIO_BASE + 0x4) 367 #define AUDIO_AUDIO_TOP_3 (AUDIO_BASE + 0xc) 368 #define AUDIO_SRC_MEM_ASRC_TOP_1 (AUDIO_SRC_BASE + 0x1004) 369 #define PERICFG_AO_PERI_MODULE_SW_CG_0_SET (PERICFG_AO_BASE + 0x10) 370 #define PERICFG_AO_PERI_MODULE_SW_CG_0_CLR (PERICFG_AO_BASE + 0x14) 371 #define MFGCFG_MFG_CG_CLR (MFGCFG_BASE + 0x8) 372 #define VPP0_REG_VPPSYS0_CG0_CLR (VPP0_REG_BASE + 0x28) 373 #define VPP0_REG_VPPSYS0_CG1_CLR (VPP0_REG_BASE + 0x34) 374 #define VPP0_REG_VPPSYS0_CG2_CLR (VPP0_REG_BASE + 0x40) 375 #define WPESYS_TOP_REG_WPESYS_RG_000 (WPESYS_TOP_REG_BASE + 0x0) 376 #define WPE_VPP0_CTL_WPE_DCM_DIS (WPE_VPP0_BASE + 0x58) 377 #define WPE_VPP0_CTL_DMA_DCM_DIS (WPE_VPP0_BASE + 0x5c) 378 #define WPE_VPP1_CTL_WPE_DCM_DIS (WPE_VPP1_BASE + 0x58) 379 #define WPE_VPP1_CTL_DMA_DCM_DIS (WPE_VPP1_BASE + 0x5c) 380 #define VPPSYS1_CONFIG_VPPSYS1_CG_0_CLR (VPPSYS1_CONFIG_BASE + 0x108) 381 #define VPPSYS1_CONFIG_VPPSYS1_CG_1_CLR (VPPSYS1_CONFIG_BASE + 0x118) 382 #define IMGSYS_MAIN_IMG_MAIN_CG_CLR (IMGSYS_MAIN_BASE + 0x8) 383 #define IMGSYS1_DIP_TOP_MACRO_CG_CLR (IMGSYS1_DIP_TOP_BASE + 0x8) 384 #define IMGSYS1_DIP_NR_MACRO_CG_CLR (IMGSYS1_DIP_NR_BASE + 0x8) 385 #define IMGSYS1_WPE_MACRO_CG_CLR (IMGSYS1_WPE_BASE + 0x8) 386 #define IPESYS_MACRO_CG (IPESYS_BASE + 0x0) 387 #define CAMSYS_MAIN_CAMSYS_CG_CLR (CAMSYS_MAIN_BASE + 0x8) 388 #define CAMSYS_RAWA_CAMSYS_CG_CLR (CAMSYS_RAWA_BASE + 0x8) 389 #define CAMSYS_YUVA_CAMSYS_CG_CLR (CAMSYS_YUVA_BASE + 0x8) 390 #define CAMSYS_RAWB_CAMSYS_CG_CLR (CAMSYS_RAWB_BASE + 0x8) 391 #define CAMSYS_YUVB_CAMSYS_CG_CLR (CAMSYS_YUVB_BASE + 0x8) 392 #define CAMSYS_MRAW_CAMSYS_CG_CLR (CAMSYS_MRAW_BASE + 0x8) 393 #define CCU_MAIN_CCUSYS_CG_CLR (CCU_MAIN_BASE + 0x8) 394 #define VDEC_SOC_GCON_VDEC_CKEN (VDEC_SOC_GCON_BASE + 0x0) 395 #define VDEC_SOC_GCON_LAT_CKEN (VDEC_SOC_GCON_BASE + 0x200) 396 #define VDEC_SOC_GCON_LARB_CKEN_CON (VDEC_SOC_GCON_BASE + 0x8) 397 #define VDEC_GCON_VDEC_CKEN (VDEC_GCON_BASE + 0x0) 398 #define VDEC_GCON_LAT_CKEN (VDEC_GCON_BASE + 0x200) 399 #define VDEC_GCON_LARB_CKEN_CON (VDEC_GCON_BASE + 0x8) 400 #define VDEC_CORE1_GCON_VDEC_CKEN (VDEC_CORE1_GCON_BASE + 0x0) 401 #define VDEC_CORE1_GCON_LAT_CKEN (VDEC_CORE1_GCON_BASE + 0x200) 402 #define VDEC_CORE1_GCON_LARB_CKEN_CON (VDEC_CORE1_GCON_BASE + 0x8) 403 #define VENC_GCON_VENCSYS_CG_SET (VENC_GCON_BASE + 0x4) 404 #define VENC_CORE1_GCON_VENCSYS_CG_SET (VENC_CORE1_GCON_BASE + 0x4) 405 #define VDOSYS0_CONFIG_GLOBAL0_CG_0_CLR (VDOSYS0_CONFIG_BASE + 0x108) 406 #define VDOSYS0_CONFIG_GLOBAL0_CG_1_CLR (VDOSYS0_CONFIG_BASE + 0x118) 407 #define VDOSYS0_CONFIG_GLOBAL0_CG_2_CLR (VDOSYS0_CONFIG_BASE + 0x128) 408 #define VDOSYS0_CONFIG_GLOBAL1_CG_0_CLR (VDOSYS0_CONFIG_BASE + 0x308) 409 #define VDOSYS0_CONFIG_GLOBAL1_CG_1_CLR (VDOSYS0_CONFIG_BASE + 0x318) 410 #define VDOSYS0_CONFIG_GLOBAL1_CG_2_CLR (VDOSYS0_CONFIG_BASE + 0x328) 411 #define VDOSYS1_CONFIG_VDOSYS1_CG_0_CLR (VDOSYS1_CONFIG_BASE + 0x108) 412 #define VDOSYS1_CONFIG_VDOSYS1_CG_1_CLR (VDOSYS1_CONFIG_BASE + 0x128) 413 #define VDOSYS1_CONFIG_VDOSYS1_CG_2_CLR (VDOSYS1_CONFIG_BASE + 0x138) 414 #define VDOSYS1_CONFIG_VDOSYS1_CG_3_CLR (VDOSYS1_CONFIG_BASE + 0x148) 415 416 #define AP_MDSRC_REQ (SPM_BASE + 0x43C) 417 418 /* CPU Freq Boost*/ 419 enum cpu_opp { 420 CPU_OPP0 = 0, 421 CPU_OPP1, 422 CPU_OPP2, 423 CPU_OPP3, 424 CPU_OPP4, 425 CPU_OPP5, 426 CPU_OPP_NUM, 427 }; 428 429 /* 430 * EXTERN FUNCTIONS 431 */ 432 extern unsigned int mt_get_abist_freq(unsigned int ID); 433 extern unsigned int mt_get_cpu_freq(void); 434 extern void set_armpll_ll_rate(enum cpu_opp opp); 435 extern void mt_set_topck_default(void); 436 437 #endif 438