1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _BAYTRAIL_PM_H_ 4 #define _BAYTRAIL_PM_H_ 5 6 #include <acpi/acpi.h> 7 8 #define IOCOM1 0x3f8 9 10 /* Memory mapped IO registers behind PMC_BASE_ADDRESS */ 11 #define PRSTS 0x00 12 #define PMC_WDT_STS (1 << 15) 13 #define SEC_GBLRST_STS (1 << 7) 14 #define SEC_WDT_STS (1 << 6) 15 #define WOL_OVR_WK_STS (1 << 5) 16 #define PMC_WAKE_STS (1 << 4) 17 #define PMC_CFG 0x08 18 #define SPS (1 << 5) 19 #define NO_REBOOT (1 << 4) 20 #define SX_ENT_TO_EN (1 << 3) 21 #define TIMING_T581_SHIFT (0) 22 #define TIMING_T581_MASK (3 << TIMING_T581_SHIFT) 23 #define TIMING_T581_10uS (0 << TIMING_T581_SHIFT) 24 #define TIMING_T581_100uS (1 << TIMING_T581_SHIFT) 25 #define TIMING_T581_1mS (2 << TIMING_T581_SHIFT) 26 #define TIMING_T581_10mS (3 << TIMING_T581_SHIFT) 27 #define VLV_PM_STS 0x0c 28 #define PMC_MSG_FULL_STS (1 << 24) 29 #define PMC_MSG_4_FULL_STS (1 << 23) 30 #define PMC_MSG_3_FULL_STS (1 << 22) 31 #define PMC_MSG_2_FULL_STS (1 << 21) 32 #define PMC_MSG_1_FULL_STS (1 << 20) 33 #define CODE_REQ (1 << 8) 34 #define HPR_ENT_TO (1 << 2) 35 #define SX_ENT_TO (1 << 1) 36 #define GEN_PMCON1 0x20 37 #define UART_EN (1 << 24) 38 #define DISB (1 << 23) 39 #define MEM_SR (1 << 21) 40 #define SRS (1 << 20) 41 #define CTS (1 << 19) 42 #define MS4V (1 << 18) 43 #define PWR_FLR (1 << 16) 44 #define PME_B0_S5_DIS (1 << 15) 45 #define SUS_PWR_FLR (1 << 14) 46 #define WOL_EN_OVRD (1 << 13) 47 #define DIS_SLP_X_STRCH_SUS_UP (1 << 12) 48 #define GEN_RST_STS (1 << 9) 49 #define RPS (1 << 2) 50 #define AFTERG3_EN (1 << 0) 51 #define GEN_PMCON2 0x24 52 #define SLPSX_STR_POL_LOCK (1 << 18) 53 #define BIOS_PCI_EXP_EN (1 << 10) 54 #define PWRBTN_LVL (1 << 9) 55 #define SMI_LOCK (1 << 4) 56 #define ETR 0x48 57 #define CF9LOCK (1 << 31) 58 #define LTR_DEF (1 << 22) 59 #define IGNORE_HPET (1 << 21) 60 #define CF9GR (1 << 20) 61 #define CWORWRE (1 << 18) 62 #define FUNC_DIS 0x34 63 #define SIO_DMA2_DIS (1 << 0) 64 #define PWM1_DIS (1 << 1) 65 #define PWM2_DIS (1 << 2) 66 #define HSUART1_DIS (1 << 3) 67 #define HSUART2_DIS (1 << 4) 68 #define SPI_DIS (1 << 5) 69 #define MMC_DIS (1 << 8) 70 #define SDIO_DIS (1 << 9) 71 #define SD_DIS (1 << 10) 72 #define MMC45_DIS (1 << 11) 73 #define HDA_DIS (1 << 12) 74 #define LPE_DIS (1 << 13) 75 #define OTG_DIS (1 << 14) 76 #define XHCI_DIS (1 << 15) 77 #define SATA_DIS (1 << 17) 78 #define EHCI_DIS (1 << 18) 79 #define TXE_DIS (1 << 19) 80 #define PCIE_PORT1_DIS (1 << 20) 81 #define PCIE_PORT2_DIS (1 << 21) 82 #define PCIE_PORT3_DIS (1 << 22) 83 #define PCIE_PORT4_DIS (1 << 23) 84 #define SIO_DMA1_DIS (1 << 24) 85 #define I2C1_DIS (1 << 25) 86 #define I2C2_DIS (1 << 26) 87 #define I2C3_DIS (1 << 27) 88 #define I2C4_DIS (1 << 28) 89 #define I2C5_DIS (1 << 29) 90 #define I2C6_DIS (1 << 30) 91 #define I2C7_DIS (1 << 31) 92 #define FUNC_DIS2 0x38 93 #define USH_SS_PHY_DIS (1 << 2) 94 #define OTG_SS_PHY_DIS (1 << 1) 95 #define SMBUS_DIS (1 << 0) 96 #define GPIO_ROUT 0x58 97 #define ROUTE_MASK 3 98 #define ROUTE_NONE 0 99 #define ROUTE_SMI 1 100 #define ROUTE_SCI 2 101 #define PLT_CLK_CTL_0 0x60 102 #define PLT_CLK_CTL_1 0x64 103 #define PLT_CLK_CTL_2 0x68 104 #define PLT_CLK_CTL_3 0x6c 105 #define PLT_CLK_CTL_4 0x70 106 #define PLT_CLK_CTL_5 0x74 107 #define CLK_FREQ_25MHZ (0x0 << 2) 108 #define CLK_FREQ_19P2MHZ (0x1 << 2) 109 #define CLK_CTL_D3_LPE (0x0 << 0) 110 #define CLK_CTL_ON (0x1 << 0) 111 #define CLK_CTL_OFF (0x2 << 0) 112 #define PME_STS 0xc0 113 #define GPE_LEVEL_EDGE 0xc4 114 #define GPE_EDGE 0 115 #define GPE_LEVEL 1 116 #define GPE_POLARITY 0xc8 117 #define GPE_ACTIVE_HIGH 1 118 #define GPE_ACTIVE_LOW 0 119 #define LOCK 0xcc 120 121 /* IO Mapped registers behind ACPI_BASE_ADDRESS */ 122 #define PM1_STS 0x00 123 #define WAK_STS (1 << 15) 124 #define PCIEXPWAK_STS (1 << 14) 125 #define USB_STS (1 << 13) 126 #define PRBTNOR_STS (1 << 11) 127 #define RTC_STS (1 << 10) 128 #define PWRBTN_STS (1 << 8) 129 #define GBL_STS (1 << 5) 130 #define TMROF_STS (1 << 0) 131 #define PM1_EN 0x02 132 #define PCIEXPWAK_DIS (1 << 14) 133 #define USB_WAKE_EN (1 << 13) 134 #define RTC_EN (1 << 10) 135 #define PWRBTN_EN (1 << 8) 136 #define GBL_EN (1 << 5) 137 #define TMROF_EN (1 << 0) 138 #define PM1_CNT 0x04 139 #define GBL_RLS (1 << 2) 140 #define BM_RLD (1 << 1) 141 #define SCI_EN (1 << 0) 142 #define PM1_TMR 0x08 143 #define GPE0_STS 0x20 144 #define CORE_GPIO_STS7 (1 << 31) 145 #define CORE_GPIO_STS6 (1 << 30) 146 #define CORE_GPIO_STS5 (1 << 29) 147 #define CORE_GPIO_STS4 (1 << 28) 148 #define CORE_GPIO_STS3 (1 << 27) 149 #define CORE_GPIO_STS2 (1 << 26) 150 #define CORE_GPIO_STS1 (1 << 25) 151 #define CORE_GPIO_STS0 (1 << 24) 152 #define SUS_GPIO_STS7 (1 << 23) 153 #define SUS_GPIO_STS6 (1 << 22) 154 #define SUS_GPIO_STS5 (1 << 21) 155 #define SUS_GPIO_STS4 (1 << 20) 156 #define SUS_GPIO_STS3 (1 << 19) 157 #define SUS_GPIO_STS2 (1 << 18) 158 #define SUS_GPIO_STS1 (1 << 17) 159 #define SUS_GPIO_STS0 (1 << 16) 160 #define PME_B0_STS (1 << 13) 161 #define BATLOW_STS (1 << 10) 162 #define PCI_EXP_STS (1 << 9) 163 #define PCIE_WAKE3_STS (1 << 8) 164 #define PCIE_WAKE2_STS (1 << 7) 165 #define PCIE_WAKE1_STS (1 << 6) 166 #define GUNIT_SCI_STS (1 << 5) 167 #define PUNIT_SCI_STS (1 << 4) 168 #define PCIE_WAKE0_STS (1 << 3) 169 #define SWGPE_STS (1 << 2) 170 #define HOT_PLUG_STS (1 << 1) 171 #define GPE0_EN 0x28 172 #define CORE_GPIO_EN7 (1 << 31) 173 #define CORE_GPIO_EN6 (1 << 30) 174 #define CORE_GPIO_EN5 (1 << 29) 175 #define CORE_GPIO_EN4 (1 << 28) 176 #define CORE_GPIO_EN3 (1 << 27) 177 #define CORE_GPIO_EN2 (1 << 26) 178 #define CORE_GPIO_EN1 (1 << 25) 179 #define CORE_GPIO_EN0 (1 << 24) 180 #define SUS_GPIO_EN7_BIT 23 181 #define SUS_GPIO_EN7 (1 << SUS_GPIO_EN7_BIT) 182 #define SUS_GPIO_EN6_BIT 22 183 #define SUS_GPIO_EN6 (1 << SUS_GPIO_EN6_BIT) 184 #define SUS_GPIO_EN5_BIT 21 185 #define SUS_GPIO_EN5 (1 << SUS_GPIO_EN5_BIT) 186 #define SUS_GPIO_EN4_BIT 20 187 #define SUS_GPIO_EN4 (1 << SUS_GPIO_EN4_BIT) 188 #define SUS_GPIO_EN3_BIT 19 189 #define SUS_GPIO_EN3 (1 << SUS_GPIO_EN3_BIT) 190 #define SUS_GPIO_EN2_BIT 18 191 #define SUS_GPIO_EN2 (1 << SUS_GPIO_EN2_BIT) 192 #define SUS_GPIO_EN1_BIT 17 193 #define SUS_GPIO_EN1 (1 << SUS_GPIO_EN1_BIT) 194 #define SUS_GPIO_EN0_BIT 16 195 #define SUS_GPIO_EN0 (1 << SUS_GPIO_EN0_BIT) 196 #define PME_B0_EN (1 << 13) 197 #define BATLOW_EN (1 << 10) 198 #define PCI_EXP_EN (1 << 9) 199 #define PCIE_WAKE3_EN (1 << 8) 200 #define PCIE_WAKE2_EN (1 << 7) 201 #define PCIE_WAKE1_EN (1 << 6) 202 #define PCIE_WAKE0_EN (1 << 3) 203 #define SWGPE_EN (1 << 2) 204 #define HOT_PLUG_EN (1 << 1) 205 #define _ACPI_ENABLE_WAKE_SUS_GPIO(x) SUS_GPIO_EN##x##_BIT 206 #define ACPI_ENABLE_WAKE_SUS_GPIO(x) _ACPI_ENABLE_WAKE_SUS_GPIO(x) 207 #define SMI_EN 0x30 208 #define INTEL_USB2_EN (1 << 18) /* Intel-Specific USB2 SMI logic */ 209 #define USB_EN (1 << 17) /* Legacy USB2 SMI logic */ 210 #define PERIODIC_EN (1 << 14) /* SMI on PERIODIC_STS in SMI_STS */ 211 #define TCO_EN (1 << 13) /* Enable TCO Logic (BIOSWE et al) */ 212 #define BIOS_RLS (1 << 7) /* asserts SCI on bit set */ 213 #define SWSMI_TMR_EN (1 << 6) /* start software smi timer on bit set */ 214 #define APMC_EN (1 << 5) /* Writes to APM_CNT cause SMI# */ 215 #define SLP_SMI_EN (1 << 4) /* Write to SLP_EN in PM1_CNT asserts SMI# */ 216 #define BIOS_EN (1 << 2) /* Assert SMI# on setting GBL_RLS bit */ 217 #define EOS (1 << 1) /* End of SMI (deassert SMI#) */ 218 #define GBL_SMI_EN (1 << 0) /* SMI# generation at all? */ 219 #define SMI_STS 0x34 220 #define ALT_GPIO_SMI 0x38 221 #define UPRWC 0x3c 222 # define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */ 223 #define GPE_CTRL 0x40 224 #define PM2A_CNT_BLK 0x50 225 226 #if CONFIG(TCO_SPACE_NOT_YET_SPLIT) 227 #define TCO_RLD 0x60 228 #define TCO_STS 0x64 229 #define TCO1_32_STS_SECOND_TO_STS (1 << 17) 230 #define TCO_TIMEOUT (1 << 3) 231 #define TCO1_CNT 0x68 232 #define TCO_LOCK (1 << 12) 233 #define TCO_TMR_HALT (1 << 11) 234 #define TCO_TMR 0x70 235 #endif 236 237 /* I/O ports */ 238 #define RST_CNT 0xcf9 239 #define FULL_RST (1 << 3) 240 #define RST_CPU (1 << 2) 241 #define SYS_RST (1 << 1) 242 243 #if !defined(__ASSEMBLER__) && !defined(__ACPI__) 244 245 /* Track power state from reset to log events. */ 246 struct chipset_power_state { 247 uint16_t pm1_sts; 248 uint16_t pm1_en; 249 uint32_t pm1_cnt; 250 uint32_t gpe0_sts; 251 uint32_t gpe0_en; 252 uint32_t tco_sts; 253 uint32_t prsts; 254 uint32_t gen_pmcon1; 255 uint32_t gen_pmcon2; 256 } __packed; 257 258 /* Power Management Utility Functions. */ 259 uint16_t get_pmbase(void); 260 uint32_t clear_smi_status(void); 261 uint16_t clear_pm1_status(void); 262 uint32_t clear_tco_status(void); 263 uint32_t clear_gpe_status(void); 264 uint32_t clear_alt_status(void); 265 void clear_pmc_status(void); 266 void enable_smi(uint32_t mask); 267 void disable_smi(uint32_t mask); 268 void enable_pm1(uint16_t events); 269 void enable_pm1_control(uint32_t mask); 270 void disable_pm1_control(uint32_t mask); 271 void enable_gpe(uint32_t mask); 272 void disable_gpe(uint32_t mask); 273 void disable_all_gpe(void); 274 275 void southcluster_log_state(void); 276 277 /* Return non-zero when RTC failure happened. */ 278 int rtc_failure(void); 279 280 #endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */ 281 282 #endif /* _BAYTRAIL_PM_H_ */ 283