1# SPDX-License-Identifier: GPL-2.0-only 2 3config SOC_INTEL_DENVERTON_NS 4 bool 5 select ARCH_X86 6 select BOOT_DEVICE_SUPPORTS_WRITES 7 select CACHE_MRC_SETTINGS 8 select CPU_INTEL_COMMON 9 select CPU_INTEL_FIRMWARE_INTERFACE_TABLE 10 select CPU_SUPPORTS_PM_TIMER_EMULATION 11 select DEBUG_GPIO 12 select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 13 select FSP_M_XIP 14 select FSP_T_XIP if FSP_CAR 15 select HAVE_INTEL_FSP_REPO 16 select HAVE_SMI_HANDLER 17 select INTEL_DESCRIPTOR_MODE_CAPABLE 18 select PCR_COMMON_IOSF_1_0 19 select PLATFORM_USES_FSP2_0 20 select SOC_INTEL_COMMON 21 select SOC_INTEL_COMMON_RESET 22 select SOC_INTEL_COMMON_BLOCK 23 select SOC_INTEL_COMMON_BLOCK_CPU 24 select SOC_INTEL_COMMON_BLOCK_ACPI 25 select SOC_INTEL_COMMON_BLOCK_PMC 26 select ACPI_INTEL_HARDWARE_SLEEP_VALUES 27 select SOC_INTEL_COMMON_BLOCK_SPI 28 select SOC_INTEL_COMMON_BLOCK_FAST_SPI 29 select SOC_INTEL_COMMON_BLOCK_GPIO 30 select SOC_INTEL_COMMON_BLOCK_PCR 31 select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE 32 select SOC_INTEL_COMMON_BLOCK_SMBUS 33 select SUPPORT_CPU_UCODE_IN_CBFS 34 select SOUTHBRIDGE_INTEL_COMMON_SMBUS 35 select TSC_MONOTONIC_TIMER 36 select TSC_SYNC_MFENCE 37 select UDELAY_TSC 38 select UDK_2017_BINDING 39 select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM 40 select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT 41 select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE 42 help 43 Intel Denverton-NS SoC support 44 45if SOC_INTEL_DENVERTON_NS 46 47config CPU_INTEL_NUM_FIT_ENTRIES 48 int 49 default 1 50 51config ECAM_MMCONF_BASE_ADDRESS 52 default 0xe0000000 53 54config ECAM_MMCONF_BUS_NUMBER 55 int 56 default 256 57 58config FSP_HEADER_PATH 59 default "3rdparty/fsp/DenvertonNSFspBinPkg/Include/" 60 61config FSP_FD_PATH 62 default "3rdparty/fsp/DenvertonNSFspBinPkg/FspBin/DenvertonNSFsp.fd" 63 64# CAR memory layout on DENVERTON_NS hardware: 65## CAR base address - 0xfef00000 66## CAR size 1MB - 0x100 (0xfff00) 67## coreboot usage: 68## DCACHE base - 0xfef00000 69## DCACHE size - 0xb0000 70## FSP usage: 71## FSP base - 0xfefb0000 72## FSP size - 0x50000 - 0x100 (0x4ff00) 73config MAX_CPUS 74 int 75 default 16 76 77config PCR_BASE_ADDRESS 78 hex 79 default 0xfd000000 80 help 81 This option allows you to select MMIO Base Address of sideband bus. 82 83config DCACHE_RAM_BASE 84 hex 85 default 0xfef00000 86 87config DCACHE_RAM_SIZE 88 hex 89 default 0xb0000 if FSP_CAR 90 default 0x100000 if !FSP_CAR 91 92config DCACHE_BSP_STACK_SIZE 93 hex 94 default 0x10000 95 96config CPU_BCLK_MHZ 97 int 98 default 100 99 100config CPU_XTAL_HZ 101 default 24000000 102 103config SMM_TSEG_SIZE 104 hex 105 default 0x200000 106 107config SMM_RESERVED_SIZE 108 hex 109 default 0x000000 110 111config IQAT_ENABLE 112 bool "Enable IQAT" 113 default y 114 115config HSUART_DEV 116 hex 117 default 0x1a 118 119choice 120 prompt "UART mode selection" 121 default NON_LEGACY_UART_MODE 122 123config NON_LEGACY_UART_MODE 124 bool "Non Legacy Mode" 125 help 126 Disable legacy UART mode 127 128config LEGACY_UART_MODE 129 bool "Legacy Mode" 130 help 131 Enable legacy UART mode 132 select CONSOLE_SERIAL 133 select DRIVERS_UART 134 select DRIVERS_UART_8250IO 135endchoice 136 137config ENABLE_HSUART 138 depends on NON_LEGACY_UART_MODE 139 bool "Enable High-speed UART debug port selected by UART_FOR_CONSOLE." 140 default n 141 select CONSOLE_SERIAL 142 select DRIVERS_UART 143 select DRIVERS_UART_8250MEM 144 145config CONSOLE_UART_BASE_ADDRESS 146 depends on ENABLE_HSUART 147 hex "MMIO base address for UART" 148 default 0xd4000000 149 150choice 151 prompt "Cache-as-ram implementation" 152 default USE_DENVERTON_NS_CAR_NEM_ENHANCED 153 help 154 This option allows you to select how cache-as-ram (CAR) is set up. 155 156config USE_DENVERTON_NS_CAR_NEM_ENHANCED 157 bool "Enhanced Non-evict mode" 158 select SOC_INTEL_COMMON_BLOCK_CAR 159 select INTEL_CAR_NEM_ENHANCED 160 help 161 A current limitation of NEM (Non-Evict mode) is that code and data sizes 162 are derived from the requirement to not write out any modified cache line. 163 With NEM, if there is no physical memory behind the cached area, 164 the modified data will be lost and NEM results will be inconsistent. 165 ENHANCED NEM guarantees that modified data is always 166 kept in cache while clean data is replaced. 167 168config USE_DENVERTON_NS_FSP_CAR 169 bool "Use FSP CAR" 170 select FSP_CAR 171 help 172 Use FSP APIs to initialize and tear down the Cache-As-Ram. 173 174endchoice 175 176config IFD_CHIPSET 177 string 178 default "dnv" 179 180endif ## SOC_INTEL_DENVERTON_NS 181