1## SPDX-License-Identifier: GPL-2.0-only 2 3config SOC_INTEL_ELKHARTLAKE 4 bool 5 select ACPI_INTEL_HARDWARE_SLEEP_VALUES 6 select ARCH_X86 7 select BOOT_DEVICE_SUPPORTS_WRITES 8 select CACHE_MRC_SETTINGS 9 select CPU_INTEL_COMMON 10 select CPU_INTEL_FIRMWARE_INTERFACE_TABLE 11 select CPU_SUPPORTS_PM_TIMER_EMULATION 12 select DISPLAY_FSP_VERSION_INFO 13 select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 14 select FSP_COMPRESS_FSP_S_LZ4 15 select FSP_M_XIP 16 select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 17 select GENERIC_GPIO_LIB 18 select HAVE_FSP_GOP 19 select HAVE_SMI_HANDLER 20 select IDT_IN_EVERY_STAGE 21 select INTEL_CAR_NEM 22 select INTEL_DESCRIPTOR_MODE_CAPABLE 23 select INTEL_GMA_ACPI 24 select INTEL_GMA_ADD_VBT if RUN_FSP_GOP 25 select MP_SERVICES_PPI_V1 26 select MRC_SETTINGS_PROTECT 27 select NEED_SMALL_2MB_PAGE_TABLES 28 select PARALLEL_MP_AP_WORK 29 select PLATFORM_USES_FSP2_1 30 select PMC_GLOBAL_RESET_ENABLE_LOCK 31 select SOC_INTEL_COMMON 32 select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE 33 select SOC_INTEL_COMMON_BLOCK 34 select SOC_INTEL_COMMON_BLOCK_ACPI 35 select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC 36 select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO 37 select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT 38 select SOC_INTEL_COMMON_BLOCK_ACPI_PEP 39 select SOC_INTEL_COMMON_BLOCK_CAR 40 select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG 41 select SOC_INTEL_COMMON_BLOCK_CPU 42 select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT 43 select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE 44 select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT 45 select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 46 select SOC_INTEL_COMMON_BLOCK_HDA 47 select HAVE_INTEL_FSP_REPO 48 select HECI_DISABLE_USING_SMM if DISABLE_HECI1_AT_PRE_BOOT 49 select SOC_INTEL_COMMON_BLOCK_ME_SPEC_15 50 select SOC_INTEL_COMMON_BLOCK_PMC_EPOC 51 select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT 52 select SOC_INTEL_COMMON_BLOCK_SA 53 select SOC_INTEL_COMMON_BLOCK_SCS 54 select SOC_INTEL_COMMON_BLOCK_SMM 55 select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP 56 select SOC_INTEL_COMMON_FSP_RESET 57 select SOC_INTEL_COMMON_PCH_CLIENT 58 select SOC_INTEL_COMMON_RESET 59 select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION 60 select SSE2 61 select SUPPORT_CPU_UCODE_IN_CBFS 62 select TSC_MONOTONIC_TIMER 63 select UDELAY_TSC 64 select UDK_202005_BINDING 65 select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM 66 select SOC_INTEL_RAPL_DISABLE_VIA_MCHBAR 67 select X86_CLFLUSH_CAR 68 help 69 Intel Elkhartlake support 70 71if SOC_INTEL_ELKHARTLAKE 72 73config MAX_CPUS 74 int 75 default 4 76 77config DCACHE_RAM_BASE 78 default 0xfef00000 79 80config DCACHE_RAM_SIZE 81 default 0xc0000 82 help 83 The size of the cache-as-ram region required during bootblock 84 and/or romstage. 85 86config DCACHE_BSP_STACK_SIZE 87 hex 88 default 0x30400 89 help 90 The amount of anticipated stack usage in CAR by bootblock and 91 other stages. In the case of FSP_USES_CB_STACK default value will be 92 sum of FSP-M stack requirement (192KiB) and CB romstage stack requirement (~1KiB). 93 94config FSP_TEMP_RAM_SIZE 95 hex 96 default 0x40000 97 help 98 The amount of anticipated heap usage in CAR by FSP. 99 Refer to Platform FSP integration guide document to know 100 the exact FSP requirement for Heap setup. 101 102config IFD_CHIPSET 103 string 104 default "ehl" 105 106config IED_REGION_SIZE 107 hex 108 default 0x0 109 110config MAX_ROOT_PORTS 111 int 112 default 7 113 114config MAX_SATA_PORTS 115 int 116 default 2 117 118config MAX_PCIE_CLOCK_SRC 119 int 120 default 6 121 122config SMM_TSEG_SIZE 123 hex 124 default 0x1000000 125 126config SMM_RESERVED_SIZE 127 hex 128 default 0x200000 129 130config PCR_BASE_ADDRESS 131 hex 132 default 0xfd000000 133 help 134 This option allows you to select MMIO Base Address of sideband bus. 135 136config ECAM_MMCONF_BASE_ADDRESS 137 default 0xc0000000 138 139config CPU_BCLK_MHZ 140 int 141 default 100 142 143config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ 144 int 145 default 120 146 147config CPU_XTAL_HZ 148 default 38400000 149 150config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ 151 int 152 default 100 153 154config SOC_INTEL_COMMON_BLOCK_GSPI_MAX 155 int 156 default 3 157 158config SOC_INTEL_I2C_DEV_MAX 159 int 160 default 8 161 162config SOC_INTEL_UART_DEV_MAX 163 int 164 default 3 165 166config CONSOLE_UART_BASE_ADDRESS 167 hex 168 default 0xfe042000 169 depends on INTEL_LPSS_UART_FOR_CONSOLE 170 171# Clock divider parameters for 115200 baud rate 172# Baudrate = (UART source clock * M) /(N *16) 173# EHL UART source clock: 100MHz 174config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL 175 hex 176 default 0x25a 177 178config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL 179 hex 180 default 0x7fff 181 182config VBOOT 183 select VBOOT_MUST_REQUEST_DISPLAY 184 select VBOOT_STARTS_IN_BOOTBLOCK 185 186config CBFS_SIZE 187 default 0x200000 188 189config FSP_HEADER_PATH 190 default "3rdparty/fsp/ElkhartLakeFspBinPkg/Include/" 191 192config FSP_FD_PATH 193 string 194 depends on FSP_USE_REPO 195 default "3rdparty/fsp/ElkhartLakeFspBinPkg/FspBin/FSPRel.bin" 196 197config PSE_ENABLE 198 bool "Enable PSE ARM controller" 199 help 200 Enable PSE IP. The PSE describes the integrated programmable 201 service engine that is designed together with x86 Atom cores 202 as an Asymmetric Multi-Processing (AMP) system. 203 204config ADD_PSE_IMAGE_TO_CBFS 205 bool "Add PSE Firmware to CBFS" 206 depends on PSE_ENABLE 207 default n 208 help 209 PSE FW binary is required to use PSE dedicated peripherals from 210 x86 subsystem. Once PSE is enabled, the FW will be loaded from 211 CBFS by FSP and executed. 212 213config PSE_IMAGE_FILE 214 string "PSE binary path and filename" 215 depends on ADD_PSE_IMAGE_TO_CBFS 216 help 217 The path and filename of the PSE binary. 218 219config PSE_FW_FILE_SIZE_KIB 220 hex "Memory buffer (KiB) for PSE FW image" 221 depends on ADD_PSE_IMAGE_TO_CBFS 222 default 0x200 223 help 224 It is recommended to allocate at least 512 KiB for PSE FW. 225 226config PSE_CONFIG_BUFFER_SIZE_KIB 227 hex "Memory buffer (KiB) for PSE config data" 228 depends on ADD_PSE_IMAGE_TO_CBFS 229 default 0x100 230 help 231 It is recommended to allocate at least 256 KiB for PSE config 232 data (FSP will append PSE config data to memory region right 233 after PSE FW memory region). 234 235config EHL_TSN_DRIVER 236 bool 237 default n 238 help 239 Enable TSN GbE driver to provide board specific settings in the GBE MAC. 240 As an example of a possible change, the MAC address could be adjusted. 241 242config SOC_INTEL_ELKHARTLAKE_DEBUG_CONSENT 243 int "Debug Consent for EHL" 244 # USB DBC is more common for developers so make this default to 3 if 245 # SOC_INTEL_DEBUG_CONSENT=y 246 default 3 if SOC_INTEL_DEBUG_CONSENT 247 default 0 248 help 249 This is to control debug interface on SOC. 250 Setting non-zero value will allow to use DBC or DCI to debug SOC. 251 PlatformDebugConsent in FspmUpd.h has the details. 252 253 Desired platform debug type are 254 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), 255 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), 256 6:Enable (2-wire DCI OOB), 7:Manual 257 258config PRERAM_CBMEM_CONSOLE_SIZE 259 hex 260 default 0x1400 261 262config SOC_INTEL_ELKHARTLAKE_TCO_NO_REBOOT_EN 263 bool "Disable reset on second TCO expiration" 264 depends on SOC_INTEL_COMMON_BLOCK_TCO 265 default n 266 help 267 Setting this option will prevent a host reset if the TCO timer expires 268 for the second time. Since this feature is not exposed to the OS in the 269 standard TCO interface, this setting can be enabled on firmware level. 270 This might be useful depending on the TCO policy. 271 272config DIMM_SPD_SIZE 273 default 512 274 275endif 276