1# SPDX-License-Identifier: GPL-2.0-only 2 3# TODO: Evaluate what can be moved to a common directory 4# TODO: Update for Glinda 5 6config SOC_AMD_GLINDA 7 bool 8 select ACPI_SOC_NVS 9 select ARCH_X86 10 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH 11 select DRIVERS_USB_ACPI 12 select DRIVERS_USB_PCI_XHCI 13 select FSP_COMPRESS_FSP_M_LZMA if !ASYNC_FILE_LOADING 14 select FSP_COMPRESS_FSP_M_LZ4 if ASYNC_FILE_LOADING 15 select FSP_COMPRESS_FSP_S_LZ4 16 select GENERIC_GPIO_LIB 17 select HAVE_ACPI_TABLES 18 select HAVE_CF9_RESET 19 select HAVE_EM100_SUPPORT 20 select HAVE_FSP_GOP 21 select HAVE_SMI_HANDLER 22 select IDT_IN_EVERY_STAGE 23 select PARALLEL_MP_AP_WORK 24 select PLATFORM_USES_FSP2_0 25 select PROVIDES_ROM_SHARING 26 select PSP_SUPPORTS_EFS2_RELATIVE_ADDR if VBOOT_STARTS_BEFORE_BOOTBLOCK 27 select PSP_VERSTAGE_CCP_DMA if VBOOT_STARTS_BEFORE_BOOTBLOCK 28 select RESET_VECTOR_IN_RAM 29 select RTC 30 select SOC_AMD_COMMON 31 select SOC_AMD_COMMON_BLOCK_ACP_GEN2 # TODO: Check if this is still correct 32 select SOC_AMD_COMMON_BLOCK_ACPI # TODO: Check if this is still correct 33 select SOC_AMD_COMMON_BLOCK_ACPIMMIO # TODO: Check if this is still correct 34 select SOC_AMD_COMMON_BLOCK_ACPI_ALIB # TODO: Check if this is still correct 35 select SOC_AMD_COMMON_BLOCK_ACPI_CPPC # TODO: Check if this is still correct 36 select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE 37 select SOC_AMD_COMMON_BLOCK_ACPI_GPIO # TODO: Check if this is still correct 38 select SOC_AMD_COMMON_BLOCK_ACPI_IVRS # TODO: Check if this is still correct 39 select SOC_AMD_COMMON_BLOCK_ACPI_MADT 40 select SOC_AMD_COMMON_BLOCK_AOAC # TODO: Check if this is still correct 41 select SOC_AMD_COMMON_BLOCK_APOB # TODO: Check if this is still correct 42 select SOC_AMD_COMMON_BLOCK_APOB_HASH # TODO: Check if this is still correct 43 select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS # TODO: Check if this is still correct 44 select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH 45 select SOC_AMD_COMMON_BLOCK_DATA_FABRIC 46 select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN 47 select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_MULTI_PCI_SEGMENT 48 select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES # TODO: Check if this is still correct 49 select SOC_AMD_COMMON_BLOCK_GPP_CLK 50 select SOC_AMD_COMMON_BLOCK_GRAPHICS # TODO: Check if this is still correct 51 select SOC_AMD_COMMON_BLOCK_HAS_ESPI # TODO: Check if this is still correct 52 select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE # TODO: Check if this is still correct 53 select SOC_AMD_COMMON_BLOCK_I2C # TODO: Check if this is still correct 54 select SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL # TODO: Check if this is still correct 55 select SOC_AMD_COMMON_BLOCK_IOMMU # TODO: Check if this is still correct 56 select SOC_AMD_COMMON_BLOCK_LPC # TODO: Check if this is still correct 57 select SOC_AMD_COMMON_BLOCK_MCAX # TODO: Check if this is still correct 58 select SOC_AMD_COMMON_BLOCK_NONCAR # TODO: Check if this is still correct 59 select SOC_AMD_COMMON_BLOCK_PCI # TODO: Check if this is still correct 60 select SOC_AMD_COMMON_BLOCK_PCI_MMCONF # TODO: Check if this is still correct 61 select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER # TODO: Check if this is still correct 62 select SOC_AMD_COMMON_BLOCK_PM # TODO: Check if this is still correct 63 select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE # TODO: Check if this is still correct 64 select SOC_AMD_COMMON_BLOCK_PSP_GEN2 # TODO: Check if this is still correct 65 select SOC_AMD_COMMON_BLOCK_PSP_SPL 66 select SOC_AMD_COMMON_BLOCK_RESET 67 select SOC_AMD_COMMON_BLOCK_SMBUS # TODO: Check if this is still correct 68 select SOC_AMD_COMMON_BLOCK_SMI # TODO: Check if this is still correct 69 select SOC_AMD_COMMON_BLOCK_SMM # TODO: Check if this is still correct 70 select SOC_AMD_COMMON_BLOCK_SMU # TODO: Check if this is still correct 71 select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY # TODO: Check if this is still correct 72 select SOC_AMD_COMMON_BLOCK_SPI # TODO: Check if this is still correct 73 select SOC_AMD_COMMON_BLOCK_SVI3 74 select SOC_AMD_COMMON_BLOCK_TSC 75 select SOC_AMD_COMMON_BLOCK_UART # TODO: Check if this is still correct 76 select SOC_AMD_COMMON_BLOCK_UCODE # TODO: Check if this is still correct 77 select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB # TODO: Check if this is still correct 78 select SOC_AMD_COMMON_FSP_DMI_TABLES # TODO: Check if this is still correct 79 select SOC_AMD_COMMON_FSP_PCIE_CLK_REQ 80 select SOC_AMD_COMMON_FSP_PCI # TODO: Check if this is still correct 81 select SOC_AMD_COMMON_FSP_PRELOAD_FSPS 82 select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP 83 select SSE2 84 select UDK_2017_BINDING 85 select USE_DDR5 86 select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM 87 select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT 88 select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE 89 select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK 90 select X86_AMD_FIXED_MTRRS 91 select X86_INIT_NEED_1_SIPI 92 help 93 AMD Glinda support 94 95if SOC_AMD_GLINDA 96 97config CHIPSET_DEVICETREE 98 string 99 default "soc/amd/glinda/chipset.cb" 100 101config EARLY_RESERVED_DRAM_BASE 102 hex 103 default 0x2000000 104 help 105 This variable defines the base address of the DRAM which is reserved 106 for usage by coreboot in early stages (i.e. before ramstage is up). 107 This memory gets reserved in BIOS tables to ensure that the OS does 108 not use it, thus preventing corruption of OS memory in case of S3 109 resume. 110 111config EARLYRAM_BSP_STACK_SIZE 112 hex 113 default 0x1000 114 115config PSP_APOB_DRAM_ADDRESS 116 hex 117 default 0x2001000 118 help 119 Location in DRAM where the PSP will copy the AGESA PSP Output 120 Block. 121 122config PSP_APOB_DRAM_SIZE 123 hex 124 default 0x1E000 125 126config PSP_SHAREDMEM_BASE 127 hex 128 default 0x201F000 if VBOOT 129 default 0x0 130 help 131 This variable defines the base address in DRAM memory where PSP copies 132 the vboot workbuf. This is used in the linker script to have a static 133 allocation for the buffer as well as for adding relevant entries in 134 the BIOS directory table for the PSP. 135 136config PSP_SHAREDMEM_SIZE 137 hex 138 default 0x8000 if VBOOT 139 default 0x0 140 help 141 Sets the maximum size for the PSP to pass the vboot workbuf and 142 any logs or timestamps back to coreboot. This will be copied 143 into main memory by the PSP and will be available when the x86 is 144 started. The workbuf's base depends on the address of the reset 145 vector. 146 147config PRE_X86_CBMEM_CONSOLE_SIZE 148 hex 149 default 0x1600 150 help 151 Size of the CBMEM console used in PSP verstage. 152 153config PRERAM_CBMEM_CONSOLE_SIZE 154 hex 155 default 0x1600 156 help 157 Increase this value if preram cbmem console is getting truncated 158 159config CBFS_MCACHE_SIZE 160 hex 161 default 0x2000 if VBOOT_STARTS_BEFORE_BOOTBLOCK 162 163config C_ENV_BOOTBLOCK_SIZE 164 hex 165 default 0x20000 166 help 167 Sets the size of the bootblock stage that should be loaded in DRAM. 168 This variable controls the DRAM allocation size in linker script 169 for bootblock stage. 170 171config ROMSTAGE_ADDR 172 hex 173 default 0x2050000 174 help 175 Sets the address in DRAM where romstage should be loaded. 176 177config ROMSTAGE_SIZE 178 hex 179 default 0x70000 180 help 181 Sets the size of DRAM allocation for romstage in linker script. 182 183config FSP_M_ADDR 184 hex 185 default 0x20C0000 186 help 187 Sets the address in DRAM where FSP-M should be loaded. cbfstool 188 performs relocation of FSP-M to this address. 189 190config FSP_M_SIZE 191 hex 192 default 0xC0000 193 help 194 Sets the size of DRAM allocation for FSP-M in linker script. 195 196config FSP_TEMP_RAM_SIZE 197 hex 198 default 0x40000 199 help 200 The amount of coreboot-allocated heap and stack usage by the FSP. 201 202config VERSTAGE_ADDR 203 hex 204 depends on VBOOT_SEPARATE_VERSTAGE 205 default 0x2180000 206 help 207 Sets the address in DRAM where verstage should be loaded if running 208 as a separate stage on x86. 209 210config VERSTAGE_SIZE 211 hex 212 depends on VBOOT_SEPARATE_VERSTAGE 213 default 0x80000 214 help 215 Sets the size of DRAM allocation for verstage in linker script if 216 running as a separate stage on x86. 217 218config ASYNC_FILE_LOADING 219 bool "Loads files from SPI asynchronously" 220 select COOP_MULTITASKING 221 select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA 222 select CBFS_PRELOAD 223 help 224 When enabled, the platform will use the LPC SPI DMA controller to 225 asynchronously load contents from the SPI ROM. This will improve 226 boot time because the CPUs can be performing useful work while the 227 SPI contents are being preloaded. 228 229config CBFS_CACHE_SIZE 230 hex 231 default 0x40000 if CBFS_PRELOAD 232 233config RO_REGION_ONLY 234 string 235 depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A 236 default "apu/amdfw" 237 238config ECAM_MMCONF_BASE_ADDRESS 239 default 0xE0000000 240 241config ECAM_MMCONF_BUS_NUMBER 242 default 256 243 244config MAX_CPUS 245 int 246 default 24 247 help 248 Maximum number of threads the platform can have. 249 250config CONSOLE_UART_BASE_ADDRESS 251 depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART 252 hex 253 default 0xfedc9000 if UART_FOR_CONSOLE = 0 254 default 0xfedca000 if UART_FOR_CONSOLE = 1 255 default 0xfedce000 if UART_FOR_CONSOLE = 2 256 default 0xfedcf000 if UART_FOR_CONSOLE = 3 257 default 0xfedd1000 if UART_FOR_CONSOLE = 4 258 259config SMM_TSEG_SIZE 260 hex 261 default 0x800000 if HAVE_SMI_HANDLER 262 default 0x0 263 264config SMM_RESERVED_SIZE 265 hex 266 default 0x180000 267 268config SMM_MODULE_STACK_SIZE 269 hex 270 default 0x800 271 272config ACPI_BERT 273 bool "Build ACPI BERT Table" 274 default y 275 depends on HAVE_ACPI_TABLES 276 help 277 Report Machine Check errors identified in POST to the OS in an 278 ACPI Boot Error Record Table. 279 280config ACPI_BERT_SIZE 281 hex 282 default 0x4000 if ACPI_BERT 283 default 0x0 284 help 285 Specify the amount of DRAM reserved for gathering the data used to 286 generate the ACPI table. 287 288config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ 289 int 290 default 150 291 292config DISABLE_SPI_FLASH_ROM_SHARING 293 def_bool n 294 help 295 Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin 296 which indicates a board level ROM transaction request. This 297 removes arbitration with board and assumes the chipset controls 298 the SPI flash bus entirely. 299 300config DISABLE_KEYBOARD_RESET_PIN 301 bool 302 help 303 Instruct the SoC to not to reset based on the state of GPIO_21, KBDRST_L. 304 305menu "PSP Configuration Options" 306 307config AMDFW_CONFIG_FILE 308 string "AMD PSP Firmware config file" 309 default "src/soc/amd/glinda/fw.cfg" 310 help 311 Specify the path/location of AMD PSP Firmware config file. 312 313config PSP_DISABLE_POSTCODES 314 bool "Disable PSP post codes" 315 help 316 Disables the output of port80 post codes from PSP. 317 318config PSP_POSTCODES_ON_ESPI 319 bool "Use eSPI bus for PSP post codes" 320 default y 321 depends on !PSP_DISABLE_POSTCODES 322 help 323 Select to send PSP port80 post codes on eSPI bus. 324 If not selected, PSP port80 codes will be sent on LPC bus. 325 326config PSP_LOAD_MP2_FW 327 bool 328 default n 329 help 330 Include the MP2 firmwares and configuration into the PSP build. 331 332 If unsure, answer 'n' 333 334config PSP_UNLOCK_SECURE_DEBUG 335 bool "Unlock secure debug" 336 default y 337 help 338 Select this item to enable secure debug options in PSP. 339 340config HAVE_PSP_WHITELIST_FILE 341 bool "Include a debug whitelist file in PSP build" 342 default n 343 help 344 Support secured unlock prior to reset using a whitelisted 345 serial number. This feature requires a signed whitelist image 346 and bootloader from AMD. 347 348 If unsure, answer 'n' 349 350config PSP_WHITELIST_FILE 351 string "Debug whitelist file path" 352 depends on HAVE_PSP_WHITELIST_FILE 353 default "site-local/3rdparty/amd_blobs/glinda/PSP/wtl-mrg.sbin" 354 355config PSP_SOFTFUSE_BITS 356 string "PSP Soft Fuse bits to enable" 357 default "34 28 6" 358 help 359 Space separated list of Soft Fuse bits to enable. 360 Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG) 361 Bit 7: Disable PSP postcodes on Renoir and newer chips only 362 (Set by PSP_DISABLE_PORT80) 363 Bit 15: PSP debug output destination: 364 0=SoC MMIO UART, 1=IO port 0x3F8 365 Bit 29: Disable MP2 firmware loading (Set by PSP_LOAD_MP2_FW) 366 367 See #55758 (NDA) for additional bit definitions. 368 369config PSP_VERSTAGE_FILE 370 string "Specify the PSP_verstage file path" 371 depends on VBOOT_STARTS_BEFORE_BOOTBLOCK 372 default "\$(obj)/psp_verstage.bin" 373 help 374 Add psp_verstage file to the build & PSP Directory Table 375 376config PSP_VERSTAGE_SIGNING_TOKEN 377 string "Specify the PSP_verstage Signature Token file path" 378 depends on VBOOT_STARTS_BEFORE_BOOTBLOCK 379 default "" 380 help 381 Add psp_verstage signature token to the build & PSP Directory Table 382 383endmenu 384 385config VBOOT 386 select VBOOT_VBNV_CMOS 387 select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH 388 389config VBOOT_STARTS_BEFORE_BOOTBLOCK 390 def_bool n 391 depends on VBOOT 392 select ARCH_VERSTAGE_ARMV7 393 help 394 Runs verstage on the PSP. Only available on 395 certain ChromeOS branded parts from AMD. 396 397config VBOOT_HASH_BLOCK_SIZE 398 hex 399 default 0x9000 400 depends on VBOOT_STARTS_BEFORE_BOOTBLOCK 401 help 402 Because the bulk of the time in psp_verstage to hash the RO cbfs is 403 spent in the overhead of doing svc calls, increasing the hash block 404 size significantly cuts the verstage hashing time as seen below. 405 406 4k takes 180ms 407 16k takes 44ms 408 32k takes 33.7ms 409 36k takes 32.5ms 410 There's actually still room for an even bigger stack, but we've 411 reached a point of diminishing returns. 412 413config CMOS_RECOVERY_BYTE 414 hex 415 default 0x51 416 depends on VBOOT_STARTS_BEFORE_BOOTBLOCK 417 help 418 If the workbuf is not passed from the PSP to coreboot, set the 419 recovery flag and reboot. The PSP will read this byte, mark the 420 recovery request in VBNV, and reset the system into recovery mode. 421 422 This is the byte before the default first byte used by VBNV 423 (0x26 + 0x0E - 1) 424 425if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK 426 427config RWA_REGION_ONLY 428 string 429 default "apu/amdfw_a" 430 help 431 Add a space-delimited list of filenames that should only be in the 432 RW-A section. 433 434config RWB_REGION_ONLY 435 string 436 default "apu/amdfw_b" 437 help 438 Add a space-delimited list of filenames that should only be in the 439 RW-B section. 440 441endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK 442 443endif # SOC_AMD_GLINDA 444