1## SPDX-License-Identifier: GPL-2.0-only 2 3config SOC_INTEL_TIGERLAKE 4 bool 5 select ACPI_INTEL_HARDWARE_SLEEP_VALUES 6 select ARCH_X86 7 select BOOT_DEVICE_SUPPORTS_WRITES 8 select CACHE_MRC_SETTINGS 9 select CPU_INTEL_COMMON 10 select CPU_INTEL_FIRMWARE_INTERFACE_TABLE 11 select CPU_SUPPORTS_INTEL_TME 12 select CPU_SUPPORTS_PM_TIMER_EMULATION 13 select DEFAULT_SOFTWARE_CONNECTION_MANAGER if MAINBOARD_HAS_CHROMEOS 14 select DISPLAY_FSP_VERSION_INFO if !FSP_TYPE_IOT 15 select DRIVERS_USB_ACPI 16 select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 17 select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW 18 select FSP_COMPRESS_FSP_S_LZ4 19 select FSP_M_XIP 20 select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 21 select GENERIC_GPIO_LIB 22 select HAVE_FSP_GOP 23 select HAVE_HYPERTHREADING 24 select HAVE_INTEL_FSP_REPO 25 select INTEL_DESCRIPTOR_MODE_CAPABLE 26 select HAVE_SMI_HANDLER 27 select IDT_IN_EVERY_STAGE 28 select INTEL_CAR_NEM_ENHANCED if !INTEL_CAR_NEM 29 select CAR_HAS_SF_MASKS if INTEL_CAR_NEM_ENHANCED 30 select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED 31 select SF_MASK_2WAYS_PER_BIT if INTEL_CAR_NEM_ENHANCED 32 select INTEL_GMA_ACPI 33 select INTEL_GMA_ADD_VBT if RUN_FSP_GOP 34 select INTEL_GMA_VERSION_2 35 select MP_SERVICES_PPI_V1 36 select MRC_SETTINGS_PROTECT 37 select PARALLEL_MP_AP_WORK 38 select PLATFORM_USES_FSP2_2 39 select PMC_GLOBAL_RESET_ENABLE_LOCK 40 select SOC_INTEL_COMMON 41 select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE 42 select SOC_INTEL_COMMON_BLOCK 43 select SOC_INTEL_COMMON_BLOCK_ACPI 44 select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC 45 select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO 46 select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT 47 select SOC_INTEL_COMMON_BLOCK_ACPI_PEP 48 select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ 49 select SOC_INTEL_COMMON_BLOCK_CAR 50 select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG 51 select SOC_INTEL_COMMON_BLOCK_CNVI 52 select SOC_INTEL_COMMON_BLOCK_CPU 53 select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT 54 select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE 55 select SOC_INTEL_COMMON_BLOCK_DTT 56 select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT 57 select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY 58 select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 59 select SOC_INTEL_COMMON_BLOCK_HDA 60 select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC 61 select SOC_INTEL_COMMON_BLOCK_IRQ 62 select SOC_INTEL_COMMON_BLOCK_ME_SPEC_15 63 select SOC_INTEL_COMMON_BLOCK_MEMINIT 64 select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 65 select SOC_INTEL_COMMON_BLOCK_PMC_EPOC 66 select SOC_INTEL_COMMON_BLOCK_SA 67 select SOC_INTEL_COMMON_BLOCK_SMM 68 select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP 69 select SOC_INTEL_COMMON_BLOCK_TCSS 70 select SOC_INTEL_COMMON_BLOCK_USB4 71 select SOC_INTEL_COMMON_BLOCK_USB4_PCIE 72 select SOC_INTEL_COMMON_BLOCK_USB4_XHCI 73 select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG 74 select SOC_INTEL_COMMON_FSP_RESET 75 select SOC_INTEL_COMMON_PCH_CLIENT 76 select SOC_INTEL_COMMON_RESET 77 select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT 78 select SOC_INTEL_CSE_SEND_EOP_LATE 79 select SOC_INTEL_CSE_SET_EOP 80 select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION 81 select SSE2 82 select SUPPORT_CPU_UCODE_IN_CBFS 83 select TSC_MONOTONIC_TIMER 84 select UDELAY_TSC 85 select UDK_2017_BINDING 86 select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM 87 select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT 88 select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE 89 select SOC_INTEL_COMMON_BASECODE 90 select SOC_INTEL_COMMON_BASECODE_RAMTOP 91 select CR50_USE_LONG_INTERRUPT_PULSES if TPM_GOOGLE_CR50 92 select X86_CLFLUSH_CAR 93 help 94 Intel Tigerlake support 95 96config SOC_INTEL_TIGERLAKE_PCH_H 97 bool 98 99if SOC_INTEL_TIGERLAKE 100 101config MAX_CPUS 102 int 103 default 16 if SOC_INTEL_TIGERLAKE_PCH_H 104 default 8 105 106config DIMM_SPD_SIZE 107 default 512 108 109config DCACHE_RAM_BASE 110 default 0xfef00000 111 112config DCACHE_RAM_SIZE 113 default 0x80000 114 help 115 The size of the cache-as-ram region required during bootblock 116 and/or romstage. 117 118config DCACHE_BSP_STACK_SIZE 119 hex 120 default 0x40400 121 help 122 The amount of anticipated stack usage in CAR by bootblock and 123 other stages. In the case of FSP_USES_CB_STACK default value will be 124 sum of FSP-M stack requirement(256KiB) and CB romstage stack requirement 125 (~1KiB). 126 127config FSP_TEMP_RAM_SIZE 128 hex 129 default 0x20000 130 help 131 The amount of anticipated heap usage in CAR by FSP. 132 Refer to Platform FSP integration guide document to know 133 the exact FSP requirement for Heap setup. 134 135config CHIPSET_DEVICETREE 136 string 137 default "soc/intel/tigerlake/chipset_pch_h.cb" if SOC_INTEL_TIGERLAKE_PCH_H 138 default "soc/intel/tigerlake/chipset.cb" 139 140config EXT_BIOS_WIN_BASE 141 default 0xf8000000 142 143config EXT_BIOS_WIN_SIZE 144 default 0x2000000 145 146config IFD_CHIPSET 147 string 148 default "tgl" 149 150config IED_REGION_SIZE 151 hex 152 default 0x400000 153 154config INTEL_TME 155 default n 156 157config MAX_ROOT_PORTS 158 int 159 default 24 if SOC_INTEL_TIGERLAKE_PCH_H 160 default 12 161 162config MAX_PCIE_CLOCK_SRC 163 int 164 default 16 if SOC_INTEL_TIGERLAKE_PCH_H 165 default 7 166 167config SMM_TSEG_SIZE 168 hex 169 default 0x800000 170 171config SMM_RESERVED_SIZE 172 hex 173 default 0x200000 174 175config PCR_BASE_ADDRESS 176 hex 177 default 0xfd000000 178 help 179 This option allows you to select MMIO Base Address of sideband bus. 180 181config ECAM_MMCONF_BASE_ADDRESS 182 default 0xc0000000 183 184config CPU_BCLK_MHZ 185 int 186 default 100 187 188config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ 189 int 190 default 120 191 192config CPU_XTAL_HZ 193 default 38400000 194 195config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ 196 int 197 default 133 198 199config SOC_INTEL_COMMON_BLOCK_GSPI_MAX 200 int 201 default 4 202 203config SOC_INTEL_I2C_DEV_MAX 204 int 205 default 6 206 207config SOC_INTEL_UART_DEV_MAX 208 int 209 default 3 210 211config CONSOLE_UART_BASE_ADDRESS 212 hex 213 default 0xfe03e000 214 depends on INTEL_LPSS_UART_FOR_CONSOLE 215 216# Clock divider parameters for 115200 baud rate 217# Baudrate = (UART source clock * M) /(N *16) 218# TGL UART source clock: 100MHz 219config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL 220 hex 221 default 0x25a 222 223config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL 224 hex 225 default 0x7fff 226 227config VBOOT 228 select VBOOT_MUST_REQUEST_DISPLAY 229 select VBOOT_STARTS_IN_BOOTBLOCK 230 select VBOOT_VBNV_CMOS 231 select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH 232 233config CBFS_SIZE 234 default 0x200000 235 236config FSP_TYPE_IOT 237 bool 238 default n 239 help 240 This option allows to select FSP IOT type from 3rdparty/fsp repo 241 242config FSP_TYPE_CLIENT 243 bool 244 default !FSP_TYPE_IOT 245 help 246 This option allows to select FSP CLIENT type from 3rdparty/fsp repo 247 248config FSP_HEADER_PATH 249 default "3rdparty/fsp/TigerLakeFspBinPkg/TGL_IOT/Include/" if FSP_TYPE_IOT 250 default "3rdparty/fsp/TigerLakeFspBinPkg/Client/Include/" if FSP_TYPE_CLIENT 251 252config FSP_FD_PATH 253 default "3rdparty/fsp/TigerLakeFspBinPkg/TGL_IOT/Fsp.fd" if FSP_TYPE_IOT 254 default "3rdparty/fsp/TigerLakeFspBinPkg/Client/Fsp.fd" if FSP_TYPE_CLIENT 255 256config SOC_INTEL_TIGERLAKE_DEBUG_CONSENT 257 int "Debug Consent for TGL" 258 # USB DBC is more common for developers so make this default to 3 if 259 # SOC_INTEL_DEBUG_CONSENT=y 260 default 3 if SOC_INTEL_DEBUG_CONSENT 261 default 0 262 help 263 This is to control debug interface on SOC. 264 Setting non-zero value will allow to use DBC or DCI to debug SOC. 265 PlatformDebugConsent in FspmUpd.h has the details. 266 267 Desired platform debug type are 268 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), 269 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), 270 6:Enable (2-wire DCI OOB), 7:Manual 271 272config PRERAM_CBMEM_CONSOLE_SIZE 273 hex 274 default 0x2000 275 276config DATA_BUS_WIDTH 277 int 278 default 128 279 280config DIMMS_PER_CHANNEL 281 int 282 default 2 283 284config MRC_CHANNEL_WIDTH 285 int 286 default 16 287 288# Intel recommends reserving the following resources per USB4 root port, 289# from TGL BIOS Spec (doc #611569) Revision 0.7.6 Section 7.2.5.1.5 290# - 42 buses 291# - 194 MiB Non-prefetchable memory 292# - 448 MiB Prefetchable memory 293if SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES 294 295config PCIEXP_HOTPLUG_BUSES 296 default 42 297 298config PCIEXP_HOTPLUG_MEM 299 default 0xc200000 # 194 MiB 300 301config PCIEXP_HOTPLUG_PREFETCH_MEM 302 default 0x1c000000 # 448 MiB 303 304endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES 305 306config INTEL_GMA_BCLV_OFFSET 307 default 0xc8258 308 309config INTEL_GMA_BCLV_WIDTH 310 default 32 311 312config INTEL_GMA_BCLM_OFFSET 313 default 0xc8254 314 315config INTEL_GMA_BCLM_WIDTH 316 default 32 317 318endif 319