1## SPDX-License-Identifier: GPL-2.0-only 2 3config SOUTHBRIDGE_INTEL_LYNXPOINT 4 bool 5 select ACPI_COMMON_MADT_IOAPIC 6 select ACPI_COMMON_MADT_LAPIC 7 select ACPI_INTEL_HARDWARE_SLEEP_VALUES 8 select ACPI_SOC_NVS 9 select AZALIA_HDA_CODEC_SUPPORT 10 select SOUTHBRIDGE_INTEL_COMMON_SMBUS 11 select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS 12 select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 13 select SOUTHBRIDGE_INTEL_COMMON_FINALIZE 14 select SOUTHBRIDGE_INTEL_COMMON_PMCLIB 15 select SOUTHBRIDGE_INTEL_COMMON_PMBASE 16 select SOUTHBRIDGE_INTEL_COMMON_RTC 17 select SOUTHBRIDGE_INTEL_COMMON_RESET 18 select HAVE_SMI_HANDLER 19 select HAVE_USBDEBUG_OPTIONS 20 select USE_WATCHDOG_ON_BOOT 21 select PCIEXP_ASPM 22 select PCIEXP_COMMON_CLOCK 23 select INTEL_DESCRIPTOR_MODE_CAPABLE 24 select HAVE_EM100PRO_SPI_CONSOLE_SUPPORT 25 select RTC 26 select SOUTHBRIDGE_INTEL_COMMON_GPIO if !INTEL_LYNXPOINT_LP 27 select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ 28 select HAVE_INTEL_CHIPSET_LOCKDOWN 29 select HAVE_POWER_STATE_AFTER_FAILURE 30 select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE 31 select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG 32 select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG 33 select TCO_SPACE_NOT_YET_SPLIT 34 35if SOUTHBRIDGE_INTEL_LYNXPOINT 36 37config INTEL_LYNXPOINT_LP 38 bool 39 default n 40 help 41 Set this option to y for LynxPoint LP (Haswell ULT). 42 43config EHCI_BAR 44 hex 45 default 0xd8000000 if USE_BROADWELL_MRC 46 default 0xe8000000 47 48config SERIRQ_CONTINUOUS_MODE 49 bool 50 default n 51 help 52 If you set this option to y, the serial IRQ machine will be 53 operated in continuous mode. 54 55config HPET_MIN_TICKS 56 default 0x80 57 58config FINALIZE_USB_ROUTE_XHCI 59 bool "Route all ports to XHCI controller in finalize step" 60 default y 61 help 62 If you set this option to y, the USB ports will be routed 63 to the XHCI controller during the finalize SMM callback. 64 65config PCIEXP_AER 66 bool 67 default y 68 69config PCIEXP_CLK_PM 70 default y 71 72config PCIEXP_L1_SUB_STATE 73 default y 74 75config SERIALIO_UART_CONSOLE 76 bool "Use SerialIO UART for console" 77 depends on INTEL_LYNXPOINT_LP 78 select DRIVERS_UART_8250MEM_32 79 help 80 Selected by mainboards where SerialIO UARTs can be used to retrieve 81 coreboot logs. Boards also need to set UART_FOR_CONSOLE accordingly. 82 83config CONSOLE_UART_BASE_ADDRESS 84 default 0xd6000000 if SERIALIO_UART_CONSOLE 85 86config DISABLE_ME_PCI 87 bool "Disable Intel ME PCI interface (MEI1)" 88 default y 89 help 90 Disable and hide the ME PCI interface during finalize stage of boot. 91 This will prevent the OS (and userspace apps) from interacting with 92 the ME via the PCI interface after boot. 93 94endif 95