1// Generated by ARM internal tool 2// DO NOT EDIT 3 4// Copyright 2017 The Go Authors. All rights reserved. 5// Use of this source code is governed by a BSD-style 6// license that can be found in the LICENSE file. 7 8package arm64asm 9 10const ( 11 _ Op = iota 12 ABS 13 ADC 14 ADCS 15 ADD 16 ADDHN 17 ADDHN2 18 ADDP 19 ADDS 20 ADDV 21 ADR 22 ADRP 23 AESD 24 AESE 25 AESIMC 26 AESMC 27 AND 28 ANDS 29 ASR 30 ASRV 31 AT 32 B 33 BFI 34 BFM 35 BFXIL 36 BIC 37 BICS 38 BIF 39 BIT 40 BL 41 BLR 42 BR 43 BRK 44 BSL 45 CBNZ 46 CBZ 47 CCMN 48 CCMP 49 CINC 50 CINV 51 CLREX 52 CLS 53 CLZ 54 CMEQ 55 CMGE 56 CMGT 57 CMHI 58 CMHS 59 CMLE 60 CMLT 61 CMN 62 CMP 63 CMTST 64 CNEG 65 CNT 66 CRC32B 67 CRC32CB 68 CRC32CH 69 CRC32CW 70 CRC32CX 71 CRC32H 72 CRC32W 73 CRC32X 74 CSEL 75 CSET 76 CSETM 77 CSINC 78 CSINV 79 CSNEG 80 DC 81 DCPS1 82 DCPS2 83 DCPS3 84 DMB 85 DRPS 86 DSB 87 DUP 88 EON 89 EOR 90 ERET 91 EXT 92 EXTR 93 FABD 94 FABS 95 FACGE 96 FACGT 97 FADD 98 FADDP 99 FCCMP 100 FCCMPE 101 FCMEQ 102 FCMGE 103 FCMGT 104 FCMLE 105 FCMLT 106 FCMP 107 FCMPE 108 FCSEL 109 FCVT 110 FCVTAS 111 FCVTAU 112 FCVTL 113 FCVTL2 114 FCVTMS 115 FCVTMU 116 FCVTN 117 FCVTN2 118 FCVTNS 119 FCVTNU 120 FCVTPS 121 FCVTPU 122 FCVTXN 123 FCVTXN2 124 FCVTZS 125 FCVTZU 126 FDIV 127 FMADD 128 FMAX 129 FMAXNM 130 FMAXNMP 131 FMAXNMV 132 FMAXP 133 FMAXV 134 FMIN 135 FMINNM 136 FMINNMP 137 FMINNMV 138 FMINP 139 FMINV 140 FMLA 141 FMLS 142 FMOV 143 FMSUB 144 FMUL 145 FMULX 146 FNEG 147 FNMADD 148 FNMSUB 149 FNMUL 150 FRECPE 151 FRECPS 152 FRECPX 153 FRINTA 154 FRINTI 155 FRINTM 156 FRINTN 157 FRINTP 158 FRINTX 159 FRINTZ 160 FRSQRTE 161 FRSQRTS 162 FSQRT 163 FSUB 164 HINT 165 HLT 166 HVC 167 IC 168 INS 169 ISB 170 LD1 171 LD1R 172 LD2 173 LD2R 174 LD3 175 LD3R 176 LD4 177 LD4R 178 LDAR 179 LDARB 180 LDARH 181 LDAXP 182 LDAXR 183 LDAXRB 184 LDAXRH 185 LDNP 186 LDP 187 LDPSW 188 LDR 189 LDRB 190 LDRH 191 LDRSB 192 LDRSH 193 LDRSW 194 LDTR 195 LDTRB 196 LDTRH 197 LDTRSB 198 LDTRSH 199 LDTRSW 200 LDUR 201 LDURB 202 LDURH 203 LDURSB 204 LDURSH 205 LDURSW 206 LDXP 207 LDXR 208 LDXRB 209 LDXRH 210 LSL 211 LSLV 212 LSR 213 LSRV 214 MADD 215 MLA 216 MLS 217 MNEG 218 MOV 219 MOVI 220 MOVK 221 MOVN 222 MOVZ 223 MRS 224 MSR 225 MSUB 226 MUL 227 MVN 228 MVNI 229 NEG 230 NEGS 231 NGC 232 NGCS 233 NOP 234 NOT 235 ORN 236 ORR 237 PMUL 238 PMULL 239 PMULL2 240 PRFM 241 PRFUM 242 RADDHN 243 RADDHN2 244 RBIT 245 RET 246 REV 247 REV16 248 REV32 249 REV64 250 ROR 251 RORV 252 RSHRN 253 RSHRN2 254 RSUBHN 255 RSUBHN2 256 SABA 257 SABAL 258 SABAL2 259 SABD 260 SABDL 261 SABDL2 262 SADALP 263 SADDL 264 SADDL2 265 SADDLP 266 SADDLV 267 SADDW 268 SADDW2 269 SBC 270 SBCS 271 SBFIZ 272 SBFM 273 SBFX 274 SCVTF 275 SDIV 276 SEV 277 SEVL 278 SHA1C 279 SHA1H 280 SHA1M 281 SHA1P 282 SHA1SU0 283 SHA1SU1 284 SHA256H 285 SHA256H2 286 SHA256SU0 287 SHA256SU1 288 SHADD 289 SHL 290 SHLL 291 SHLL2 292 SHRN 293 SHRN2 294 SHSUB 295 SLI 296 SMADDL 297 SMAX 298 SMAXP 299 SMAXV 300 SMC 301 SMIN 302 SMINP 303 SMINV 304 SMLAL 305 SMLAL2 306 SMLSL 307 SMLSL2 308 SMNEGL 309 SMOV 310 SMSUBL 311 SMULH 312 SMULL 313 SMULL2 314 SQABS 315 SQADD 316 SQDMLAL 317 SQDMLAL2 318 SQDMLSL 319 SQDMLSL2 320 SQDMULH 321 SQDMULL 322 SQDMULL2 323 SQNEG 324 SQRDMULH 325 SQRSHL 326 SQRSHRN 327 SQRSHRN2 328 SQRSHRUN 329 SQRSHRUN2 330 SQSHL 331 SQSHLU 332 SQSHRN 333 SQSHRN2 334 SQSHRUN 335 SQSHRUN2 336 SQSUB 337 SQXTN 338 SQXTN2 339 SQXTUN 340 SQXTUN2 341 SRHADD 342 SRI 343 SRSHL 344 SRSHR 345 SRSRA 346 SSHL 347 SSHLL 348 SSHLL2 349 SSHR 350 SSRA 351 SSUBL 352 SSUBL2 353 SSUBW 354 SSUBW2 355 ST1 356 ST2 357 ST3 358 ST4 359 STLR 360 STLRB 361 STLRH 362 STLXP 363 STLXR 364 STLXRB 365 STLXRH 366 STNP 367 STP 368 STR 369 STRB 370 STRH 371 STTR 372 STTRB 373 STTRH 374 STUR 375 STURB 376 STURH 377 STXP 378 STXR 379 STXRB 380 STXRH 381 SUB 382 SUBHN 383 SUBHN2 384 SUBS 385 SUQADD 386 SVC 387 SXTB 388 SXTH 389 SXTL 390 SXTL2 391 SXTW 392 SYS 393 SYSL 394 TBL 395 TBNZ 396 TBX 397 TBZ 398 TLBI 399 TRN1 400 TRN2 401 TST 402 UABA 403 UABAL 404 UABAL2 405 UABD 406 UABDL 407 UABDL2 408 UADALP 409 UADDL 410 UADDL2 411 UADDLP 412 UADDLV 413 UADDW 414 UADDW2 415 UBFIZ 416 UBFM 417 UBFX 418 UCVTF 419 UDIV 420 UHADD 421 UHSUB 422 UMADDL 423 UMAX 424 UMAXP 425 UMAXV 426 UMIN 427 UMINP 428 UMINV 429 UMLAL 430 UMLAL2 431 UMLSL 432 UMLSL2 433 UMNEGL 434 UMOV 435 UMSUBL 436 UMULH 437 UMULL 438 UMULL2 439 UQADD 440 UQRSHL 441 UQRSHRN 442 UQRSHRN2 443 UQSHL 444 UQSHRN 445 UQSHRN2 446 UQSUB 447 UQXTN 448 UQXTN2 449 URECPE 450 URHADD 451 URSHL 452 URSHR 453 URSQRTE 454 URSRA 455 USHL 456 USHLL 457 USHLL2 458 USHR 459 USQADD 460 USRA 461 USUBL 462 USUBL2 463 USUBW 464 USUBW2 465 UXTB 466 UXTH 467 UXTL 468 UXTL2 469 UZP1 470 UZP2 471 WFE 472 WFI 473 XTN 474 XTN2 475 YIELD 476 ZIP1 477 ZIP2 478) 479 480var opstr = [...]string{ 481 ABS: "ABS", 482 ADC: "ADC", 483 ADCS: "ADCS", 484 ADD: "ADD", 485 ADDHN: "ADDHN", 486 ADDHN2: "ADDHN2", 487 ADDP: "ADDP", 488 ADDS: "ADDS", 489 ADDV: "ADDV", 490 ADR: "ADR", 491 ADRP: "ADRP", 492 AESD: "AESD", 493 AESE: "AESE", 494 AESIMC: "AESIMC", 495 AESMC: "AESMC", 496 AND: "AND", 497 ANDS: "ANDS", 498 ASR: "ASR", 499 ASRV: "ASRV", 500 AT: "AT", 501 B: "B", 502 BFI: "BFI", 503 BFM: "BFM", 504 BFXIL: "BFXIL", 505 BIC: "BIC", 506 BICS: "BICS", 507 BIF: "BIF", 508 BIT: "BIT", 509 BL: "BL", 510 BLR: "BLR", 511 BR: "BR", 512 BRK: "BRK", 513 BSL: "BSL", 514 CBNZ: "CBNZ", 515 CBZ: "CBZ", 516 CCMN: "CCMN", 517 CCMP: "CCMP", 518 CINC: "CINC", 519 CINV: "CINV", 520 CLREX: "CLREX", 521 CLS: "CLS", 522 CLZ: "CLZ", 523 CMEQ: "CMEQ", 524 CMGE: "CMGE", 525 CMGT: "CMGT", 526 CMHI: "CMHI", 527 CMHS: "CMHS", 528 CMLE: "CMLE", 529 CMLT: "CMLT", 530 CMN: "CMN", 531 CMP: "CMP", 532 CMTST: "CMTST", 533 CNEG: "CNEG", 534 CNT: "CNT", 535 CRC32B: "CRC32B", 536 CRC32CB: "CRC32CB", 537 CRC32CH: "CRC32CH", 538 CRC32CW: "CRC32CW", 539 CRC32CX: "CRC32CX", 540 CRC32H: "CRC32H", 541 CRC32W: "CRC32W", 542 CRC32X: "CRC32X", 543 CSEL: "CSEL", 544 CSET: "CSET", 545 CSETM: "CSETM", 546 CSINC: "CSINC", 547 CSINV: "CSINV", 548 CSNEG: "CSNEG", 549 DC: "DC", 550 DCPS1: "DCPS1", 551 DCPS2: "DCPS2", 552 DCPS3: "DCPS3", 553 DMB: "DMB", 554 DRPS: "DRPS", 555 DSB: "DSB", 556 DUP: "DUP", 557 EON: "EON", 558 EOR: "EOR", 559 ERET: "ERET", 560 EXT: "EXT", 561 EXTR: "EXTR", 562 FABD: "FABD", 563 FABS: "FABS", 564 FACGE: "FACGE", 565 FACGT: "FACGT", 566 FADD: "FADD", 567 FADDP: "FADDP", 568 FCCMP: "FCCMP", 569 FCCMPE: "FCCMPE", 570 FCMEQ: "FCMEQ", 571 FCMGE: "FCMGE", 572 FCMGT: "FCMGT", 573 FCMLE: "FCMLE", 574 FCMLT: "FCMLT", 575 FCMP: "FCMP", 576 FCMPE: "FCMPE", 577 FCSEL: "FCSEL", 578 FCVT: "FCVT", 579 FCVTAS: "FCVTAS", 580 FCVTAU: "FCVTAU", 581 FCVTL: "FCVTL", 582 FCVTL2: "FCVTL2", 583 FCVTMS: "FCVTMS", 584 FCVTMU: "FCVTMU", 585 FCVTN: "FCVTN", 586 FCVTN2: "FCVTN2", 587 FCVTNS: "FCVTNS", 588 FCVTNU: "FCVTNU", 589 FCVTPS: "FCVTPS", 590 FCVTPU: "FCVTPU", 591 FCVTXN: "FCVTXN", 592 FCVTXN2: "FCVTXN2", 593 FCVTZS: "FCVTZS", 594 FCVTZU: "FCVTZU", 595 FDIV: "FDIV", 596 FMADD: "FMADD", 597 FMAX: "FMAX", 598 FMAXNM: "FMAXNM", 599 FMAXNMP: "FMAXNMP", 600 FMAXNMV: "FMAXNMV", 601 FMAXP: "FMAXP", 602 FMAXV: "FMAXV", 603 FMIN: "FMIN", 604 FMINNM: "FMINNM", 605 FMINNMP: "FMINNMP", 606 FMINNMV: "FMINNMV", 607 FMINP: "FMINP", 608 FMINV: "FMINV", 609 FMLA: "FMLA", 610 FMLS: "FMLS", 611 FMOV: "FMOV", 612 FMSUB: "FMSUB", 613 FMUL: "FMUL", 614 FMULX: "FMULX", 615 FNEG: "FNEG", 616 FNMADD: "FNMADD", 617 FNMSUB: "FNMSUB", 618 FNMUL: "FNMUL", 619 FRECPE: "FRECPE", 620 FRECPS: "FRECPS", 621 FRECPX: "FRECPX", 622 FRINTA: "FRINTA", 623 FRINTI: "FRINTI", 624 FRINTM: "FRINTM", 625 FRINTN: "FRINTN", 626 FRINTP: "FRINTP", 627 FRINTX: "FRINTX", 628 FRINTZ: "FRINTZ", 629 FRSQRTE: "FRSQRTE", 630 FRSQRTS: "FRSQRTS", 631 FSQRT: "FSQRT", 632 FSUB: "FSUB", 633 HINT: "HINT", 634 HLT: "HLT", 635 HVC: "HVC", 636 IC: "IC", 637 INS: "INS", 638 ISB: "ISB", 639 LD1: "LD1", 640 LD1R: "LD1R", 641 LD2: "LD2", 642 LD2R: "LD2R", 643 LD3: "LD3", 644 LD3R: "LD3R", 645 LD4: "LD4", 646 LD4R: "LD4R", 647 LDAR: "LDAR", 648 LDARB: "LDARB", 649 LDARH: "LDARH", 650 LDAXP: "LDAXP", 651 LDAXR: "LDAXR", 652 LDAXRB: "LDAXRB", 653 LDAXRH: "LDAXRH", 654 LDNP: "LDNP", 655 LDP: "LDP", 656 LDPSW: "LDPSW", 657 LDR: "LDR", 658 LDRB: "LDRB", 659 LDRH: "LDRH", 660 LDRSB: "LDRSB", 661 LDRSH: "LDRSH", 662 LDRSW: "LDRSW", 663 LDTR: "LDTR", 664 LDTRB: "LDTRB", 665 LDTRH: "LDTRH", 666 LDTRSB: "LDTRSB", 667 LDTRSH: "LDTRSH", 668 LDTRSW: "LDTRSW", 669 LDUR: "LDUR", 670 LDURB: "LDURB", 671 LDURH: "LDURH", 672 LDURSB: "LDURSB", 673 LDURSH: "LDURSH", 674 LDURSW: "LDURSW", 675 LDXP: "LDXP", 676 LDXR: "LDXR", 677 LDXRB: "LDXRB", 678 LDXRH: "LDXRH", 679 LSL: "LSL", 680 LSLV: "LSLV", 681 LSR: "LSR", 682 LSRV: "LSRV", 683 MADD: "MADD", 684 MLA: "MLA", 685 MLS: "MLS", 686 MNEG: "MNEG", 687 MOV: "MOV", 688 MOVI: "MOVI", 689 MOVK: "MOVK", 690 MOVN: "MOVN", 691 MOVZ: "MOVZ", 692 MRS: "MRS", 693 MSR: "MSR", 694 MSUB: "MSUB", 695 MUL: "MUL", 696 MVN: "MVN", 697 MVNI: "MVNI", 698 NEG: "NEG", 699 NEGS: "NEGS", 700 NGC: "NGC", 701 NGCS: "NGCS", 702 NOP: "NOP", 703 NOT: "NOT", 704 ORN: "ORN", 705 ORR: "ORR", 706 PMUL: "PMUL", 707 PMULL: "PMULL", 708 PMULL2: "PMULL2", 709 PRFM: "PRFM", 710 PRFUM: "PRFUM", 711 RADDHN: "RADDHN", 712 RADDHN2: "RADDHN2", 713 RBIT: "RBIT", 714 RET: "RET", 715 REV: "REV", 716 REV16: "REV16", 717 REV32: "REV32", 718 REV64: "REV64", 719 ROR: "ROR", 720 RORV: "RORV", 721 RSHRN: "RSHRN", 722 RSHRN2: "RSHRN2", 723 RSUBHN: "RSUBHN", 724 RSUBHN2: "RSUBHN2", 725 SABA: "SABA", 726 SABAL: "SABAL", 727 SABAL2: "SABAL2", 728 SABD: "SABD", 729 SABDL: "SABDL", 730 SABDL2: "SABDL2", 731 SADALP: "SADALP", 732 SADDL: "SADDL", 733 SADDL2: "SADDL2", 734 SADDLP: "SADDLP", 735 SADDLV: "SADDLV", 736 SADDW: "SADDW", 737 SADDW2: "SADDW2", 738 SBC: "SBC", 739 SBCS: "SBCS", 740 SBFIZ: "SBFIZ", 741 SBFM: "SBFM", 742 SBFX: "SBFX", 743 SCVTF: "SCVTF", 744 SDIV: "SDIV", 745 SEV: "SEV", 746 SEVL: "SEVL", 747 SHA1C: "SHA1C", 748 SHA1H: "SHA1H", 749 SHA1M: "SHA1M", 750 SHA1P: "SHA1P", 751 SHA1SU0: "SHA1SU0", 752 SHA1SU1: "SHA1SU1", 753 SHA256H: "SHA256H", 754 SHA256H2: "SHA256H2", 755 SHA256SU0: "SHA256SU0", 756 SHA256SU1: "SHA256SU1", 757 SHADD: "SHADD", 758 SHL: "SHL", 759 SHLL: "SHLL", 760 SHLL2: "SHLL2", 761 SHRN: "SHRN", 762 SHRN2: "SHRN2", 763 SHSUB: "SHSUB", 764 SLI: "SLI", 765 SMADDL: "SMADDL", 766 SMAX: "SMAX", 767 SMAXP: "SMAXP", 768 SMAXV: "SMAXV", 769 SMC: "SMC", 770 SMIN: "SMIN", 771 SMINP: "SMINP", 772 SMINV: "SMINV", 773 SMLAL: "SMLAL", 774 SMLAL2: "SMLAL2", 775 SMLSL: "SMLSL", 776 SMLSL2: "SMLSL2", 777 SMNEGL: "SMNEGL", 778 SMOV: "SMOV", 779 SMSUBL: "SMSUBL", 780 SMULH: "SMULH", 781 SMULL: "SMULL", 782 SMULL2: "SMULL2", 783 SQABS: "SQABS", 784 SQADD: "SQADD", 785 SQDMLAL: "SQDMLAL", 786 SQDMLAL2: "SQDMLAL2", 787 SQDMLSL: "SQDMLSL", 788 SQDMLSL2: "SQDMLSL2", 789 SQDMULH: "SQDMULH", 790 SQDMULL: "SQDMULL", 791 SQDMULL2: "SQDMULL2", 792 SQNEG: "SQNEG", 793 SQRDMULH: "SQRDMULH", 794 SQRSHL: "SQRSHL", 795 SQRSHRN: "SQRSHRN", 796 SQRSHRN2: "SQRSHRN2", 797 SQRSHRUN: "SQRSHRUN", 798 SQRSHRUN2: "SQRSHRUN2", 799 SQSHL: "SQSHL", 800 SQSHLU: "SQSHLU", 801 SQSHRN: "SQSHRN", 802 SQSHRN2: "SQSHRN2", 803 SQSHRUN: "SQSHRUN", 804 SQSHRUN2: "SQSHRUN2", 805 SQSUB: "SQSUB", 806 SQXTN: "SQXTN", 807 SQXTN2: "SQXTN2", 808 SQXTUN: "SQXTUN", 809 SQXTUN2: "SQXTUN2", 810 SRHADD: "SRHADD", 811 SRI: "SRI", 812 SRSHL: "SRSHL", 813 SRSHR: "SRSHR", 814 SRSRA: "SRSRA", 815 SSHL: "SSHL", 816 SSHLL: "SSHLL", 817 SSHLL2: "SSHLL2", 818 SSHR: "SSHR", 819 SSRA: "SSRA", 820 SSUBL: "SSUBL", 821 SSUBL2: "SSUBL2", 822 SSUBW: "SSUBW", 823 SSUBW2: "SSUBW2", 824 ST1: "ST1", 825 ST2: "ST2", 826 ST3: "ST3", 827 ST4: "ST4", 828 STLR: "STLR", 829 STLRB: "STLRB", 830 STLRH: "STLRH", 831 STLXP: "STLXP", 832 STLXR: "STLXR", 833 STLXRB: "STLXRB", 834 STLXRH: "STLXRH", 835 STNP: "STNP", 836 STP: "STP", 837 STR: "STR", 838 STRB: "STRB", 839 STRH: "STRH", 840 STTR: "STTR", 841 STTRB: "STTRB", 842 STTRH: "STTRH", 843 STUR: "STUR", 844 STURB: "STURB", 845 STURH: "STURH", 846 STXP: "STXP", 847 STXR: "STXR", 848 STXRB: "STXRB", 849 STXRH: "STXRH", 850 SUB: "SUB", 851 SUBHN: "SUBHN", 852 SUBHN2: "SUBHN2", 853 SUBS: "SUBS", 854 SUQADD: "SUQADD", 855 SVC: "SVC", 856 SXTB: "SXTB", 857 SXTH: "SXTH", 858 SXTL: "SXTL", 859 SXTL2: "SXTL2", 860 SXTW: "SXTW", 861 SYS: "SYS", 862 SYSL: "SYSL", 863 TBL: "TBL", 864 TBNZ: "TBNZ", 865 TBX: "TBX", 866 TBZ: "TBZ", 867 TLBI: "TLBI", 868 TRN1: "TRN1", 869 TRN2: "TRN2", 870 TST: "TST", 871 UABA: "UABA", 872 UABAL: "UABAL", 873 UABAL2: "UABAL2", 874 UABD: "UABD", 875 UABDL: "UABDL", 876 UABDL2: "UABDL2", 877 UADALP: "UADALP", 878 UADDL: "UADDL", 879 UADDL2: "UADDL2", 880 UADDLP: "UADDLP", 881 UADDLV: "UADDLV", 882 UADDW: "UADDW", 883 UADDW2: "UADDW2", 884 UBFIZ: "UBFIZ", 885 UBFM: "UBFM", 886 UBFX: "UBFX", 887 UCVTF: "UCVTF", 888 UDIV: "UDIV", 889 UHADD: "UHADD", 890 UHSUB: "UHSUB", 891 UMADDL: "UMADDL", 892 UMAX: "UMAX", 893 UMAXP: "UMAXP", 894 UMAXV: "UMAXV", 895 UMIN: "UMIN", 896 UMINP: "UMINP", 897 UMINV: "UMINV", 898 UMLAL: "UMLAL", 899 UMLAL2: "UMLAL2", 900 UMLSL: "UMLSL", 901 UMLSL2: "UMLSL2", 902 UMNEGL: "UMNEGL", 903 UMOV: "UMOV", 904 UMSUBL: "UMSUBL", 905 UMULH: "UMULH", 906 UMULL: "UMULL", 907 UMULL2: "UMULL2", 908 UQADD: "UQADD", 909 UQRSHL: "UQRSHL", 910 UQRSHRN: "UQRSHRN", 911 UQRSHRN2: "UQRSHRN2", 912 UQSHL: "UQSHL", 913 UQSHRN: "UQSHRN", 914 UQSHRN2: "UQSHRN2", 915 UQSUB: "UQSUB", 916 UQXTN: "UQXTN", 917 UQXTN2: "UQXTN2", 918 URECPE: "URECPE", 919 URHADD: "URHADD", 920 URSHL: "URSHL", 921 URSHR: "URSHR", 922 URSQRTE: "URSQRTE", 923 URSRA: "URSRA", 924 USHL: "USHL", 925 USHLL: "USHLL", 926 USHLL2: "USHLL2", 927 USHR: "USHR", 928 USQADD: "USQADD", 929 USRA: "USRA", 930 USUBL: "USUBL", 931 USUBL2: "USUBL2", 932 USUBW: "USUBW", 933 USUBW2: "USUBW2", 934 UXTB: "UXTB", 935 UXTH: "UXTH", 936 UXTL: "UXTL", 937 UXTL2: "UXTL2", 938 UZP1: "UZP1", 939 UZP2: "UZP2", 940 WFE: "WFE", 941 WFI: "WFI", 942 XTN: "XTN", 943 XTN2: "XTN2", 944 YIELD: "YIELD", 945 ZIP1: "ZIP1", 946 ZIP2: "ZIP2", 947} 948 949var instFormats = [...]instFormat{ 950 // ADC <Wd>, <Wn>, <Wm> 951 {0xffe0fc00, 0x1a000000, ADC, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil}, 952 // ADC <Xd>, <Xn>, <Xm> 953 {0xffe0fc00, 0x9a000000, ADC, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil}, 954 // ADCS <Wd>, <Wn>, <Wm> 955 {0xffe0fc00, 0x3a000000, ADCS, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil}, 956 // ADCS <Xd>, <Xn>, <Xm> 957 {0xffe0fc00, 0xba000000, ADCS, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil}, 958 // ADD <Wd|WSP>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}} 959 {0xffe00000, 0x0b200000, ADD, instArgs{arg_Wds, arg_Wns, arg_Wm_extend__UXTB_0__UXTH_1__LSL_UXTW_2__UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4}, nil}, 960 // ADD <Xd|SP>, <Xn|SP>, <R><m>{, <extend_1> {#<amount>}} 961 {0xffe00000, 0x8b200000, ADD, instArgs{arg_Xds, arg_Xns, arg_Rm_extend__UXTB_0__UXTH_1__UXTW_2__LSL_UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4}, nil}, 962 // MOV <Wd|WSP>, <Wn|WSP> 963 {0xfffffc00, 0x11000000, MOV, instArgs{arg_Wds, arg_Wns}, mov_add_32_addsub_imm_cond}, 964 // ADD <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>} 965 {0xff000000, 0x11000000, ADD, instArgs{arg_Wds, arg_Wns, arg_IAddSub}, nil}, 966 // MOV <Xd|SP>, <Xn|SP> 967 {0xfffffc00, 0x91000000, MOV, instArgs{arg_Xds, arg_Xns}, mov_add_64_addsub_imm_cond}, 968 // ADD <Xd|SP>, <Xn|SP>, #<imm>{, <shift>} 969 {0xff000000, 0x91000000, ADD, instArgs{arg_Xds, arg_Xns, arg_IAddSub}, nil}, 970 // ADD <Wd>, <Wn>, <Wm> {, <shift> #<amount> } 971 {0xff208000, 0x0b000000, ADD, instArgs{arg_Wd, arg_Wn, arg_Wm_shift__LSL_0__LSR_1__ASR_2__0_31}, nil}, 972 // ADD <Xd>, <Xn>, <Xm> {, <shift> #<amount> } 973 {0xff200000, 0x8b000000, ADD, instArgs{arg_Xd, arg_Xn, arg_Xm_shift__LSL_0__LSR_1__ASR_2__0_63}, nil}, 974 // CMN <Wn|WSP>, <Wm>{, <extend> {#<amount>}} 975 {0xffe0001f, 0x2b20001f, CMN, instArgs{arg_Wns, arg_Wm_extend__UXTB_0__UXTH_1__LSL_UXTW_2__UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4}, nil}, 976 // ADDS <Wd>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}} 977 {0xffe00000, 0x2b200000, ADDS, instArgs{arg_Wd, arg_Wns, arg_Wm_extend__UXTB_0__UXTH_1__LSL_UXTW_2__UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4}, nil}, 978 // CMN <Xn|SP>, <R><m>{, <extend_1> {#<amount>}} 979 {0xffe0001f, 0xab20001f, CMN, instArgs{arg_Xns, arg_Rm_extend__UXTB_0__UXTH_1__UXTW_2__LSL_UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4}, nil}, 980 // ADDS <Xd>, <Xn|SP>, <R><m>{, <extend_1> {#<amount>}} 981 {0xffe00000, 0xab200000, ADDS, instArgs{arg_Xd, arg_Xns, arg_Rm_extend__UXTB_0__UXTH_1__UXTW_2__LSL_UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4}, nil}, 982 // CMN <Wn|WSP>, #<imm>{, <shift>} 983 {0xff00001f, 0x3100001f, CMN, instArgs{arg_Wns, arg_IAddSub}, nil}, 984 // ADDS <Wd>, <Wn|WSP>, #<imm>{, <shift>} 985 {0xff000000, 0x31000000, ADDS, instArgs{arg_Wd, arg_Wns, arg_IAddSub}, nil}, 986 // CMN <Xn|SP>, #<imm>{, <shift>} 987 {0xff00001f, 0xb100001f, CMN, instArgs{arg_Xns, arg_IAddSub}, nil}, 988 // ADDS <Xd>, <Xn|SP>, #<imm>{, <shift>} 989 {0xff000000, 0xb1000000, ADDS, instArgs{arg_Xd, arg_Xns, arg_IAddSub}, nil}, 990 // CMN <Wn>, <Wm> {, <shift> #<amount> } 991 {0xff20801f, 0x2b00001f, CMN, instArgs{arg_Wn, arg_Wm_shift__LSL_0__LSR_1__ASR_2__0_31}, nil}, 992 // ADDS <Wd>, <Wn>, <Wm> {, <shift> #<amount> } 993 {0xff208000, 0x2b000000, ADDS, instArgs{arg_Wd, arg_Wn, arg_Wm_shift__LSL_0__LSR_1__ASR_2__0_31}, nil}, 994 // CMN <Xn>, <Xm> {, <shift> #<amount> } 995 {0xff20001f, 0xab00001f, CMN, instArgs{arg_Xn, arg_Xm_shift__LSL_0__LSR_1__ASR_2__0_63}, nil}, 996 // ADDS <Xd>, <Xn>, <Xm> {, <shift> #<amount> } 997 {0xff200000, 0xab000000, ADDS, instArgs{arg_Xd, arg_Xn, arg_Xm_shift__LSL_0__LSR_1__ASR_2__0_63}, nil}, 998 // ADR <Xd>, <label> 999 {0x9f000000, 0x10000000, ADR, instArgs{arg_Xd, arg_slabel_immhi_immlo_0}, nil}, 1000 // ADRP <Xd>, <label> 1001 {0x9f000000, 0x90000000, ADRP, instArgs{arg_Xd, arg_slabel_immhi_immlo_12}, nil}, 1002 // AND <Wd|WSP>, <Wn>, #<imm> 1003 {0xffc00000, 0x12000000, AND, instArgs{arg_Wds, arg_Wn, arg_immediate_bitmask_32_imms_immr}, nil}, 1004 // AND <Xd|SP>, <Xn>, #<imm> 1005 {0xff800000, 0x92000000, AND, instArgs{arg_Xds, arg_Xn, arg_immediate_bitmask_64_N_imms_immr}, nil}, 1006 // AND <Wd>, <Wn>, <Wm> {, <shift> #<amount> } 1007 {0xff208000, 0x0a000000, AND, instArgs{arg_Wd, arg_Wn, arg_Wm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_31}, nil}, 1008 // AND <Xd>, <Xn>, <Xm> {, <shift> #<amount> } 1009 {0xff200000, 0x8a000000, AND, instArgs{arg_Xd, arg_Xn, arg_Xm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_63}, nil}, 1010 // TST <Wn>, #<imm> 1011 {0xffc0001f, 0x7200001f, TST, instArgs{arg_Wn, arg_immediate_bitmask_32_imms_immr}, nil}, 1012 // ANDS <Wd>, <Wn>, #<imm> 1013 {0xffc00000, 0x72000000, ANDS, instArgs{arg_Wd, arg_Wn, arg_immediate_bitmask_32_imms_immr}, nil}, 1014 // TST <Xn>, #<imm> 1015 {0xff80001f, 0xf200001f, TST, instArgs{arg_Xn, arg_immediate_bitmask_64_N_imms_immr}, nil}, 1016 // ANDS <Xd>, <Xn>, #<imm> 1017 {0xff800000, 0xf2000000, ANDS, instArgs{arg_Xd, arg_Xn, arg_immediate_bitmask_64_N_imms_immr}, nil}, 1018 // TST <Wn>, <Wm> {, <shift> #<amount> } 1019 {0xff20801f, 0x6a00001f, TST, instArgs{arg_Wn, arg_Wm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_31}, nil}, 1020 // ANDS <Wd>, <Wn>, <Wm> {, <shift> #<amount> } 1021 {0xff208000, 0x6a000000, ANDS, instArgs{arg_Wd, arg_Wn, arg_Wm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_31}, nil}, 1022 // TST <Xn>, <Xm> {, <shift> #<amount> } 1023 {0xff20001f, 0xea00001f, TST, instArgs{arg_Xn, arg_Xm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_63}, nil}, 1024 // ANDS <Xd>, <Xn>, <Xm> {, <shift> #<amount> } 1025 {0xff200000, 0xea000000, ANDS, instArgs{arg_Xd, arg_Xn, arg_Xm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_63}, nil}, 1026 // ASR <Wd>, <Wn>, #<shift> 1027 {0xffc0fc00, 0x13007c00, ASR, instArgs{arg_Wd, arg_Wn, arg_immediate_ASR_SBFM_32M_bitfield_0_31_immr}, nil}, 1028 // SBFIZ <Wd>, <Wn>, #<lsb>, #<width> 1029 {0xffc00000, 0x13000000, SBFIZ, instArgs{arg_Wd, arg_Wn, arg_immediate_SBFIZ_SBFM_32M_bitfield_lsb_32_immr, arg_immediate_SBFIZ_SBFM_32M_bitfield_width_32_imms}, sbfiz_sbfm_32m_bitfield_cond}, 1030 // SBFX <Wd>, <Wn>, #<lsb>, #<width> 1031 {0xffc00000, 0x13000000, SBFX, instArgs{arg_Wd, arg_Wn, arg_immediate_SBFX_SBFM_32M_bitfield_lsb_32_immr, arg_immediate_SBFX_SBFM_32M_bitfield_width_32_imms}, sbfx_sbfm_32m_bitfield_cond}, 1032 // SXTB <Wd>, <Wn> 1033 {0xfffffc00, 0x13001c00, SXTB, instArgs{arg_Wd, arg_Wn}, nil}, 1034 // SXTH <Wd>, <Wn> 1035 {0xfffffc00, 0x13003c00, SXTH, instArgs{arg_Wd, arg_Wn}, nil}, 1036 // SBFM <Wd>, <Wn>, #<immr>, #<imms> 1037 {0xffc00000, 0x13000000, SBFM, instArgs{arg_Wd, arg_Wn, arg_immediate_0_31_immr, arg_immediate_0_31_imms}, nil}, 1038 // ASR <Xd>, <Xn>, #<shift> 1039 {0xffc0fc00, 0x9340fc00, ASR, instArgs{arg_Xd, arg_Xn, arg_immediate_ASR_SBFM_64M_bitfield_0_63_immr}, nil}, 1040 // SBFIZ <Xd>, <Xn>, #<lsb>, #<width> 1041 {0xffc00000, 0x93400000, SBFIZ, instArgs{arg_Xd, arg_Xn, arg_immediate_SBFIZ_SBFM_64M_bitfield_lsb_64_immr, arg_immediate_SBFIZ_SBFM_64M_bitfield_width_64_imms}, sbfiz_sbfm_64m_bitfield_cond}, 1042 // SBFX <Xd>, <Xn>, #<lsb>, #<width> 1043 {0xffc00000, 0x93400000, SBFX, instArgs{arg_Xd, arg_Xn, arg_immediate_SBFX_SBFM_64M_bitfield_lsb_64_immr, arg_immediate_SBFX_SBFM_64M_bitfield_width_64_imms}, sbfx_sbfm_64m_bitfield_cond}, 1044 // SXTB <Xd>, <Wn> 1045 {0xfffffc00, 0x93401c00, SXTB, instArgs{arg_Xd, arg_Wn}, nil}, 1046 // SXTH <Xd>, <Wn> 1047 {0xfffffc00, 0x93403c00, SXTH, instArgs{arg_Xd, arg_Wn}, nil}, 1048 // SXTW <Xd>, <Wn> 1049 {0xfffffc00, 0x93407c00, SXTW, instArgs{arg_Xd, arg_Wn}, nil}, 1050 // SBFM <Xd>, <Xn>, #<immr>, #<imms> 1051 {0xffc00000, 0x93400000, SBFM, instArgs{arg_Xd, arg_Xn, arg_immediate_0_63_immr, arg_immediate_0_63_imms}, nil}, 1052 // ASR <Wd>, <Wn>, <Wm> 1053 {0xffe0fc00, 0x1ac02800, ASR, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil}, 1054 // ASRV <Wd>, <Wn>, <Wm> 1055 {0xffe0fc00, 0x1ac02800, ASRV, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil}, 1056 // ASR <Xd>, <Xn>, <Xm> 1057 {0xffe0fc00, 0x9ac02800, ASR, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil}, 1058 // ASRV <Xd>, <Xn>, <Xm> 1059 {0xffe0fc00, 0x9ac02800, ASRV, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil}, 1060 // AT <at>, <Xt> 1061 {0xfff8ff00, 0xd5087800, AT, instArgs{arg_sysop_AT_SYS_CR_system}, at_sys_cr_system_cond}, 1062 // DC <dc>, <Xt> 1063 {0xfff8f000, 0xd5087000, DC, instArgs{arg_sysop_DC_SYS_CR_system}, dc_sys_cr_system_cond}, 1064 // IC <ic>, {<Xt>} 1065 {0xfff8f000, 0xd5087000, IC, instArgs{arg_sysop_IC_SYS_CR_system}, ic_sys_cr_system_cond}, 1066 // TLBI <tlbi>, {<Xt>} 1067 {0xfff8f000, 0xd5088000, TLBI, instArgs{arg_sysop_TLBI_SYS_CR_system}, tlbi_sys_cr_system_cond}, 1068 // SYS #<op1>, <Cn>, <Cm>, <op>, {<Xt>} 1069 {0xfff80000, 0xd5080000, SYS, instArgs{arg_immediate_0_7_op1, arg_Cn, arg_Cm, arg_sysop_SYS_CR_system}, nil}, 1070 // B <label> 1071 {0xfc000000, 0x14000000, B, instArgs{arg_slabel_imm26_2}, nil}, 1072 // B<c> <label> 1073 {0xff000010, 0x54000000, B, instArgs{arg_conditional, arg_slabel_imm19_2}, nil}, 1074 // BFI <Wd>, <Wn>, #<lsb>, #<width> 1075 {0xffc00000, 0x33000000, BFI, instArgs{arg_Wd, arg_Wn, arg_immediate_BFI_BFM_32M_bitfield_lsb_32_immr, arg_immediate_BFI_BFM_32M_bitfield_width_32_imms}, bfi_bfm_32m_bitfield_cond}, 1076 // BFXIL <Wd>, <Wn>, #<lsb>, #<width> 1077 {0xffc00000, 0x33000000, BFXIL, instArgs{arg_Wd, arg_Wn, arg_immediate_BFXIL_BFM_32M_bitfield_lsb_32_immr, arg_immediate_BFXIL_BFM_32M_bitfield_width_32_imms}, bfxil_bfm_32m_bitfield_cond}, 1078 // BFM <Wd>, <Wn>, #<immr>, #<imms> 1079 {0xffc00000, 0x33000000, BFM, instArgs{arg_Wd, arg_Wn, arg_immediate_0_31_immr, arg_immediate_0_31_imms}, nil}, 1080 // BFI <Xd>, <Xn>, #<lsb>, #<width> 1081 {0xffc00000, 0xb3400000, BFI, instArgs{arg_Xd, arg_Xn, arg_immediate_BFI_BFM_64M_bitfield_lsb_64_immr, arg_immediate_BFI_BFM_64M_bitfield_width_64_imms}, bfi_bfm_64m_bitfield_cond}, 1082 // BFXIL <Xd>, <Xn>, #<lsb>, #<width> 1083 {0xffc00000, 0xb3400000, BFXIL, instArgs{arg_Xd, arg_Xn, arg_immediate_BFXIL_BFM_64M_bitfield_lsb_64_immr, arg_immediate_BFXIL_BFM_64M_bitfield_width_64_imms}, bfxil_bfm_64m_bitfield_cond}, 1084 // BFM <Xd>, <Xn>, #<immr>, #<imms> 1085 {0xffc00000, 0xb3400000, BFM, instArgs{arg_Xd, arg_Xn, arg_immediate_0_63_immr, arg_immediate_0_63_imms}, nil}, 1086 // BIC <Wd>, <Wn>, <Wm> {, <shift> #<amount> } 1087 {0xff208000, 0x0a200000, BIC, instArgs{arg_Wd, arg_Wn, arg_Wm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_31}, nil}, 1088 // BIC <Xd>, <Xn>, <Xm> {, <shift> #<amount> } 1089 {0xff200000, 0x8a200000, BIC, instArgs{arg_Xd, arg_Xn, arg_Xm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_63}, nil}, 1090 // BICS <Wd>, <Wn>, <Wm> {, <shift> #<amount> } 1091 {0xff208000, 0x6a200000, BICS, instArgs{arg_Wd, arg_Wn, arg_Wm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_31}, nil}, 1092 // BICS <Xd>, <Xn>, <Xm> {, <shift> #<amount> } 1093 {0xff200000, 0xea200000, BICS, instArgs{arg_Xd, arg_Xn, arg_Xm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_63}, nil}, 1094 // BL <label> 1095 {0xfc000000, 0x94000000, BL, instArgs{arg_slabel_imm26_2}, nil}, 1096 // BLR <Xn> 1097 {0xfffffc1f, 0xd63f0000, BLR, instArgs{arg_Xn}, nil}, 1098 // BR <Xn> 1099 {0xfffffc1f, 0xd61f0000, BR, instArgs{arg_Xn}, nil}, 1100 // BRK #<imm> 1101 {0xffe0001f, 0xd4200000, BRK, instArgs{arg_immediate_0_65535_imm16}, nil}, 1102 // CBNZ <Wt>, <label> 1103 {0xff000000, 0x35000000, CBNZ, instArgs{arg_Wt, arg_slabel_imm19_2}, nil}, 1104 // CBNZ <Xt>, <label> 1105 {0xff000000, 0xb5000000, CBNZ, instArgs{arg_Xt, arg_slabel_imm19_2}, nil}, 1106 // CBZ <Wt>, <label> 1107 {0xff000000, 0x34000000, CBZ, instArgs{arg_Wt, arg_slabel_imm19_2}, nil}, 1108 // CBZ <Xt>, <label> 1109 {0xff000000, 0xb4000000, CBZ, instArgs{arg_Xt, arg_slabel_imm19_2}, nil}, 1110 // CCMN <Wn>, #<imm>, #<nzcv>, <cond> 1111 {0xffe00c10, 0x3a400800, CCMN, instArgs{arg_Wn, arg_immediate_0_31_imm5, arg_immediate_0_15_nzcv, arg_cond_AllowALNV_Normal}, nil}, 1112 // CCMN <Xn>, #<imm>, #<nzcv>, <cond> 1113 {0xffe00c10, 0xba400800, CCMN, instArgs{arg_Xn, arg_immediate_0_31_imm5, arg_immediate_0_15_nzcv, arg_cond_AllowALNV_Normal}, nil}, 1114 // CCMN <Wn>, <Wm>, #<nzcv>, <cond> 1115 {0xffe00c10, 0x3a400000, CCMN, instArgs{arg_Wn, arg_Wm, arg_immediate_0_15_nzcv, arg_cond_AllowALNV_Normal}, nil}, 1116 // CCMN <Xn>, <Xm>, #<nzcv>, <cond> 1117 {0xffe00c10, 0xba400000, CCMN, instArgs{arg_Xn, arg_Xm, arg_immediate_0_15_nzcv, arg_cond_AllowALNV_Normal}, nil}, 1118 // CCMP <Wn>, #<imm>, #<nzcv>, <cond> 1119 {0xffe00c10, 0x7a400800, CCMP, instArgs{arg_Wn, arg_immediate_0_31_imm5, arg_immediate_0_15_nzcv, arg_cond_AllowALNV_Normal}, nil}, 1120 // CCMP <Xn>, #<imm>, #<nzcv>, <cond> 1121 {0xffe00c10, 0xfa400800, CCMP, instArgs{arg_Xn, arg_immediate_0_31_imm5, arg_immediate_0_15_nzcv, arg_cond_AllowALNV_Normal}, nil}, 1122 // CCMP <Wn>, <Wm>, #<nzcv>, <cond> 1123 {0xffe00c10, 0x7a400000, CCMP, instArgs{arg_Wn, arg_Wm, arg_immediate_0_15_nzcv, arg_cond_AllowALNV_Normal}, nil}, 1124 // CCMP <Xn>, <Xm>, #<nzcv>, <cond> 1125 {0xffe00c10, 0xfa400000, CCMP, instArgs{arg_Xn, arg_Xm, arg_immediate_0_15_nzcv, arg_cond_AllowALNV_Normal}, nil}, 1126 // CINC <Wd>, <Wn>, <cond> 1127 {0xffe00c00, 0x1a800400, CINC, instArgs{arg_Wd, arg_Wn, arg_cond_NotAllowALNV_Invert}, cinc_csinc_32_condsel_cond}, 1128 // CSET <Wd>, <cond> 1129 {0xffff0fe0, 0x1a9f07e0, CSET, instArgs{arg_Wd, arg_cond_NotAllowALNV_Invert}, csinc_general_cond}, 1130 // CSINC <Wd>, <Wn>, <Wm>, <cond> 1131 {0xffe00c00, 0x1a800400, CSINC, instArgs{arg_Wd, arg_Wn, arg_Wm, arg_cond_AllowALNV_Normal}, nil}, 1132 // CINC <Xd>, <Xn>, <cond> 1133 {0xffe00c00, 0x9a800400, CINC, instArgs{arg_Xd, arg_Xn, arg_cond_NotAllowALNV_Invert}, cinc_csinc_64_condsel_cond}, 1134 // CSET <Xd>, <cond> 1135 {0xffff0fe0, 0x9a9f07e0, CSET, instArgs{arg_Xd, arg_cond_NotAllowALNV_Invert}, csinc_general_cond}, 1136 // CSINC <Xd>, <Xn>, <Xm>, <cond> 1137 {0xffe00c00, 0x9a800400, CSINC, instArgs{arg_Xd, arg_Xn, arg_Xm, arg_cond_AllowALNV_Normal}, nil}, 1138 // CINV <Wd>, <Wn>, <cond> 1139 {0xffe00c00, 0x5a800000, CINV, instArgs{arg_Wd, arg_Wn, arg_cond_NotAllowALNV_Invert}, cinv_csinv_32_condsel_cond}, 1140 // CSETM <Wd>, <cond> 1141 {0xffff0fe0, 0x5a9f03e0, CSETM, instArgs{arg_Wd, arg_cond_NotAllowALNV_Invert}, csinv_general_cond}, 1142 // CSINV <Wd>, <Wn>, <Wm>, <cond> 1143 {0xffe00c00, 0x5a800000, CSINV, instArgs{arg_Wd, arg_Wn, arg_Wm, arg_cond_AllowALNV_Normal}, nil}, 1144 // CINV <Xd>, <Xn>, <cond> 1145 {0xffe00c00, 0xda800000, CINV, instArgs{arg_Xd, arg_Xn, arg_cond_NotAllowALNV_Invert}, cinv_csinv_64_condsel_cond}, 1146 // CSETM <Xd>, <cond> 1147 {0xffff0fe0, 0xda9f03e0, CSETM, instArgs{arg_Xd, arg_cond_NotAllowALNV_Invert}, csinv_general_cond}, 1148 // CSINV <Xd>, <Xn>, <Xm>, <cond> 1149 {0xffe00c00, 0xda800000, CSINV, instArgs{arg_Xd, arg_Xn, arg_Xm, arg_cond_AllowALNV_Normal}, nil}, 1150 // CLREX {#<imm>} 1151 {0xfffff0ff, 0xd503305f, CLREX, instArgs{arg_immediate_optional_0_15_CRm}, nil}, 1152 // CLS <Wd>, <Wn> 1153 {0xfffffc00, 0x5ac01400, CLS, instArgs{arg_Wd, arg_Wn}, nil}, 1154 // CLS <Xd>, <Xn> 1155 {0xfffffc00, 0xdac01400, CLS, instArgs{arg_Xd, arg_Xn}, nil}, 1156 // CLZ <Wd>, <Wn> 1157 {0xfffffc00, 0x5ac01000, CLZ, instArgs{arg_Wd, arg_Wn}, nil}, 1158 // CLZ <Xd>, <Xn> 1159 {0xfffffc00, 0xdac01000, CLZ, instArgs{arg_Xd, arg_Xn}, nil}, 1160 // CMP <Wn|WSP>, <Wm>{, <extend> {#<amount>}} 1161 {0xffe0001f, 0x6b20001f, CMP, instArgs{arg_Wns, arg_Wm_extend__UXTB_0__UXTH_1__LSL_UXTW_2__UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4}, nil}, 1162 // SUBS <Wd>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}} 1163 {0xffe00000, 0x6b200000, SUBS, instArgs{arg_Wd, arg_Wns, arg_Wm_extend__UXTB_0__UXTH_1__LSL_UXTW_2__UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4}, nil}, 1164 // CMP <Xn|SP>, <R><m>{, <extend_1> {#<amount>}} 1165 {0xffe0001f, 0xeb20001f, CMP, instArgs{arg_Xns, arg_Rm_extend__UXTB_0__UXTH_1__UXTW_2__LSL_UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4}, nil}, 1166 // SUBS <Xd>, <Xn|SP>, <R><m>{, <extend_1> {#<amount>}} 1167 {0xffe00000, 0xeb200000, SUBS, instArgs{arg_Xd, arg_Xns, arg_Rm_extend__UXTB_0__UXTH_1__UXTW_2__LSL_UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4}, nil}, 1168 // CMP <Wn|WSP>, #<imm>{, <shift>} 1169 {0xff00001f, 0x7100001f, CMP, instArgs{arg_Wns, arg_IAddSub}, nil}, 1170 // SUBS <Wd>, <Wn|WSP>, #<imm>{, <shift>} 1171 {0xff000000, 0x71000000, SUBS, instArgs{arg_Wd, arg_Wns, arg_IAddSub}, nil}, 1172 // CMP <Xn|SP>, #<imm>{, <shift>} 1173 {0xff00001f, 0xf100001f, CMP, instArgs{arg_Xns, arg_IAddSub}, nil}, 1174 // SUBS <Xd>, <Xn|SP>, #<imm>{, <shift>} 1175 {0xff000000, 0xf1000000, SUBS, instArgs{arg_Xd, arg_Xns, arg_IAddSub}, nil}, 1176 // CMP <Wn>, <Wm> {, <shift> #<amount> } 1177 {0xff20801f, 0x6b00001f, CMP, instArgs{arg_Wn, arg_Wm_shift__LSL_0__LSR_1__ASR_2__0_31}, nil}, 1178 // NEGS <Wd>, <Wm> {, <shift> #<amount> } 1179 {0xff2003e0, 0x6b0003e0, NEGS, instArgs{arg_Wd, arg_Wm_shift__LSL_0__LSR_1__ASR_2__0_31}, nil}, 1180 // SUBS <Wd>, <Wn>, <Wm> {, <shift> #<amount> } 1181 {0xff208000, 0x6b000000, SUBS, instArgs{arg_Wd, arg_Wn, arg_Wm_shift__LSL_0__LSR_1__ASR_2__0_31}, nil}, 1182 // CMP <Xn>, <Xm> {, <shift> #<amount> } 1183 {0xff20001f, 0xeb00001f, CMP, instArgs{arg_Xn, arg_Xm_shift__LSL_0__LSR_1__ASR_2__0_63}, nil}, 1184 // NEGS <Xd>, <Xm> {, <shift> #<amount> } 1185 {0xff2003e0, 0xeb0003e0, NEGS, instArgs{arg_Xd, arg_Xm_shift__LSL_0__LSR_1__ASR_2__0_63}, nil}, 1186 // SUBS <Xd>, <Xn>, <Xm> {, <shift> #<amount> } 1187 {0xff200000, 0xeb000000, SUBS, instArgs{arg_Xd, arg_Xn, arg_Xm_shift__LSL_0__LSR_1__ASR_2__0_63}, nil}, 1188 // CNEG <Wd>, <Wn>, <cond> 1189 {0xffe00c00, 0x5a800400, CNEG, instArgs{arg_Wd, arg_Wn, arg_cond_NotAllowALNV_Invert}, cneg_csneg_32_condsel_cond}, 1190 // CSNEG <Wd>, <Wn>, <Wm>, <cond> 1191 {0xffe00c00, 0x5a800400, CSNEG, instArgs{arg_Wd, arg_Wn, arg_Wm, arg_cond_AllowALNV_Normal}, nil}, 1192 // CNEG <Xd>, <Xn>, <cond> 1193 {0xffe00c00, 0xda800400, CNEG, instArgs{arg_Xd, arg_Xn, arg_cond_NotAllowALNV_Invert}, cneg_csneg_64_condsel_cond}, 1194 // CSNEG <Xd>, <Xn>, <Xm>, <cond> 1195 {0xffe00c00, 0xda800400, CSNEG, instArgs{arg_Xd, arg_Xn, arg_Xm, arg_cond_AllowALNV_Normal}, nil}, 1196 // CRC32B <Wd>, <Wn>, <Wm> 1197 {0xffe0fc00, 0x1ac04000, CRC32B, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil}, 1198 // CRC32H <Wd>, <Wn>, <Wm> 1199 {0xffe0fc00, 0x1ac04400, CRC32H, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil}, 1200 // CRC32W <Wd>, <Wn>, <Wm> 1201 {0xffe0fc00, 0x1ac04800, CRC32W, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil}, 1202 // CRC32X <Wd>, <Wn>, <Xm> 1203 {0xffe0fc00, 0x9ac04c00, CRC32X, instArgs{arg_Wd, arg_Wn, arg_Xm}, nil}, 1204 // CRC32CB <Wd>, <Wn>, <Wm> 1205 {0xffe0fc00, 0x1ac05000, CRC32CB, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil}, 1206 // CRC32CH <Wd>, <Wn>, <Wm> 1207 {0xffe0fc00, 0x1ac05400, CRC32CH, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil}, 1208 // CRC32CW <Wd>, <Wn>, <Wm> 1209 {0xffe0fc00, 0x1ac05800, CRC32CW, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil}, 1210 // CRC32CX <Wd>, <Wn>, <Xm> 1211 {0xffe0fc00, 0x9ac05c00, CRC32CX, instArgs{arg_Wd, arg_Wn, arg_Xm}, nil}, 1212 // CSEL <Wd>, <Wn>, <Wm>, <cond> 1213 {0xffe00c00, 0x1a800000, CSEL, instArgs{arg_Wd, arg_Wn, arg_Wm, arg_cond_AllowALNV_Normal}, nil}, 1214 // CSEL <Xd>, <Xn>, <Xm>, <cond> 1215 {0xffe00c00, 0x9a800000, CSEL, instArgs{arg_Xd, arg_Xn, arg_Xm, arg_cond_AllowALNV_Normal}, nil}, 1216 // DCPS1 {#<imm>} 1217 {0xffe0001f, 0xd4a00001, DCPS1, instArgs{arg_immediate_optional_0_65535_imm16}, nil}, 1218 // DCPS2 {#<imm>} 1219 {0xffe0001f, 0xd4a00002, DCPS2, instArgs{arg_immediate_optional_0_65535_imm16}, nil}, 1220 // DCPS3 {#<imm>} 1221 {0xffe0001f, 0xd4a00003, DCPS3, instArgs{arg_immediate_optional_0_65535_imm16}, nil}, 1222 // DMB <option>|<imm> 1223 {0xfffff0ff, 0xd50330bf, DMB, instArgs{arg_option_DMB_BO_system_CRm}, nil}, 1224 // DRPS 1225 {0xffffffff, 0xd6bf03e0, DRPS, instArgs{}, nil}, 1226 // DSB <option>|<imm> 1227 {0xfffff0ff, 0xd503309f, DSB, instArgs{arg_option_DSB_BO_system_CRm}, nil}, 1228 // EON <Wd>, <Wn>, <Wm> {, <shift> #<amount> } 1229 {0xff208000, 0x4a200000, EON, instArgs{arg_Wd, arg_Wn, arg_Wm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_31}, nil}, 1230 // EON <Xd>, <Xn>, <Xm> {, <shift> #<amount> } 1231 {0xff200000, 0xca200000, EON, instArgs{arg_Xd, arg_Xn, arg_Xm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_63}, nil}, 1232 // EOR <Wd|WSP>, <Wn>, #<imm> 1233 {0xffc00000, 0x52000000, EOR, instArgs{arg_Wds, arg_Wn, arg_immediate_bitmask_32_imms_immr}, nil}, 1234 // EOR <Xd|SP>, <Xn>, #<imm> 1235 {0xff800000, 0xd2000000, EOR, instArgs{arg_Xds, arg_Xn, arg_immediate_bitmask_64_N_imms_immr}, nil}, 1236 // EOR <Wd>, <Wn>, <Wm> {, <shift> #<amount> } 1237 {0xff208000, 0x4a000000, EOR, instArgs{arg_Wd, arg_Wn, arg_Wm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_31}, nil}, 1238 // EOR <Xd>, <Xn>, <Xm> {, <shift> #<amount> } 1239 {0xff200000, 0xca000000, EOR, instArgs{arg_Xd, arg_Xn, arg_Xm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_63}, nil}, 1240 // ERET 1241 {0xffffffff, 0xd69f03e0, ERET, instArgs{}, nil}, 1242 // ROR <Wd>, <Ws>, #<shift> 1243 {0xffe08000, 0x13800000, ROR, instArgs{arg_Wd, arg_Ws, arg_immediate_0_31_imms}, ror_extr_32_extract_cond}, 1244 // EXTR <Wd>, <Wn>, <Wm>, #<lsb> 1245 {0xffe08000, 0x13800000, EXTR, instArgs{arg_Wd, arg_Wn, arg_Wm, arg_immediate_0_31_imms}, nil}, 1246 // ROR <Xd>, <Xs>, #<shift> 1247 {0xffe00000, 0x93c00000, ROR, instArgs{arg_Xd, arg_Xs, arg_immediate_0_63_imms}, ror_extr_64_extract_cond}, 1248 // EXTR <Xd>, <Xn>, <Xm>, #<lsb> 1249 {0xffe00000, 0x93c00000, EXTR, instArgs{arg_Xd, arg_Xn, arg_Xm, arg_immediate_0_63_imms}, nil}, 1250 // NOP 1251 {0xffffffff, 0xd503201f, NOP, instArgs{}, nil}, 1252 // SEV 1253 {0xffffffff, 0xd503209f, SEV, instArgs{}, nil}, 1254 // SEVL 1255 {0xffffffff, 0xd50320bf, SEVL, instArgs{}, nil}, 1256 // WFE 1257 {0xffffffff, 0xd503205f, WFE, instArgs{}, nil}, 1258 // WFI 1259 {0xffffffff, 0xd503207f, WFI, instArgs{}, nil}, 1260 // YIELD 1261 {0xffffffff, 0xd503203f, YIELD, instArgs{}, nil}, 1262 // HINT #<imm> 1263 {0xfffff01f, 0xd503201f, HINT, instArgs{arg_immediate_0_127_CRm_op2}, nil}, 1264 // HLT #<imm> 1265 {0xffe0001f, 0xd4400000, HLT, instArgs{arg_immediate_0_65535_imm16}, nil}, 1266 // ISB {<option>|<imm>} 1267 {0xfffff0ff, 0xd50330df, ISB, instArgs{arg_option_ISB_BI_system_CRm}, nil}, 1268 // LDAR <Wt>, [<Xn|SP>{, #0}] 1269 {0xffe08000, 0x88c08000, LDAR, instArgs{arg_Wt, arg_Xns_mem}, nil}, 1270 // LDAR <Xt>, [<Xn|SP>{, #0}] 1271 {0xffe08000, 0xc8c08000, LDAR, instArgs{arg_Xt, arg_Xns_mem}, nil}, 1272 // LDARB <Wt>, [<Xn|SP>{, #0}] 1273 {0xffe08000, 0x08c08000, LDARB, instArgs{arg_Wt, arg_Xns_mem}, nil}, 1274 // LDARH <Wt>, [<Xn|SP>{, #0}] 1275 {0xffe08000, 0x48c08000, LDARH, instArgs{arg_Wt, arg_Xns_mem}, nil}, 1276 // LDAXP <Wt>, <Wt2>, [<Xn|SP>{, #0}] 1277 {0xffe08000, 0x88608000, LDAXP, instArgs{arg_Wt, arg_Wt2, arg_Xns_mem}, nil}, 1278 // LDAXP <Xt>, <Xt2>, [<Xn|SP>{, #0}] 1279 {0xffe08000, 0xc8608000, LDAXP, instArgs{arg_Xt, arg_Xt2, arg_Xns_mem}, nil}, 1280 // LDAXR <Wt>, [<Xn|SP>{, #0}] 1281 {0xffe08000, 0x88408000, LDAXR, instArgs{arg_Wt, arg_Xns_mem}, nil}, 1282 // LDAXR <Xt>, [<Xn|SP>{, #0}] 1283 {0xffe08000, 0xc8408000, LDAXR, instArgs{arg_Xt, arg_Xns_mem}, nil}, 1284 // LDAXRB <Wt>, [<Xn|SP>{, #0}] 1285 {0xffe08000, 0x08408000, LDAXRB, instArgs{arg_Wt, arg_Xns_mem}, nil}, 1286 // LDAXRH <Wt>, [<Xn|SP>{, #0}] 1287 {0xffe08000, 0x48408000, LDAXRH, instArgs{arg_Wt, arg_Xns_mem}, nil}, 1288 // LDNP <Wt>, <Wt2>, [<Xn|SP>{, #<imm>}] 1289 {0xffc00000, 0x28400000, LDNP, instArgs{arg_Wt, arg_Wt2, arg_Xns_mem_optional_imm7_4_signed}, nil}, 1290 // LDNP <Xt>, <Xt2>, [<Xn|SP>{, #<imm_1>}] 1291 {0xffc00000, 0xa8400000, LDNP, instArgs{arg_Xt, arg_Xt2, arg_Xns_mem_optional_imm7_8_signed}, nil}, 1292 // LDP <Wt>, <Wt2>, [<Xn|SP>], #<imm_1> 1293 {0xffc00000, 0x28c00000, LDP, instArgs{arg_Wt, arg_Wt2, arg_Xns_mem_post_imm7_4_signed}, nil}, 1294 // LDP <Xt>, <Xt2>, [<Xn|SP>], #<imm_3> 1295 {0xffc00000, 0xa8c00000, LDP, instArgs{arg_Xt, arg_Xt2, arg_Xns_mem_post_imm7_8_signed}, nil}, 1296 // LDP <Wt>, <Wt2>, [<Xn|SP>{, #<imm_1>}]! 1297 {0xffc00000, 0x29c00000, LDP, instArgs{arg_Wt, arg_Wt2, arg_Xns_mem_wb_imm7_4_signed}, nil}, 1298 // LDP <Xt>, <Xt2>, [<Xn|SP>{, #<imm_3>}]! 1299 {0xffc00000, 0xa9c00000, LDP, instArgs{arg_Xt, arg_Xt2, arg_Xns_mem_wb_imm7_8_signed}, nil}, 1300 // LDP <Wt>, <Wt2>, [<Xn|SP>{, #<imm>}] 1301 {0xffc00000, 0x29400000, LDP, instArgs{arg_Wt, arg_Wt2, arg_Xns_mem_optional_imm7_4_signed}, nil}, 1302 // LDP <Xt>, <Xt2>, [<Xn|SP>{, #<imm_2>}] 1303 {0xffc00000, 0xa9400000, LDP, instArgs{arg_Xt, arg_Xt2, arg_Xns_mem_optional_imm7_8_signed}, nil}, 1304 // LDPSW <Xt>, <Xt2>, [<Xn|SP>], #<imm_1> 1305 {0xffc00000, 0x68c00000, LDPSW, instArgs{arg_Xt, arg_Xt2, arg_Xns_mem_post_imm7_4_signed}, nil}, 1306 // LDPSW <Xt>, <Xt2>, [<Xn|SP>{, #<imm_1>}]! 1307 {0xffc00000, 0x69c00000, LDPSW, instArgs{arg_Xt, arg_Xt2, arg_Xns_mem_wb_imm7_4_signed}, nil}, 1308 // LDPSW <Xt>, <Xt2>, [<Xn|SP>{, #<imm>}] 1309 {0xffc00000, 0x69400000, LDPSW, instArgs{arg_Xt, arg_Xt2, arg_Xns_mem_optional_imm7_4_signed}, nil}, 1310 // LDR <Wt>, [<Xn|SP>], #<simm> 1311 {0xffe00c00, 0xb8400400, LDR, instArgs{arg_Wt, arg_Xns_mem_post_imm9_1_signed}, nil}, 1312 // LDR <Xt>, [<Xn|SP>], #<simm> 1313 {0xffe00c00, 0xf8400400, LDR, instArgs{arg_Xt, arg_Xns_mem_post_imm9_1_signed}, nil}, 1314 // LDR <Wt>, [<Xn|SP>{, #<simm>}]! 1315 {0xffe00c00, 0xb8400c00, LDR, instArgs{arg_Wt, arg_Xns_mem_wb_imm9_1_signed}, nil}, 1316 // LDR <Xt>, [<Xn|SP>{, #<simm>}]! 1317 {0xffe00c00, 0xf8400c00, LDR, instArgs{arg_Xt, arg_Xns_mem_wb_imm9_1_signed}, nil}, 1318 // LDR <Wt>, [<Xn|SP>{, #<pimm>}] 1319 {0xffc00000, 0xb9400000, LDR, instArgs{arg_Wt, arg_Xns_mem_optional_imm12_4_unsigned}, nil}, 1320 // LDR <Xt>, [<Xn|SP>{, #<pimm_1>}] 1321 {0xffc00000, 0xf9400000, LDR, instArgs{arg_Xt, arg_Xns_mem_optional_imm12_8_unsigned}, nil}, 1322 // LDR <Wt>, <label> 1323 {0xff000000, 0x18000000, LDR, instArgs{arg_Wt, arg_slabel_imm19_2}, nil}, 1324 // LDR <Xt>, <label> 1325 {0xff000000, 0x58000000, LDR, instArgs{arg_Xt, arg_slabel_imm19_2}, nil}, 1326 // LDR <Wt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}] 1327 {0xffe00c00, 0xb8600800, LDR, instArgs{arg_Wt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__2_1}, nil}, 1328 // LDR <Xt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}] 1329 {0xffe00c00, 0xf8600800, LDR, instArgs{arg_Xt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__3_1}, nil}, 1330 // LDRB <Wt>, [<Xn|SP>], #<simm> 1331 {0xffe00c00, 0x38400400, LDRB, instArgs{arg_Wt, arg_Xns_mem_post_imm9_1_signed}, nil}, 1332 // LDRB <Wt>, [<Xn|SP>{, #<simm>}]! 1333 {0xffe00c00, 0x38400c00, LDRB, instArgs{arg_Wt, arg_Xns_mem_wb_imm9_1_signed}, nil}, 1334 // LDRB <Wt>, [<Xn|SP>{, #<pimm>}] 1335 {0xffc00000, 0x39400000, LDRB, instArgs{arg_Wt, arg_Xns_mem_optional_imm12_1_unsigned}, nil}, 1336 // LDRB <Wt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}] 1337 {0xffe00c00, 0x38600800, LDRB, instArgs{arg_Wt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__absent_0__0_1}, nil}, 1338 // LDRH <Wt>, [<Xn|SP>], #<simm> 1339 {0xffe00c00, 0x78400400, LDRH, instArgs{arg_Wt, arg_Xns_mem_post_imm9_1_signed}, nil}, 1340 // LDRH <Wt>, [<Xn|SP>{, #<simm>}]! 1341 {0xffe00c00, 0x78400c00, LDRH, instArgs{arg_Wt, arg_Xns_mem_wb_imm9_1_signed}, nil}, 1342 // LDRH <Wt>, [<Xn|SP>{, #<pimm>}] 1343 {0xffc00000, 0x79400000, LDRH, instArgs{arg_Wt, arg_Xns_mem_optional_imm12_2_unsigned}, nil}, 1344 // LDRH <Wt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}] 1345 {0xffe00c00, 0x78600800, LDRH, instArgs{arg_Wt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__1_1}, nil}, 1346 // LDRSB <Wt>, [<Xn|SP>], #<simm> 1347 {0xffe00c00, 0x38c00400, LDRSB, instArgs{arg_Wt, arg_Xns_mem_post_imm9_1_signed}, nil}, 1348 // LDRSB <Xt>, [<Xn|SP>], #<simm> 1349 {0xffe00c00, 0x38800400, LDRSB, instArgs{arg_Xt, arg_Xns_mem_post_imm9_1_signed}, nil}, 1350 // LDRSB <Wt>, [<Xn|SP>{, #<simm>}]! 1351 {0xffe00c00, 0x38c00c00, LDRSB, instArgs{arg_Wt, arg_Xns_mem_wb_imm9_1_signed}, nil}, 1352 // LDRSB <Xt>, [<Xn|SP>{, #<simm>}]! 1353 {0xffe00c00, 0x38800c00, LDRSB, instArgs{arg_Xt, arg_Xns_mem_wb_imm9_1_signed}, nil}, 1354 // LDRSB <Wt>, [<Xn|SP>{, #<pimm>}] 1355 {0xffc00000, 0x39c00000, LDRSB, instArgs{arg_Wt, arg_Xns_mem_optional_imm12_1_unsigned}, nil}, 1356 // LDRSB <Xt>, [<Xn|SP>{, #<pimm>}] 1357 {0xffc00000, 0x39800000, LDRSB, instArgs{arg_Xt, arg_Xns_mem_optional_imm12_1_unsigned}, nil}, 1358 // LDRSB <Wt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}] 1359 {0xffe00c00, 0x38e00800, LDRSB, instArgs{arg_Wt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__absent_0__0_1}, nil}, 1360 // LDRSB <Xt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}] 1361 {0xffe00c00, 0x38a00800, LDRSB, instArgs{arg_Xt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__absent_0__0_1}, nil}, 1362 // LDRSH <Wt>, [<Xn|SP>], #<simm> 1363 {0xffe00c00, 0x78c00400, LDRSH, instArgs{arg_Wt, arg_Xns_mem_post_imm9_1_signed}, nil}, 1364 // LDRSH <Xt>, [<Xn|SP>], #<simm> 1365 {0xffe00c00, 0x78800400, LDRSH, instArgs{arg_Xt, arg_Xns_mem_post_imm9_1_signed}, nil}, 1366 // LDRSH <Wt>, [<Xn|SP>{, #<simm>}]! 1367 {0xffe00c00, 0x78c00c00, LDRSH, instArgs{arg_Wt, arg_Xns_mem_wb_imm9_1_signed}, nil}, 1368 // LDRSH <Xt>, [<Xn|SP>{, #<simm>}]! 1369 {0xffe00c00, 0x78800c00, LDRSH, instArgs{arg_Xt, arg_Xns_mem_wb_imm9_1_signed}, nil}, 1370 // LDRSH <Wt>, [<Xn|SP>{, #<pimm>}] 1371 {0xffc00000, 0x79c00000, LDRSH, instArgs{arg_Wt, arg_Xns_mem_optional_imm12_2_unsigned}, nil}, 1372 // LDRSH <Xt>, [<Xn|SP>{, #<pimm>}] 1373 {0xffc00000, 0x79800000, LDRSH, instArgs{arg_Xt, arg_Xns_mem_optional_imm12_2_unsigned}, nil}, 1374 // LDRSH <Wt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}] 1375 {0xffe00c00, 0x78e00800, LDRSH, instArgs{arg_Wt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__1_1}, nil}, 1376 // LDRSH <Xt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}] 1377 {0xffe00c00, 0x78a00800, LDRSH, instArgs{arg_Xt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__1_1}, nil}, 1378 // LDRSW <Xt>, [<Xn|SP>], #<simm> 1379 {0xffe00c00, 0xb8800400, LDRSW, instArgs{arg_Xt, arg_Xns_mem_post_imm9_1_signed}, nil}, 1380 // LDRSW <Xt>, [<Xn|SP>{, #<simm>}]! 1381 {0xffe00c00, 0xb8800c00, LDRSW, instArgs{arg_Xt, arg_Xns_mem_wb_imm9_1_signed}, nil}, 1382 // LDRSW <Xt>, [<Xn|SP>{, #<pimm>}] 1383 {0xffc00000, 0xb9800000, LDRSW, instArgs{arg_Xt, arg_Xns_mem_optional_imm12_4_unsigned}, nil}, 1384 // LDRSW <Xt>, <label> 1385 {0xff000000, 0x98000000, LDRSW, instArgs{arg_Xt, arg_slabel_imm19_2}, nil}, 1386 // LDRSW <Xt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}] 1387 {0xffe00c00, 0xb8a00800, LDRSW, instArgs{arg_Xt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__2_1}, nil}, 1388 // LDTR <Wt>, [<Xn|SP>{, #<simm>}] 1389 {0xffe00c00, 0xb8400800, LDTR, instArgs{arg_Wt, arg_Xns_mem_optional_imm9_1_signed}, nil}, 1390 // LDTR <Xt>, [<Xn|SP>{, #<simm>}] 1391 {0xffe00c00, 0xf8400800, LDTR, instArgs{arg_Xt, arg_Xns_mem_optional_imm9_1_signed}, nil}, 1392 // LDTRB <Wt>, [<Xn|SP>{, #<simm>}] 1393 {0xffe00c00, 0x38400800, LDTRB, instArgs{arg_Wt, arg_Xns_mem_optional_imm9_1_signed}, nil}, 1394 // LDTRH <Wt>, [<Xn|SP>{, #<simm>}] 1395 {0xffe00c00, 0x78400800, LDTRH, instArgs{arg_Wt, arg_Xns_mem_optional_imm9_1_signed}, nil}, 1396 // LDTRSB <Wt>, [<Xn|SP>{, #<simm>}] 1397 {0xffe00c00, 0x38c00800, LDTRSB, instArgs{arg_Wt, arg_Xns_mem_optional_imm9_1_signed}, nil}, 1398 // LDTRSB <Xt>, [<Xn|SP>{, #<simm>}] 1399 {0xffe00c00, 0x38800800, LDTRSB, instArgs{arg_Xt, arg_Xns_mem_optional_imm9_1_signed}, nil}, 1400 // LDTRSH <Wt>, [<Xn|SP>{, #<simm>}] 1401 {0xffe00c00, 0x78c00800, LDTRSH, instArgs{arg_Wt, arg_Xns_mem_optional_imm9_1_signed}, nil}, 1402 // LDTRSH <Xt>, [<Xn|SP>{, #<simm>}] 1403 {0xffe00c00, 0x78800800, LDTRSH, instArgs{arg_Xt, arg_Xns_mem_optional_imm9_1_signed}, nil}, 1404 // LDTRSW <Xt>, [<Xn|SP>{, #<simm>}] 1405 {0xffe00c00, 0xb8800800, LDTRSW, instArgs{arg_Xt, arg_Xns_mem_optional_imm9_1_signed}, nil}, 1406 // LDUR <Wt>, [<Xn|SP>{, #<simm>}] 1407 {0xffe00c00, 0xb8400000, LDUR, instArgs{arg_Wt, arg_Xns_mem_optional_imm9_1_signed}, nil}, 1408 // LDUR <Xt>, [<Xn|SP>{, #<simm>}] 1409 {0xffe00c00, 0xf8400000, LDUR, instArgs{arg_Xt, arg_Xns_mem_optional_imm9_1_signed}, nil}, 1410 // LDURB <Wt>, [<Xn|SP>{, #<simm>}] 1411 {0xffe00c00, 0x38400000, LDURB, instArgs{arg_Wt, arg_Xns_mem_optional_imm9_1_signed}, nil}, 1412 // LDURH <Wt>, [<Xn|SP>{, #<simm>}] 1413 {0xffe00c00, 0x78400000, LDURH, instArgs{arg_Wt, arg_Xns_mem_optional_imm9_1_signed}, nil}, 1414 // LDURSB <Wt>, [<Xn|SP>{, #<simm>}] 1415 {0xffe00c00, 0x38c00000, LDURSB, instArgs{arg_Wt, arg_Xns_mem_optional_imm9_1_signed}, nil}, 1416 // LDURSB <Xt>, [<Xn|SP>{, #<simm>}] 1417 {0xffe00c00, 0x38800000, LDURSB, instArgs{arg_Xt, arg_Xns_mem_optional_imm9_1_signed}, nil}, 1418 // LDURSH <Wt>, [<Xn|SP>{, #<simm>}] 1419 {0xffe00c00, 0x78c00000, LDURSH, instArgs{arg_Wt, arg_Xns_mem_optional_imm9_1_signed}, nil}, 1420 // LDURSH <Xt>, [<Xn|SP>{, #<simm>}] 1421 {0xffe00c00, 0x78800000, LDURSH, instArgs{arg_Xt, arg_Xns_mem_optional_imm9_1_signed}, nil}, 1422 // LDURSW <Xt>, [<Xn|SP>{, #<simm>}] 1423 {0xffe00c00, 0xb8800000, LDURSW, instArgs{arg_Xt, arg_Xns_mem_optional_imm9_1_signed}, nil}, 1424 // LDXP <Wt>, <Wt2>, [<Xn|SP>{, #0}] 1425 {0xffe08000, 0x88600000, LDXP, instArgs{arg_Wt, arg_Wt2, arg_Xns_mem}, nil}, 1426 // LDXP <Xt>, <Xt2>, [<Xn|SP>{, #0}] 1427 {0xffe08000, 0xc8600000, LDXP, instArgs{arg_Xt, arg_Xt2, arg_Xns_mem}, nil}, 1428 // LDXR <Wt>, [<Xn|SP>{, #0}] 1429 {0xffe08000, 0x88400000, LDXR, instArgs{arg_Wt, arg_Xns_mem}, nil}, 1430 // LDXR <Xt>, [<Xn|SP>{, #0}] 1431 {0xffe08000, 0xc8400000, LDXR, instArgs{arg_Xt, arg_Xns_mem}, nil}, 1432 // LDXRB <Wt>, [<Xn|SP>{, #0}] 1433 {0xffe08000, 0x08400000, LDXRB, instArgs{arg_Wt, arg_Xns_mem}, nil}, 1434 // LDXRH <Wt>, [<Xn|SP>{, #0}] 1435 {0xffe08000, 0x48400000, LDXRH, instArgs{arg_Wt, arg_Xns_mem}, nil}, 1436 // LSL <Wd>, <Wn>, #<shift> 1437 {0xffc08000, 0x53000000, LSL, instArgs{arg_Wd, arg_Wn, arg_immediate_LSL_UBFM_32M_bitfield_0_31_immr}, lsl_ubfm_32m_bitfield_cond}, 1438 // LSR <Wd>, <Wn>, #<shift> 1439 {0xffc0fc00, 0x53007c00, LSR, instArgs{arg_Wd, arg_Wn, arg_immediate_LSR_UBFM_32M_bitfield_0_31_immr}, nil}, 1440 // UBFIZ <Wd>, <Wn>, #<lsb>, #<width> 1441 {0xffc00000, 0x53000000, UBFIZ, instArgs{arg_Wd, arg_Wn, arg_immediate_UBFIZ_UBFM_32M_bitfield_lsb_32_immr, arg_immediate_UBFIZ_UBFM_32M_bitfield_width_32_imms}, ubfiz_ubfm_32m_bitfield_cond}, 1442 // UBFX <Wd>, <Wn>, #<lsb>, #<width> 1443 {0xffc00000, 0x53000000, UBFX, instArgs{arg_Wd, arg_Wn, arg_immediate_UBFX_UBFM_32M_bitfield_lsb_32_immr, arg_immediate_UBFX_UBFM_32M_bitfield_width_32_imms}, ubfx_ubfm_32m_bitfield_cond}, 1444 // UXTB <Wd>, <Wn> 1445 {0xfffffc00, 0x53001c00, UXTB, instArgs{arg_Wd, arg_Wn}, nil}, 1446 // UXTH <Wd>, <Wn> 1447 {0xfffffc00, 0x53003c00, UXTH, instArgs{arg_Wd, arg_Wn}, nil}, 1448 // UBFM <Wd>, <Wn>, #<immr>, #<imms> 1449 {0xffc00000, 0x53000000, UBFM, instArgs{arg_Wd, arg_Wn, arg_immediate_0_31_immr, arg_immediate_0_31_imms}, nil}, 1450 // LSL <Xd>, <Xn>, #<shift> 1451 {0xffc00000, 0xd3400000, LSL, instArgs{arg_Xd, arg_Xn, arg_immediate_LSL_UBFM_64M_bitfield_0_63_immr}, lsl_ubfm_64m_bitfield_cond}, 1452 // LSR <Xd>, <Xn>, #<shift> 1453 {0xffc0fc00, 0xd340fc00, LSR, instArgs{arg_Xd, arg_Xn, arg_immediate_LSR_UBFM_64M_bitfield_0_63_immr}, nil}, 1454 // UBFIZ <Xd>, <Xn>, #<lsb>, #<width> 1455 {0xffc00000, 0xd3400000, UBFIZ, instArgs{arg_Xd, arg_Xn, arg_immediate_UBFIZ_UBFM_64M_bitfield_lsb_64_immr, arg_immediate_UBFIZ_UBFM_64M_bitfield_width_64_imms}, ubfiz_ubfm_64m_bitfield_cond}, 1456 // UBFX <Xd>, <Xn>, #<lsb>, #<width> 1457 {0xffc00000, 0xd3400000, UBFX, instArgs{arg_Xd, arg_Xn, arg_immediate_UBFX_UBFM_64M_bitfield_lsb_64_immr, arg_immediate_UBFX_UBFM_64M_bitfield_width_64_imms}, ubfx_ubfm_64m_bitfield_cond}, 1458 // UBFM <Xd>, <Xn>, #<immr>, #<imms> 1459 {0xffc00000, 0xd3400000, UBFM, instArgs{arg_Xd, arg_Xn, arg_immediate_0_63_immr, arg_immediate_0_63_imms}, nil}, 1460 // LSL <Wd>, <Wn>, <Wm> 1461 {0xffe0fc00, 0x1ac02000, LSL, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil}, 1462 // LSLV <Wd>, <Wn>, <Wm> 1463 {0xffe0fc00, 0x1ac02000, LSLV, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil}, 1464 // LSL <Xd>, <Xn>, <Xm> 1465 {0xffe0fc00, 0x9ac02000, LSL, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil}, 1466 // LSLV <Xd>, <Xn>, <Xm> 1467 {0xffe0fc00, 0x9ac02000, LSLV, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil}, 1468 // LSR <Wd>, <Wn>, <Wm> 1469 {0xffe0fc00, 0x1ac02400, LSR, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil}, 1470 // LSRV <Wd>, <Wn>, <Wm> 1471 {0xffe0fc00, 0x1ac02400, LSRV, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil}, 1472 // LSR <Xd>, <Xn>, <Xm> 1473 {0xffe0fc00, 0x9ac02400, LSR, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil}, 1474 // LSRV <Xd>, <Xn>, <Xm> 1475 {0xffe0fc00, 0x9ac02400, LSRV, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil}, 1476 // MUL <Wd>, <Wn>, <Wm> 1477 {0xffe0fc00, 0x1b007c00, MUL, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil}, 1478 // MADD <Wd>, <Wn>, <Wm>, <Wa> 1479 {0xffe08000, 0x1b000000, MADD, instArgs{arg_Wd, arg_Wn, arg_Wm, arg_Wa}, nil}, 1480 // MUL <Xd>, <Xn>, <Xm> 1481 {0xffe0fc00, 0x9b007c00, MUL, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil}, 1482 // MADD <Xd>, <Xn>, <Xm>, <Xa> 1483 {0xffe08000, 0x9b000000, MADD, instArgs{arg_Xd, arg_Xn, arg_Xm, arg_Xa}, nil}, 1484 // MNEG <Wd>, <Wn>, <Wm> 1485 {0xffe0fc00, 0x1b00fc00, MNEG, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil}, 1486 // MSUB <Wd>, <Wn>, <Wm>, <Wa> 1487 {0xffe08000, 0x1b008000, MSUB, instArgs{arg_Wd, arg_Wn, arg_Wm, arg_Wa}, nil}, 1488 // MNEG <Xd>, <Xn>, <Xm> 1489 {0xffe0fc00, 0x9b00fc00, MNEG, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil}, 1490 // MSUB <Xd>, <Xn>, <Xm>, <Xa> 1491 {0xffe08000, 0x9b008000, MSUB, instArgs{arg_Xd, arg_Xn, arg_Xm, arg_Xa}, nil}, 1492 // MOV <Wd|WSP>, #<imm> 1493 {0xffc003e0, 0x320003e0, MOV, instArgs{arg_Wds, arg_immediate_bitmask_32_imms_immr}, mov_orr_32_log_imm_cond}, 1494 // ORR <Wd|WSP>, <Wn>, #<imm> 1495 {0xffc00000, 0x32000000, ORR, instArgs{arg_Wds, arg_Wn, arg_immediate_bitmask_32_imms_immr}, nil}, 1496 // MOV <Xd|SP>, #<imm> 1497 {0xff8003e0, 0xb20003e0, MOV, instArgs{arg_Xds, arg_immediate_bitmask_64_N_imms_immr}, mov_orr_64_log_imm_cond}, 1498 // ORR <Xd|SP>, <Xn>, #<imm> 1499 {0xff800000, 0xb2000000, ORR, instArgs{arg_Xds, arg_Xn, arg_immediate_bitmask_64_N_imms_immr}, nil}, 1500 // MOV <Wd>, #<imm> 1501 {0xff800000, 0x12800000, MOV, instArgs{arg_Wd, arg_immediate_shift_32_implicit_inverse_imm16_hw}, mov_movn_32_movewide_cond}, 1502 // MOVN <Wd>, #<imm>{, LSL #<shift>} 1503 {0xff800000, 0x12800000, MOVN, instArgs{arg_Wd, arg_immediate_OptLSL_amount_16_0_16}, nil}, 1504 // MOV <Xd>, #<imm> 1505 {0xff800000, 0x92800000, MOV, instArgs{arg_Xd, arg_immediate_shift_64_implicit_inverse_imm16_hw}, mov_movn_64_movewide_cond}, 1506 // MOVN <Xd>, #<imm>{, LSL #<shift>} 1507 {0xff800000, 0x92800000, MOVN, instArgs{arg_Xd, arg_immediate_OptLSL_amount_16_0_48}, nil}, 1508 // MOV <Wd>, <Wm> 1509 {0xffe0ffe0, 0x2a0003e0, MOV, instArgs{arg_Wd, arg_Wm}, nil}, 1510 // ORR <Wd>, <Wn>, <Wm> {, <shift> #<amount> } 1511 {0xff208000, 0x2a000000, ORR, instArgs{arg_Wd, arg_Wn, arg_Wm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_31}, nil}, 1512 // MOV <Xd>, <Xm> 1513 {0xffe0ffe0, 0xaa0003e0, MOV, instArgs{arg_Xd, arg_Xm}, nil}, 1514 // ORR <Xd>, <Xn>, <Xm> {, <shift> #<amount> } 1515 {0xff200000, 0xaa000000, ORR, instArgs{arg_Xd, arg_Xn, arg_Xm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_63}, nil}, 1516 // MOV <Wd>, #<imm> 1517 {0xff800000, 0x52800000, MOV, instArgs{arg_Wd, arg_immediate_shift_32_implicit_imm16_hw}, mov_movz_32_movewide_cond}, 1518 // MOVZ <Wd>, #<imm>{, LSL #<shift>} 1519 {0xff800000, 0x52800000, MOVZ, instArgs{arg_Wd, arg_immediate_OptLSL_amount_16_0_16}, nil}, 1520 // MOV <Xd>, #<imm> 1521 {0xff800000, 0xd2800000, MOV, instArgs{arg_Xd, arg_immediate_shift_64_implicit_imm16_hw}, mov_movz_64_movewide_cond}, 1522 // MOVZ <Xd>, #<imm>{, LSL #<shift>} 1523 {0xff800000, 0xd2800000, MOVZ, instArgs{arg_Xd, arg_immediate_OptLSL_amount_16_0_48}, nil}, 1524 // MOVK <Wd>, #<imm>{, LSL #<shift>} 1525 {0xff800000, 0x72800000, MOVK, instArgs{arg_Wd, arg_immediate_OptLSL_amount_16_0_16}, nil}, 1526 // MOVK <Xd>, #<imm>{, LSL #<shift>} 1527 {0xff800000, 0xf2800000, MOVK, instArgs{arg_Xd, arg_immediate_OptLSL_amount_16_0_48}, nil}, 1528 // MRS <Xt>, <systemreg> 1529 {0xfff00000, 0xd5300000, MRS, instArgs{arg_Xt, arg_sysreg_o0_op1_CRn_CRm_op2}, nil}, 1530 // MSR <pstatefield>, #<imm> 1531 {0xfff8f01f, 0xd500401f, MSR, instArgs{arg_pstatefield_op1_op2__SPSel_05__DAIFSet_36__DAIFClr_37, arg_immediate_0_15_CRm}, nil}, 1532 // MSR <systemreg>, <Xt> 1533 {0xfff00000, 0xd5100000, MSR, instArgs{arg_sysreg_o0_op1_CRn_CRm_op2, arg_Xt}, nil}, 1534 // MVN <Wd>, <Wm> {, <shift> #<amount> } 1535 {0xff2003e0, 0x2a2003e0, MVN, instArgs{arg_Wd, arg_Wm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_31}, nil}, 1536 // ORN <Wd>, <Wn>, <Wm> {, <shift> #<amount> } 1537 {0xff208000, 0x2a200000, ORN, instArgs{arg_Wd, arg_Wn, arg_Wm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_31}, nil}, 1538 // MVN <Xd>, <Xm> {, <shift> #<amount> } 1539 {0xff2003e0, 0xaa2003e0, MVN, instArgs{arg_Xd, arg_Xm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_63}, nil}, 1540 // ORN <Xd>, <Xn>, <Xm> {, <shift> #<amount> } 1541 {0xff200000, 0xaa200000, ORN, instArgs{arg_Xd, arg_Xn, arg_Xm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_63}, nil}, 1542 // NEG <Wd>, <Wm> {, <shift> #<amount> } 1543 {0xff2003e0, 0x4b0003e0, NEG, instArgs{arg_Wd, arg_Wm_shift__LSL_0__LSR_1__ASR_2__0_31}, nil}, 1544 // SUB <Wd>, <Wn>, <Wm> {, <shift> #<amount> } 1545 {0xff208000, 0x4b000000, SUB, instArgs{arg_Wd, arg_Wn, arg_Wm_shift__LSL_0__LSR_1__ASR_2__0_31}, nil}, 1546 // NEG <Xd>, <Xm> {, <shift> #<amount> } 1547 {0xff2003e0, 0xcb0003e0, NEG, instArgs{arg_Xd, arg_Xm_shift__LSL_0__LSR_1__ASR_2__0_63}, nil}, 1548 // SUB <Xd>, <Xn>, <Xm> {, <shift> #<amount> } 1549 {0xff200000, 0xcb000000, SUB, instArgs{arg_Xd, arg_Xn, arg_Xm_shift__LSL_0__LSR_1__ASR_2__0_63}, nil}, 1550 // NGC <Wd>, <Wm> 1551 {0xffe0ffe0, 0x5a0003e0, NGC, instArgs{arg_Wd, arg_Wm}, nil}, 1552 // SBC <Wd>, <Wn>, <Wm> 1553 {0xffe0fc00, 0x5a000000, SBC, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil}, 1554 // NGC <Xd>, <Xm> 1555 {0xffe0ffe0, 0xda0003e0, NGC, instArgs{arg_Xd, arg_Xm}, nil}, 1556 // SBC <Xd>, <Xn>, <Xm> 1557 {0xffe0fc00, 0xda000000, SBC, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil}, 1558 // NGCS <Wd>, <Wm> 1559 {0xffe0ffe0, 0x7a0003e0, NGCS, instArgs{arg_Wd, arg_Wm}, nil}, 1560 // SBCS <Wd>, <Wn>, <Wm> 1561 {0xffe0fc00, 0x7a000000, SBCS, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil}, 1562 // NGCS <Xd>, <Xm> 1563 {0xffe0ffe0, 0xfa0003e0, NGCS, instArgs{arg_Xd, arg_Xm}, nil}, 1564 // SBCS <Xd>, <Xn>, <Xm> 1565 {0xffe0fc00, 0xfa000000, SBCS, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil}, 1566 // PRFM <prfop>, [<Xn|SP>{, #<pimm>}] 1567 {0xffc00000, 0xf9800000, PRFM, instArgs{arg_prfop_Rt, arg_Xns_mem_optional_imm12_8_unsigned}, nil}, 1568 // PRFM <prfop>, <label> 1569 {0xff000000, 0xd8000000, PRFM, instArgs{arg_prfop_Rt, arg_slabel_imm19_2}, nil}, 1570 // PRFM <prfop>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}] 1571 {0xffe00c00, 0xf8a00800, PRFM, instArgs{arg_prfop_Rt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__3_1}, nil}, 1572 // PRFUM <prfop>, [<Xn|SP>{, #<simm>}] 1573 {0xffe00c00, 0xf8800000, PRFUM, instArgs{arg_prfop_Rt, arg_Xns_mem_optional_imm9_1_signed}, nil}, 1574 // RBIT <Wd>, <Wn> 1575 {0xfffffc00, 0x5ac00000, RBIT, instArgs{arg_Wd, arg_Wn}, nil}, 1576 // RBIT <Xd>, <Xn> 1577 {0xfffffc00, 0xdac00000, RBIT, instArgs{arg_Xd, arg_Xn}, nil}, 1578 // RET {<Xn>} 1579 {0xfffffc1f, 0xd65f0000, RET, instArgs{arg_Xn}, nil}, 1580 // REV <Wd>, <Wn> 1581 {0xfffffc00, 0x5ac00800, REV, instArgs{arg_Wd, arg_Wn}, nil}, 1582 // REV <Xd>, <Xn> 1583 {0xfffffc00, 0xdac00c00, REV, instArgs{arg_Xd, arg_Xn}, nil}, 1584 // REV16 <Wd>, <Wn> 1585 {0xfffffc00, 0x5ac00400, REV16, instArgs{arg_Wd, arg_Wn}, nil}, 1586 // REV16 <Xd>, <Xn> 1587 {0xfffffc00, 0xdac00400, REV16, instArgs{arg_Xd, arg_Xn}, nil}, 1588 // REV32 <Xd>, <Xn> 1589 {0xfffffc00, 0xdac00800, REV32, instArgs{arg_Xd, arg_Xn}, nil}, 1590 // ROR <Wd>, <Wn>, <Wm> 1591 {0xffe0fc00, 0x1ac02c00, ROR, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil}, 1592 // RORV <Wd>, <Wn>, <Wm> 1593 {0xffe0fc00, 0x1ac02c00, RORV, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil}, 1594 // ROR <Xd>, <Xn>, <Xm> 1595 {0xffe0fc00, 0x9ac02c00, ROR, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil}, 1596 // RORV <Xd>, <Xn>, <Xm> 1597 {0xffe0fc00, 0x9ac02c00, RORV, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil}, 1598 // SDIV <Wd>, <Wn>, <Wm> 1599 {0xffe0fc00, 0x1ac00c00, SDIV, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil}, 1600 // SDIV <Xd>, <Xn>, <Xm> 1601 {0xffe0fc00, 0x9ac00c00, SDIV, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil}, 1602 // SMULL <Xd>, <Wn>, <Wm> 1603 {0xffe0fc00, 0x9b207c00, SMULL, instArgs{arg_Xd, arg_Wn, arg_Wm}, nil}, 1604 // SMADDL <Xd>, <Wn>, <Wm>, <Xa> 1605 {0xffe08000, 0x9b200000, SMADDL, instArgs{arg_Xd, arg_Wn, arg_Wm, arg_Xa}, nil}, 1606 // SMNEGL <Xd>, <Wn>, <Wm> 1607 {0xffe0fc00, 0x9b20fc00, SMNEGL, instArgs{arg_Xd, arg_Wn, arg_Wm}, nil}, 1608 // SMSUBL <Xd>, <Wn>, <Wm>, <Xa> 1609 {0xffe08000, 0x9b208000, SMSUBL, instArgs{arg_Xd, arg_Wn, arg_Wm, arg_Xa}, nil}, 1610 // SMULH <Xd>, <Xn>, <Xm> 1611 {0xffe08000, 0x9b400000, SMULH, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil}, 1612 // STLR <Wt>, [<Xn|SP>{, #0}] 1613 {0xffe08000, 0x88808000, STLR, instArgs{arg_Wt, arg_Xns_mem}, nil}, 1614 // STLR <Xt>, [<Xn|SP>{, #0}] 1615 {0xffe08000, 0xc8808000, STLR, instArgs{arg_Xt, arg_Xns_mem}, nil}, 1616 // STLRB <Wt>, [<Xn|SP>{, #0}] 1617 {0xffe08000, 0x08808000, STLRB, instArgs{arg_Wt, arg_Xns_mem}, nil}, 1618 // STLRH <Wt>, [<Xn|SP>{, #0}] 1619 {0xffe08000, 0x48808000, STLRH, instArgs{arg_Wt, arg_Xns_mem}, nil}, 1620 // STLXP <Ws>, <Wt>, <Wt2>, [<Xn|SP>{, #0}] 1621 {0xffe08000, 0x88208000, STLXP, instArgs{arg_Ws, arg_Wt, arg_Wt2, arg_Xns_mem}, nil}, 1622 // STLXP <Ws>, <Xt>, <Xt2>, [<Xn|SP>{, #0}] 1623 {0xffe08000, 0xc8208000, STLXP, instArgs{arg_Ws, arg_Xt, arg_Xt2, arg_Xns_mem}, nil}, 1624 // STLXR <Ws>, <Wt>, [<Xn|SP>{, #0}] 1625 {0xffe08000, 0x88008000, STLXR, instArgs{arg_Ws, arg_Wt, arg_Xns_mem}, nil}, 1626 // STLXR <Ws>, <Xt>, [<Xn|SP>{, #0}] 1627 {0xffe08000, 0xc8008000, STLXR, instArgs{arg_Ws, arg_Xt, arg_Xns_mem}, nil}, 1628 // STLXRB <Ws>, <Wt>, [<Xn|SP>{, #0}] 1629 {0xffe08000, 0x08008000, STLXRB, instArgs{arg_Ws, arg_Wt, arg_Xns_mem}, nil}, 1630 // STLXRH <Ws>, <Wt>, [<Xn|SP>{, #0}] 1631 {0xffe08000, 0x48008000, STLXRH, instArgs{arg_Ws, arg_Wt, arg_Xns_mem}, nil}, 1632 // STNP <Wt>, <Wt2>, [<Xn|SP>{, #<imm>}] 1633 {0xffc00000, 0x28000000, STNP, instArgs{arg_Wt, arg_Wt2, arg_Xns_mem_optional_imm7_4_signed}, nil}, 1634 // STNP <Xt>, <Xt2>, [<Xn|SP>{, #<imm_1>}] 1635 {0xffc00000, 0xa8000000, STNP, instArgs{arg_Xt, arg_Xt2, arg_Xns_mem_optional_imm7_8_signed}, nil}, 1636 // STP <Wt>, <Wt2>, [<Xn|SP>], #<imm_1> 1637 {0xffc00000, 0x28800000, STP, instArgs{arg_Wt, arg_Wt2, arg_Xns_mem_post_imm7_4_signed}, nil}, 1638 // STP <Xt>, <Xt2>, [<Xn|SP>], #<imm_3> 1639 {0xffc00000, 0xa8800000, STP, instArgs{arg_Xt, arg_Xt2, arg_Xns_mem_post_imm7_8_signed}, nil}, 1640 // STP <Wt>, <Wt2>, [<Xn|SP>{, #<imm_1>}]! 1641 {0xffc00000, 0x29800000, STP, instArgs{arg_Wt, arg_Wt2, arg_Xns_mem_wb_imm7_4_signed}, nil}, 1642 // STP <Xt>, <Xt2>, [<Xn|SP>{, #<imm_3>}]! 1643 {0xffc00000, 0xa9800000, STP, instArgs{arg_Xt, arg_Xt2, arg_Xns_mem_wb_imm7_8_signed}, nil}, 1644 // STP <Wt>, <Wt2>, [<Xn|SP>{, #<imm>}] 1645 {0xffc00000, 0x29000000, STP, instArgs{arg_Wt, arg_Wt2, arg_Xns_mem_optional_imm7_4_signed}, nil}, 1646 // STP <Xt>, <Xt2>, [<Xn|SP>{, #<imm_2>}] 1647 {0xffc00000, 0xa9000000, STP, instArgs{arg_Xt, arg_Xt2, arg_Xns_mem_optional_imm7_8_signed}, nil}, 1648 // STR <Wt>, [<Xn|SP>], #<simm> 1649 {0xffe00c00, 0xb8000400, STR, instArgs{arg_Wt, arg_Xns_mem_post_imm9_1_signed}, nil}, 1650 // STR <Xt>, [<Xn|SP>], #<simm> 1651 {0xffe00c00, 0xf8000400, STR, instArgs{arg_Xt, arg_Xns_mem_post_imm9_1_signed}, nil}, 1652 // STR <Wt>, [<Xn|SP>{, #<simm>}]! 1653 {0xffe00c00, 0xb8000c00, STR, instArgs{arg_Wt, arg_Xns_mem_wb_imm9_1_signed}, nil}, 1654 // STR <Xt>, [<Xn|SP>{, #<simm>}]! 1655 {0xffe00c00, 0xf8000c00, STR, instArgs{arg_Xt, arg_Xns_mem_wb_imm9_1_signed}, nil}, 1656 // STR <Wt>, [<Xn|SP>{, #<pimm>}] 1657 {0xffc00000, 0xb9000000, STR, instArgs{arg_Wt, arg_Xns_mem_optional_imm12_4_unsigned}, nil}, 1658 // STR <Xt>, [<Xn|SP>{, #<pimm_1>}] 1659 {0xffc00000, 0xf9000000, STR, instArgs{arg_Xt, arg_Xns_mem_optional_imm12_8_unsigned}, nil}, 1660 // STR <Wt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}] 1661 {0xffe00c00, 0xb8200800, STR, instArgs{arg_Wt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__2_1}, nil}, 1662 // STR <Xt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}] 1663 {0xffe00c00, 0xf8200800, STR, instArgs{arg_Xt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__3_1}, nil}, 1664 // STRB <Wt>, [<Xn|SP>], #<simm> 1665 {0xffe00c00, 0x38000400, STRB, instArgs{arg_Wt, arg_Xns_mem_post_imm9_1_signed}, nil}, 1666 // STRB <Wt>, [<Xn|SP>{, #<simm>}]! 1667 {0xffe00c00, 0x38000c00, STRB, instArgs{arg_Wt, arg_Xns_mem_wb_imm9_1_signed}, nil}, 1668 // STRB <Wt>, [<Xn|SP>{, #<pimm>}] 1669 {0xffc00000, 0x39000000, STRB, instArgs{arg_Wt, arg_Xns_mem_optional_imm12_1_unsigned}, nil}, 1670 // STRB <Wt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}] 1671 {0xffe00c00, 0x38200800, STRB, instArgs{arg_Wt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__absent_0__0_1}, nil}, 1672 // STRH <Wt>, [<Xn|SP>], #<simm> 1673 {0xffe00c00, 0x78000400, STRH, instArgs{arg_Wt, arg_Xns_mem_post_imm9_1_signed}, nil}, 1674 // STRH <Wt>, [<Xn|SP>{, #<simm>}]! 1675 {0xffe00c00, 0x78000c00, STRH, instArgs{arg_Wt, arg_Xns_mem_wb_imm9_1_signed}, nil}, 1676 // STRH <Wt>, [<Xn|SP>{, #<pimm>}] 1677 {0xffc00000, 0x79000000, STRH, instArgs{arg_Wt, arg_Xns_mem_optional_imm12_2_unsigned}, nil}, 1678 // STRH <Wt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}] 1679 {0xffe00c00, 0x78200800, STRH, instArgs{arg_Wt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__1_1}, nil}, 1680 // STTR <Wt>, [<Xn|SP>{, #<simm>}] 1681 {0xffe00c00, 0xb8000800, STTR, instArgs{arg_Wt, arg_Xns_mem_optional_imm9_1_signed}, nil}, 1682 // STTR <Xt>, [<Xn|SP>{, #<simm>}] 1683 {0xffe00c00, 0xf8000800, STTR, instArgs{arg_Xt, arg_Xns_mem_optional_imm9_1_signed}, nil}, 1684 // STTRB <Wt>, [<Xn|SP>{, #<simm>}] 1685 {0xffe00c00, 0x38000800, STTRB, instArgs{arg_Wt, arg_Xns_mem_optional_imm9_1_signed}, nil}, 1686 // STTRH <Wt>, [<Xn|SP>{, #<simm>}] 1687 {0xffe00c00, 0x78000800, STTRH, instArgs{arg_Wt, arg_Xns_mem_optional_imm9_1_signed}, nil}, 1688 // STUR <Wt>, [<Xn|SP>{, #<simm>}] 1689 {0xffe00c00, 0xb8000000, STUR, instArgs{arg_Wt, arg_Xns_mem_optional_imm9_1_signed}, nil}, 1690 // STUR <Xt>, [<Xn|SP>{, #<simm>}] 1691 {0xffe00c00, 0xf8000000, STUR, instArgs{arg_Xt, arg_Xns_mem_optional_imm9_1_signed}, nil}, 1692 // STURB <Wt>, [<Xn|SP>{, #<simm>}] 1693 {0xffe00c00, 0x38000000, STURB, instArgs{arg_Wt, arg_Xns_mem_optional_imm9_1_signed}, nil}, 1694 // STURH <Wt>, [<Xn|SP>{, #<simm>}] 1695 {0xffe00c00, 0x78000000, STURH, instArgs{arg_Wt, arg_Xns_mem_optional_imm9_1_signed}, nil}, 1696 // STXP <Ws>, <Wt>, <Wt2>, [<Xn|SP>{, #0}] 1697 {0xffe08000, 0x88200000, STXP, instArgs{arg_Ws, arg_Wt, arg_Wt2, arg_Xns_mem}, nil}, 1698 // STXP <Ws>, <Xt>, <Xt2>, [<Xn|SP>{, #0}] 1699 {0xffe08000, 0xc8200000, STXP, instArgs{arg_Ws, arg_Xt, arg_Xt2, arg_Xns_mem}, nil}, 1700 // STXR <Ws>, <Wt>, [<Xn|SP>{, #0}] 1701 {0xffe08000, 0x88000000, STXR, instArgs{arg_Ws, arg_Wt, arg_Xns_mem}, nil}, 1702 // STXR <Ws>, <Xt>, [<Xn|SP>{, #0}] 1703 {0xffe08000, 0xc8000000, STXR, instArgs{arg_Ws, arg_Xt, arg_Xns_mem}, nil}, 1704 // STXRB <Ws>, <Wt>, [<Xn|SP>{, #0}] 1705 {0xffe08000, 0x08000000, STXRB, instArgs{arg_Ws, arg_Wt, arg_Xns_mem}, nil}, 1706 // STXRH <Ws>, <Wt>, [<Xn|SP>{, #0}] 1707 {0xffe08000, 0x48000000, STXRH, instArgs{arg_Ws, arg_Wt, arg_Xns_mem}, nil}, 1708 // SUB <Wd|WSP>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}} 1709 {0xffe00000, 0x4b200000, SUB, instArgs{arg_Wds, arg_Wns, arg_Wm_extend__UXTB_0__UXTH_1__LSL_UXTW_2__UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4}, nil}, 1710 // SUB <Xd|SP>, <Xn|SP>, <R><m>{, <extend_1> {#<amount>}} 1711 {0xffe00000, 0xcb200000, SUB, instArgs{arg_Xds, arg_Xns, arg_Rm_extend__UXTB_0__UXTH_1__UXTW_2__LSL_UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4}, nil}, 1712 // SUB <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>} 1713 {0xff000000, 0x51000000, SUB, instArgs{arg_Wds, arg_Wns, arg_IAddSub}, nil}, 1714 // SUB <Xd|SP>, <Xn|SP>, #<imm>{, <shift>} 1715 {0xff000000, 0xd1000000, SUB, instArgs{arg_Xds, arg_Xns, arg_IAddSub}, nil}, 1716 // SVC #<imm> 1717 {0xffe0001f, 0xd4000001, SVC, instArgs{arg_immediate_0_65535_imm16}, nil}, 1718 // SYSL <Xt>, #<op1>, <Cn>, <Cm>, #<op2> 1719 {0xfff80000, 0xd5280000, SYSL, instArgs{arg_Xt, arg_immediate_0_7_op1, arg_Cn, arg_Cm, arg_immediate_0_7_op2}, nil}, 1720 // TBNZ <R><t>, #<imm>, <label> 1721 {0x7f000000, 0x37000000, TBNZ, instArgs{arg_Rt_31_1__W_0__X_1, arg_immediate_0_63_b5_b40, arg_slabel_imm14_2}, nil}, 1722 // TBZ <R><t>, #<imm>, <label> 1723 {0x7f000000, 0x36000000, TBZ, instArgs{arg_Rt_31_1__W_0__X_1, arg_immediate_0_63_b5_b40, arg_slabel_imm14_2}, nil}, 1724 // UDIV <Wd>, <Wn>, <Wm> 1725 {0xffe0fc00, 0x1ac00800, UDIV, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil}, 1726 // UDIV <Xd>, <Xn>, <Xm> 1727 {0xffe0fc00, 0x9ac00800, UDIV, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil}, 1728 // UMULL <Xd>, <Wn>, <Wm> 1729 {0xffe0fc00, 0x9ba07c00, UMULL, instArgs{arg_Xd, arg_Wn, arg_Wm}, nil}, 1730 // UMADDL <Xd>, <Wn>, <Wm>, <Xa> 1731 {0xffe08000, 0x9ba00000, UMADDL, instArgs{arg_Xd, arg_Wn, arg_Wm, arg_Xa}, nil}, 1732 // UMNEGL <Xd>, <Wn>, <Wm> 1733 {0xffe0fc00, 0x9ba0fc00, UMNEGL, instArgs{arg_Xd, arg_Wn, arg_Wm}, nil}, 1734 // UMSUBL <Xd>, <Wn>, <Wm>, <Xa> 1735 {0xffe08000, 0x9ba08000, UMSUBL, instArgs{arg_Xd, arg_Wn, arg_Wm, arg_Xa}, nil}, 1736 // UMULH <Xd>, <Xn>, <Xm> 1737 {0xffe08000, 0x9bc00000, UMULH, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil}, 1738 // ABS <V><d>, <V><n> 1739 {0xff3ffc00, 0x5e20b800, ABS, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3}, nil}, 1740 // ABS <Vd>.<t>, <Vn>.<t> 1741 {0xbf3ffc00, 0x0e20b800, ABS, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil}, 1742 // ADD <V><d>, <V><n>, <V><m> 1743 {0xff20fc00, 0x5e208400, ADD, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3, arg_Vm_22_2__D_3}, nil}, 1744 // ADD <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 1745 {0xbf20fc00, 0x0e208400, ADD, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil}, 1746 // ADDHN <Vd>.<tb>, <Vn>.<ta>, <Vm>.<ta> 1747 {0xff20fc00, 0x0e204000, ADDHN, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size___8H_0__4S_1__2D_2, arg_Vm_arrangement_size___8H_0__4S_1__2D_2}, nil}, 1748 // ADDHN2 <Vd>.<tb>, <Vn>.<ta>, <Vm>.<ta> 1749 {0xff20fc00, 0x4e204000, ADDHN2, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size___8H_0__4S_1__2D_2, arg_Vm_arrangement_size___8H_0__4S_1__2D_2}, nil}, 1750 // ADDP <V><d>, <Vn>.<t> 1751 {0xff3ffc00, 0x5e31b800, ADDP, instArgs{arg_Vd_22_2__D_3, arg_Vn_arrangement_size___2D_3}, nil}, 1752 // ADDP <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 1753 {0xbf20fc00, 0x0e20bc00, ADDP, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil}, 1754 // ADDV <V><d>, <Vn>.<t> 1755 {0xbf3ffc00, 0x0e31b800, ADDV, instArgs{arg_Vd_22_2__B_0__H_1__S_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__4S_21}, nil}, 1756 // AESD <Vd>.16B, <Vn>.16B 1757 {0xfffffc00, 0x4e285800, AESD, instArgs{arg_Vd_arrangement_16B, arg_Vn_arrangement_16B}, nil}, 1758 // AESE <Vd>.16B, <Vn>.16B 1759 {0xfffffc00, 0x4e284800, AESE, instArgs{arg_Vd_arrangement_16B, arg_Vn_arrangement_16B}, nil}, 1760 // AESIMC <Vd>.16B, <Vn>.16B 1761 {0xfffffc00, 0x4e287800, AESIMC, instArgs{arg_Vd_arrangement_16B, arg_Vn_arrangement_16B}, nil}, 1762 // AESMC <Vd>.16B, <Vn>.16B 1763 {0xfffffc00, 0x4e286800, AESMC, instArgs{arg_Vd_arrangement_16B, arg_Vn_arrangement_16B}, nil}, 1764 // AND <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 1765 {0xbfe0fc00, 0x0e201c00, AND, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_arrangement_Q___8B_0__16B_1, arg_Vm_arrangement_Q___8B_0__16B_1}, nil}, 1766 // BIC <Vd>.<t>, #<imm8>{, LSL #<amount>} 1767 {0xbff8dc00, 0x2f009400, BIC, instArgs{arg_Vd_arrangement_Q___4H_0__8H_1, arg_immediate_OptLSL__a_b_c_d_e_f_g_h_cmode__0_0__8_1}, nil}, 1768 // BIC <Vd>.<t_1>, #<imm8>{, LSL #<amount>} 1769 {0xbff89c00, 0x2f001400, BIC, instArgs{arg_Vd_arrangement_Q___2S_0__4S_1, arg_immediate_OptLSL__a_b_c_d_e_f_g_h_cmode__0_0__8_1__16_2__24_3}, nil}, 1770 // BIC <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 1771 {0xbfe0fc00, 0x0e601c00, BIC, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_arrangement_Q___8B_0__16B_1, arg_Vm_arrangement_Q___8B_0__16B_1}, nil}, 1772 // BIF <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 1773 {0xbfe0fc00, 0x2ee01c00, BIF, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_arrangement_Q___8B_0__16B_1, arg_Vm_arrangement_Q___8B_0__16B_1}, nil}, 1774 // BIT <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 1775 {0xbfe0fc00, 0x2ea01c00, BIT, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_arrangement_Q___8B_0__16B_1, arg_Vm_arrangement_Q___8B_0__16B_1}, nil}, 1776 // BSL <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 1777 {0xbfe0fc00, 0x2e601c00, BSL, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_arrangement_Q___8B_0__16B_1, arg_Vm_arrangement_Q___8B_0__16B_1}, nil}, 1778 // CLS <Vd>.<t>, <Vn>.<t> 1779 {0xbf3ffc00, 0x0e204800, CLS, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 1780 // CLZ <Vd>.<t>, <Vn>.<t> 1781 {0xbf3ffc00, 0x2e204800, CLZ, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 1782 // CMEQ <V><d>, <V><n>, <V><m> 1783 {0xff20fc00, 0x7e208c00, CMEQ, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3, arg_Vm_22_2__D_3}, nil}, 1784 // CMEQ <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 1785 {0xbf20fc00, 0x2e208c00, CMEQ, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil}, 1786 // CMEQ <V><d>, <V><n>, #0 1787 {0xff3ffc00, 0x5e209800, CMEQ, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3, arg_immediate_zero}, nil}, 1788 // CMEQ <Vd>.<t>, <Vn>.<t>, #0 1789 {0xbf3ffc00, 0x0e209800, CMEQ, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_immediate_zero}, nil}, 1790 // CMGE <V><d>, <V><n>, <V><m> 1791 {0xff20fc00, 0x5e203c00, CMGE, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3, arg_Vm_22_2__D_3}, nil}, 1792 // CMGE <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 1793 {0xbf20fc00, 0x0e203c00, CMGE, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil}, 1794 // CMGE <V><d>, <V><n>, #0 1795 {0xff3ffc00, 0x7e208800, CMGE, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3, arg_immediate_zero}, nil}, 1796 // CMGE <Vd>.<t>, <Vn>.<t>, #0 1797 {0xbf3ffc00, 0x2e208800, CMGE, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_immediate_zero}, nil}, 1798 // CMGT <V><d>, <V><n>, <V><m> 1799 {0xff20fc00, 0x5e203400, CMGT, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3, arg_Vm_22_2__D_3}, nil}, 1800 // CMGT <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 1801 {0xbf20fc00, 0x0e203400, CMGT, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil}, 1802 // CMGT <V><d>, <V><n>, #0 1803 {0xff3ffc00, 0x5e208800, CMGT, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3, arg_immediate_zero}, nil}, 1804 // CMGT <Vd>.<t>, <Vn>.<t>, #0 1805 {0xbf3ffc00, 0x0e208800, CMGT, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_immediate_zero}, nil}, 1806 // CMHI <V><d>, <V><n>, <V><m> 1807 {0xff20fc00, 0x7e203400, CMHI, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3, arg_Vm_22_2__D_3}, nil}, 1808 // CMHI <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 1809 {0xbf20fc00, 0x2e203400, CMHI, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil}, 1810 // CMHS <V><d>, <V><n>, <V><m> 1811 {0xff20fc00, 0x7e203c00, CMHS, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3, arg_Vm_22_2__D_3}, nil}, 1812 // CMHS <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 1813 {0xbf20fc00, 0x2e203c00, CMHS, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil}, 1814 // CMLE <V><d>, <V><n>, #0 1815 {0xff3ffc00, 0x7e209800, CMLE, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3, arg_immediate_zero}, nil}, 1816 // CMLE <Vd>.<t>, <Vn>.<t>, #0 1817 {0xbf3ffc00, 0x2e209800, CMLE, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_immediate_zero}, nil}, 1818 // CMLT <V><d>, <V><n>, #0 1819 {0xff3ffc00, 0x5e20a800, CMLT, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3, arg_immediate_zero}, nil}, 1820 // CMLT <Vd>.<t>, <Vn>.<t>, #0 1821 {0xbf3ffc00, 0x0e20a800, CMLT, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_immediate_zero}, nil}, 1822 // CMTST <V><d>, <V><n>, <V><m> 1823 {0xff20fc00, 0x5e208c00, CMTST, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3, arg_Vm_22_2__D_3}, nil}, 1824 // CMTST <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 1825 {0xbf20fc00, 0x0e208c00, CMTST, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil}, 1826 // CNT <Vd>.<t>, <Vn>.<t> 1827 {0xbf3ffc00, 0x0e205800, CNT, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01, arg_Vn_arrangement_size_Q___8B_00__16B_01}, nil}, 1828 // MOV <V><d>, <Vn>.<t_1>[<index>] 1829 {0xffe0fc00, 0x5e000400, MOV, instArgs{arg_Vd_16_5__B_1__H_2__S_4__D_8, arg_Vn_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4__imm5lt4gt_8_1}, nil}, 1830 // DUP <V><d>, <Vn>.<t_1>[<index>] 1831 {0xffe0fc00, 0x5e000400, DUP, instArgs{arg_Vd_16_5__B_1__H_2__S_4__D_8, arg_Vn_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4__imm5lt4gt_8_1}, nil}, 1832 // DUP <Vd>.<t>, <Vn>.<ts>[<index>] 1833 {0xbfe0fc00, 0x0e000400, DUP, instArgs{arg_Vd_arrangement_imm5_Q___8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_Vn_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4__imm5lt4gt_8_1}, nil}, 1834 // DUP <Vd>.<t>, <R><n> 1835 {0xbfe0fc00, 0x0e000c00, DUP, instArgs{arg_Vd_arrangement_imm5_Q___8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_Rn_16_5__W_1__W_2__W_4__X_8}, nil}, 1836 // EOR <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 1837 {0xbfe0fc00, 0x2e201c00, EOR, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_arrangement_Q___8B_0__16B_1, arg_Vm_arrangement_Q___8B_0__16B_1}, nil}, 1838 // EXT <Vd>.<t>, <Vn>.<t>, <Vm>.<t>, #<index> 1839 {0xbfe08400, 0x2e000000, EXT, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_arrangement_Q___8B_0__16B_1, arg_Vm_arrangement_Q___8B_0__16B_1, arg_immediate_index_Q_imm4__imm4lt20gt_00__imm4_10}, nil}, 1840 // FABD <V><d>, <V><n>, <V><m> 1841 {0xffa0fc00, 0x7ea0d400, FABD, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1, arg_Vm_22_1__S_0__D_1}, nil}, 1842 // FABD <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 1843 {0xbfa0fc00, 0x2ea0d400, FABD, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 1844 // FABS <Sd>, <Sn> 1845 {0xfffffc00, 0x1e20c000, FABS, instArgs{arg_Sd, arg_Sn}, nil}, 1846 // FABS <Dd>, <Dn> 1847 {0xfffffc00, 0x1e60c000, FABS, instArgs{arg_Dd, arg_Dn}, nil}, 1848 // FABS <Vd>.<t>, <Vn>.<t> 1849 {0xbfbffc00, 0x0ea0f800, FABS, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 1850 // FACGE <V><d>, <V><n>, <V><m> 1851 {0xffa0fc00, 0x7e20ec00, FACGE, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1, arg_Vm_22_1__S_0__D_1}, nil}, 1852 // FACGE <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 1853 {0xbfa0fc00, 0x2e20ec00, FACGE, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 1854 // FACGT <V><d>, <V><n>, <V><m> 1855 {0xffa0fc00, 0x7ea0ec00, FACGT, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1, arg_Vm_22_1__S_0__D_1}, nil}, 1856 // FACGT <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 1857 {0xbfa0fc00, 0x2ea0ec00, FACGT, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 1858 // FADD <Sd>, <Sn>, <Sm> 1859 {0xffe0fc00, 0x1e202800, FADD, instArgs{arg_Sd, arg_Sn, arg_Sm}, nil}, 1860 // FADD <Dd>, <Dn>, <Dm> 1861 {0xffe0fc00, 0x1e602800, FADD, instArgs{arg_Dd, arg_Dn, arg_Dm}, nil}, 1862 // FADD <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 1863 {0xbfa0fc00, 0x0e20d400, FADD, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 1864 // FADDP <V><d>, <Vn>.<t> 1865 {0xffbffc00, 0x7e30d800, FADDP, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_arrangement_sz___2S_0__2D_1}, nil}, 1866 // FADDP <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 1867 {0xbfa0fc00, 0x2e20d400, FADDP, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 1868 // FCCMP <Sn>, <Sm>, #<nzcv>, <cond> 1869 {0xffe00c10, 0x1e200400, FCCMP, instArgs{arg_Sn, arg_Sm, arg_immediate_0_15_nzcv, arg_cond_AllowALNV_Normal}, nil}, 1870 // FCCMP <Dn>, <Dm>, #<nzcv>, <cond> 1871 {0xffe00c10, 0x1e600400, FCCMP, instArgs{arg_Dn, arg_Dm, arg_immediate_0_15_nzcv, arg_cond_AllowALNV_Normal}, nil}, 1872 // FCCMPE <Sn>, <Sm>, #<nzcv>, <cond> 1873 {0xffe00c10, 0x1e200410, FCCMPE, instArgs{arg_Sn, arg_Sm, arg_immediate_0_15_nzcv, arg_cond_AllowALNV_Normal}, nil}, 1874 // FCCMPE <Dn>, <Dm>, #<nzcv>, <cond> 1875 {0xffe00c10, 0x1e600410, FCCMPE, instArgs{arg_Dn, arg_Dm, arg_immediate_0_15_nzcv, arg_cond_AllowALNV_Normal}, nil}, 1876 // FCMEQ <V><d>, <V><n>, <V><m> 1877 {0xffa0fc00, 0x5e20e400, FCMEQ, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1, arg_Vm_22_1__S_0__D_1}, nil}, 1878 // FCMEQ <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 1879 {0xbfa0fc00, 0x0e20e400, FCMEQ, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 1880 // FCMEQ <V><d>, <V><n>, #0.0 1881 {0xffbffc00, 0x5ea0d800, FCMEQ, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1, arg_immediate_floatzero}, nil}, 1882 // FCMEQ <Vd>.<t>, <Vn>.<t>, #0.0 1883 {0xbfbffc00, 0x0ea0d800, FCMEQ, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_immediate_floatzero}, nil}, 1884 // FCMGE <V><d>, <V><n>, <V><m> 1885 {0xffa0fc00, 0x7e20e400, FCMGE, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1, arg_Vm_22_1__S_0__D_1}, nil}, 1886 // FCMGE <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 1887 {0xbfa0fc00, 0x2e20e400, FCMGE, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 1888 // FCMGE <V><d>, <V><n>, #0.0 1889 {0xffbffc00, 0x7ea0c800, FCMGE, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1, arg_immediate_floatzero}, nil}, 1890 // FCMGE <Vd>.<t>, <Vn>.<t>, #0.0 1891 {0xbfbffc00, 0x2ea0c800, FCMGE, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_immediate_floatzero}, nil}, 1892 // FCMGT <V><d>, <V><n>, <V><m> 1893 {0xffa0fc00, 0x7ea0e400, FCMGT, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1, arg_Vm_22_1__S_0__D_1}, nil}, 1894 // FCMGT <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 1895 {0xbfa0fc00, 0x2ea0e400, FCMGT, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 1896 // FCMGT <V><d>, <V><n>, #0.0 1897 {0xffbffc00, 0x5ea0c800, FCMGT, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1, arg_immediate_floatzero}, nil}, 1898 // FCMGT <Vd>.<t>, <Vn>.<t>, #0.0 1899 {0xbfbffc00, 0x0ea0c800, FCMGT, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_immediate_floatzero}, nil}, 1900 // FCMLE <V><d>, <V><n>, #0.0 1901 {0xffbffc00, 0x7ea0d800, FCMLE, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1, arg_immediate_floatzero}, nil}, 1902 // FCMLE <Vd>.<t>, <Vn>.<t>, #0.0 1903 {0xbfbffc00, 0x2ea0d800, FCMLE, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_immediate_floatzero}, nil}, 1904 // FCMLT <V><d>, <V><n>, #0.0 1905 {0xffbffc00, 0x5ea0e800, FCMLT, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1, arg_immediate_floatzero}, nil}, 1906 // FCMLT <Vd>.<t>, <Vn>.<t>, #0.0 1907 {0xbfbffc00, 0x0ea0e800, FCMLT, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_immediate_floatzero}, nil}, 1908 // FCMP <Sn>, <Sm> 1909 {0xffe0fc1f, 0x1e202000, FCMP, instArgs{arg_Sn, arg_Sm}, nil}, 1910 // FCMP <Sn>, #0.0 1911 {0xffe0fc1f, 0x1e202008, FCMP, instArgs{arg_Sn, arg_immediate_floatzero}, nil}, 1912 // FCMP <Dn>, <Dm> 1913 {0xffe0fc1f, 0x1e602000, FCMP, instArgs{arg_Dn, arg_Dm}, nil}, 1914 // FCMP <Dn>, #0.0 1915 {0xffe0fc1f, 0x1e602008, FCMP, instArgs{arg_Dn, arg_immediate_floatzero}, nil}, 1916 // FCMPE <Sn>, <Sm> 1917 {0xffe0fc1f, 0x1e202010, FCMPE, instArgs{arg_Sn, arg_Sm}, nil}, 1918 // FCMPE <Sn>, #0.0 1919 {0xffe0fc1f, 0x1e202018, FCMPE, instArgs{arg_Sn, arg_immediate_floatzero}, nil}, 1920 // FCMPE <Dn>, <Dm> 1921 {0xffe0fc1f, 0x1e602010, FCMPE, instArgs{arg_Dn, arg_Dm}, nil}, 1922 // FCMPE <Dn>, #0.0 1923 {0xffe0fc1f, 0x1e602018, FCMPE, instArgs{arg_Dn, arg_immediate_floatzero}, nil}, 1924 // FCSEL <Sd>, <Sn>, <Sm>, <cond> 1925 {0xffe00c00, 0x1e200c00, FCSEL, instArgs{arg_Sd, arg_Sn, arg_Sm, arg_cond_AllowALNV_Normal}, nil}, 1926 // FCSEL <Dd>, <Dn>, <Dm>, <cond> 1927 {0xffe00c00, 0x1e600c00, FCSEL, instArgs{arg_Dd, arg_Dn, arg_Dm, arg_cond_AllowALNV_Normal}, nil}, 1928 // FCVT <Sd>, <Hn> 1929 {0xfffffc00, 0x1ee24000, FCVT, instArgs{arg_Sd, arg_Hn}, nil}, 1930 // FCVT <Dd>, <Hn> 1931 {0xfffffc00, 0x1ee2c000, FCVT, instArgs{arg_Dd, arg_Hn}, nil}, 1932 // FCVT <Hd>, <Sn> 1933 {0xfffffc00, 0x1e23c000, FCVT, instArgs{arg_Hd, arg_Sn}, nil}, 1934 // FCVT <Dd>, <Sn> 1935 {0xfffffc00, 0x1e22c000, FCVT, instArgs{arg_Dd, arg_Sn}, nil}, 1936 // FCVT <Hd>, <Dn> 1937 {0xfffffc00, 0x1e63c000, FCVT, instArgs{arg_Hd, arg_Dn}, nil}, 1938 // FCVT <Sd>, <Dn> 1939 {0xfffffc00, 0x1e624000, FCVT, instArgs{arg_Sd, arg_Dn}, nil}, 1940 // FCVTAS <Wd>, <Sn> 1941 {0xfffffc00, 0x1e240000, FCVTAS, instArgs{arg_Wd, arg_Sn}, nil}, 1942 // FCVTAS <Xd>, <Sn> 1943 {0xfffffc00, 0x9e240000, FCVTAS, instArgs{arg_Xd, arg_Sn}, nil}, 1944 // FCVTAS <Wd>, <Dn> 1945 {0xfffffc00, 0x1e640000, FCVTAS, instArgs{arg_Wd, arg_Dn}, nil}, 1946 // FCVTAS <Xd>, <Dn> 1947 {0xfffffc00, 0x9e640000, FCVTAS, instArgs{arg_Xd, arg_Dn}, nil}, 1948 // FCVTAS <V><d>, <V><n> 1949 {0xffbffc00, 0x5e21c800, FCVTAS, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1}, nil}, 1950 // FCVTAS <Vd>.<t>, <Vn>.<t> 1951 {0xbfbffc00, 0x0e21c800, FCVTAS, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 1952 // FCVTAU <Wd>, <Sn> 1953 {0xfffffc00, 0x1e250000, FCVTAU, instArgs{arg_Wd, arg_Sn}, nil}, 1954 // FCVTAU <Xd>, <Sn> 1955 {0xfffffc00, 0x9e250000, FCVTAU, instArgs{arg_Xd, arg_Sn}, nil}, 1956 // FCVTAU <Wd>, <Dn> 1957 {0xfffffc00, 0x1e650000, FCVTAU, instArgs{arg_Wd, arg_Dn}, nil}, 1958 // FCVTAU <Xd>, <Dn> 1959 {0xfffffc00, 0x9e650000, FCVTAU, instArgs{arg_Xd, arg_Dn}, nil}, 1960 // FCVTAU <V><d>, <V><n> 1961 {0xffbffc00, 0x7e21c800, FCVTAU, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1}, nil}, 1962 // FCVTAU <Vd>.<t>, <Vn>.<t> 1963 {0xbfbffc00, 0x2e21c800, FCVTAU, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 1964 // FCVTL <Vd>.<ta>, <Vn>.<tb> 1965 {0xffbffc00, 0x0e217800, FCVTL, instArgs{arg_Vd_arrangement_sz___4S_0__2D_1, arg_Vn_arrangement_sz_Q___4H_00__8H_01__2S_10__4S_11}, nil}, 1966 // FCVTL2 <Vd>.<ta>, <Vn>.<tb> 1967 {0xffbffc00, 0x4e217800, FCVTL2, instArgs{arg_Vd_arrangement_sz___4S_0__2D_1, arg_Vn_arrangement_sz_Q___4H_00__8H_01__2S_10__4S_11}, nil}, 1968 // FCVTMS <Wd>, <Sn> 1969 {0xfffffc00, 0x1e300000, FCVTMS, instArgs{arg_Wd, arg_Sn}, nil}, 1970 // FCVTMS <Xd>, <Sn> 1971 {0xfffffc00, 0x9e300000, FCVTMS, instArgs{arg_Xd, arg_Sn}, nil}, 1972 // FCVTMS <Wd>, <Dn> 1973 {0xfffffc00, 0x1e700000, FCVTMS, instArgs{arg_Wd, arg_Dn}, nil}, 1974 // FCVTMS <Xd>, <Dn> 1975 {0xfffffc00, 0x9e700000, FCVTMS, instArgs{arg_Xd, arg_Dn}, nil}, 1976 // FCVTMS <V><d>, <V><n> 1977 {0xffbffc00, 0x5e21b800, FCVTMS, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1}, nil}, 1978 // FCVTMS <Vd>.<t>, <Vn>.<t> 1979 {0xbfbffc00, 0x0e21b800, FCVTMS, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 1980 // FCVTMU <Wd>, <Sn> 1981 {0xfffffc00, 0x1e310000, FCVTMU, instArgs{arg_Wd, arg_Sn}, nil}, 1982 // FCVTMU <Xd>, <Sn> 1983 {0xfffffc00, 0x9e310000, FCVTMU, instArgs{arg_Xd, arg_Sn}, nil}, 1984 // FCVTMU <Wd>, <Dn> 1985 {0xfffffc00, 0x1e710000, FCVTMU, instArgs{arg_Wd, arg_Dn}, nil}, 1986 // FCVTMU <Xd>, <Dn> 1987 {0xfffffc00, 0x9e710000, FCVTMU, instArgs{arg_Xd, arg_Dn}, nil}, 1988 // FCVTMU <V><d>, <V><n> 1989 {0xffbffc00, 0x7e21b800, FCVTMU, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1}, nil}, 1990 // FCVTMU <Vd>.<t>, <Vn>.<t> 1991 {0xbfbffc00, 0x2e21b800, FCVTMU, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 1992 // FCVTN <Vd>.<tb>, <Vn>.<ta> 1993 {0xffbffc00, 0x0e216800, FCVTN, instArgs{arg_Vd_arrangement_sz_Q___4H_00__8H_01__2S_10__4S_11, arg_Vn_arrangement_sz___4S_0__2D_1}, nil}, 1994 // FCVTN2 <Vd>.<tb>, <Vn>.<ta> 1995 {0xffbffc00, 0x4e216800, FCVTN2, instArgs{arg_Vd_arrangement_sz_Q___4H_00__8H_01__2S_10__4S_11, arg_Vn_arrangement_sz___4S_0__2D_1}, nil}, 1996 // FCVTNS <Wd>, <Sn> 1997 {0xfffffc00, 0x1e200000, FCVTNS, instArgs{arg_Wd, arg_Sn}, nil}, 1998 // FCVTNS <Xd>, <Sn> 1999 {0xfffffc00, 0x9e200000, FCVTNS, instArgs{arg_Xd, arg_Sn}, nil}, 2000 // FCVTNS <Wd>, <Dn> 2001 {0xfffffc00, 0x1e600000, FCVTNS, instArgs{arg_Wd, arg_Dn}, nil}, 2002 // FCVTNS <Xd>, <Dn> 2003 {0xfffffc00, 0x9e600000, FCVTNS, instArgs{arg_Xd, arg_Dn}, nil}, 2004 // FCVTNS <V><d>, <V><n> 2005 {0xffbffc00, 0x5e21a800, FCVTNS, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1}, nil}, 2006 // FCVTNS <Vd>.<t>, <Vn>.<t> 2007 {0xbfbffc00, 0x0e21a800, FCVTNS, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 2008 // FCVTNU <Wd>, <Sn> 2009 {0xfffffc00, 0x1e210000, FCVTNU, instArgs{arg_Wd, arg_Sn}, nil}, 2010 // FCVTNU <Xd>, <Sn> 2011 {0xfffffc00, 0x9e210000, FCVTNU, instArgs{arg_Xd, arg_Sn}, nil}, 2012 // FCVTNU <Wd>, <Dn> 2013 {0xfffffc00, 0x1e610000, FCVTNU, instArgs{arg_Wd, arg_Dn}, nil}, 2014 // FCVTNU <Xd>, <Dn> 2015 {0xfffffc00, 0x9e610000, FCVTNU, instArgs{arg_Xd, arg_Dn}, nil}, 2016 // FCVTNU <V><d>, <V><n> 2017 {0xffbffc00, 0x7e21a800, FCVTNU, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1}, nil}, 2018 // FCVTNU <Vd>.<t>, <Vn>.<t> 2019 {0xbfbffc00, 0x2e21a800, FCVTNU, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 2020 // FCVTPS <Wd>, <Sn> 2021 {0xfffffc00, 0x1e280000, FCVTPS, instArgs{arg_Wd, arg_Sn}, nil}, 2022 // FCVTPS <Xd>, <Sn> 2023 {0xfffffc00, 0x9e280000, FCVTPS, instArgs{arg_Xd, arg_Sn}, nil}, 2024 // FCVTPS <Wd>, <Dn> 2025 {0xfffffc00, 0x1e680000, FCVTPS, instArgs{arg_Wd, arg_Dn}, nil}, 2026 // FCVTPS <Xd>, <Dn> 2027 {0xfffffc00, 0x9e680000, FCVTPS, instArgs{arg_Xd, arg_Dn}, nil}, 2028 // FCVTPS <V><d>, <V><n> 2029 {0xffbffc00, 0x5ea1a800, FCVTPS, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1}, nil}, 2030 // FCVTPS <Vd>.<t>, <Vn>.<t> 2031 {0xbfbffc00, 0x0ea1a800, FCVTPS, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 2032 // FCVTPU <Wd>, <Sn> 2033 {0xfffffc00, 0x1e290000, FCVTPU, instArgs{arg_Wd, arg_Sn}, nil}, 2034 // FCVTPU <Xd>, <Sn> 2035 {0xfffffc00, 0x9e290000, FCVTPU, instArgs{arg_Xd, arg_Sn}, nil}, 2036 // FCVTPU <Wd>, <Dn> 2037 {0xfffffc00, 0x1e690000, FCVTPU, instArgs{arg_Wd, arg_Dn}, nil}, 2038 // FCVTPU <Xd>, <Dn> 2039 {0xfffffc00, 0x9e690000, FCVTPU, instArgs{arg_Xd, arg_Dn}, nil}, 2040 // FCVTPU <V><d>, <V><n> 2041 {0xffbffc00, 0x7ea1a800, FCVTPU, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1}, nil}, 2042 // FCVTPU <Vd>.<t>, <Vn>.<t> 2043 {0xbfbffc00, 0x2ea1a800, FCVTPU, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 2044 // FCVTXN <V><d>, <V><n> 2045 {0xffbffc00, 0x7e216800, FCVTXN, instArgs{arg_Vd_22_1__S_1, arg_Vn_22_1__D_1}, nil}, 2046 // FCVTXN <Vd>.<tb>, <Vn>.<ta> 2047 {0xffbffc00, 0x2e216800, FCVTXN, instArgs{arg_Vd_arrangement_sz_Q___2S_10__4S_11, arg_Vn_arrangement_sz___2D_1}, nil}, 2048 // FCVTXN2 <Vd>.<tb>, <Vn>.<ta> 2049 {0xffbffc00, 0x6e216800, FCVTXN2, instArgs{arg_Vd_arrangement_sz_Q___2S_10__4S_11, arg_Vn_arrangement_sz___2D_1}, nil}, 2050 // FCVTZS <Wd>, <Sn>, #<fbits> 2051 {0xffff0000, 0x1e180000, FCVTZS, instArgs{arg_Wd, arg_Sn, arg_immediate_fbits_min_1_max_32_sub_64_scale}, nil}, 2052 // FCVTZS <Xd>, <Sn>, #<fbits> 2053 {0xffff0000, 0x9e180000, FCVTZS, instArgs{arg_Xd, arg_Sn, arg_immediate_fbits_min_1_max_64_sub_64_scale}, nil}, 2054 // FCVTZS <Wd>, <Dn>, #<fbits> 2055 {0xffff0000, 0x1e580000, FCVTZS, instArgs{arg_Wd, arg_Dn, arg_immediate_fbits_min_1_max_32_sub_64_scale}, nil}, 2056 // FCVTZS <Xd>, <Dn>, #<fbits> 2057 {0xffff0000, 0x9e580000, FCVTZS, instArgs{arg_Xd, arg_Dn, arg_immediate_fbits_min_1_max_64_sub_64_scale}, nil}, 2058 // FCVTZS <Wd>, <Sn> 2059 {0xfffffc00, 0x1e380000, FCVTZS, instArgs{arg_Wd, arg_Sn}, nil}, 2060 // FCVTZS <Xd>, <Sn> 2061 {0xfffffc00, 0x9e380000, FCVTZS, instArgs{arg_Xd, arg_Sn}, nil}, 2062 // FCVTZS <Wd>, <Dn> 2063 {0xfffffc00, 0x1e780000, FCVTZS, instArgs{arg_Wd, arg_Dn}, nil}, 2064 // FCVTZS <Xd>, <Dn> 2065 {0xfffffc00, 0x9e780000, FCVTZS, instArgs{arg_Xd, arg_Dn}, nil}, 2066 // FCVTZS <V><d>, <V><n>, #<fbits> 2067 {0xff80fc00, 0x5f00fc00, FCVTZS, instArgs{arg_Vd_19_4__S_4__D_8, arg_Vn_19_4__S_4__D_8, arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__64UIntimmhimmb_4__128UIntimmhimmb_8}, fcvtzs_asisdshf_c_cond}, 2068 // FCVTZS <Vd>.<t>, <Vn>.<t>, #<fbits> 2069 {0xbf80fc00, 0x0f00fc00, FCVTZS, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__2S_40__4S_41__2D_81, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__2S_40__4S_41__2D_81, arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__64UIntimmhimmb_4__128UIntimmhimmb_8}, fcvtzs_asimdshf_c_cond}, 2070 // FCVTZS <V><d>, <V><n> 2071 {0xffbffc00, 0x5ea1b800, FCVTZS, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1}, nil}, 2072 // FCVTZS <Vd>.<t>, <Vn>.<t> 2073 {0xbfbffc00, 0x0ea1b800, FCVTZS, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 2074 // FCVTZU <Wd>, <Sn>, #<fbits> 2075 {0xffff0000, 0x1e190000, FCVTZU, instArgs{arg_Wd, arg_Sn, arg_immediate_fbits_min_1_max_32_sub_64_scale}, nil}, 2076 // FCVTZU <Xd>, <Sn>, #<fbits> 2077 {0xffff0000, 0x9e190000, FCVTZU, instArgs{arg_Xd, arg_Sn, arg_immediate_fbits_min_1_max_64_sub_64_scale}, nil}, 2078 // FCVTZU <Wd>, <Dn>, #<fbits> 2079 {0xffff0000, 0x1e590000, FCVTZU, instArgs{arg_Wd, arg_Dn, arg_immediate_fbits_min_1_max_32_sub_64_scale}, nil}, 2080 // FCVTZU <Xd>, <Dn>, #<fbits> 2081 {0xffff0000, 0x9e590000, FCVTZU, instArgs{arg_Xd, arg_Dn, arg_immediate_fbits_min_1_max_64_sub_64_scale}, nil}, 2082 // FCVTZU <Wd>, <Sn> 2083 {0xfffffc00, 0x1e390000, FCVTZU, instArgs{arg_Wd, arg_Sn}, nil}, 2084 // FCVTZU <Xd>, <Sn> 2085 {0xfffffc00, 0x9e390000, FCVTZU, instArgs{arg_Xd, arg_Sn}, nil}, 2086 // FCVTZU <Wd>, <Dn> 2087 {0xfffffc00, 0x1e790000, FCVTZU, instArgs{arg_Wd, arg_Dn}, nil}, 2088 // FCVTZU <Xd>, <Dn> 2089 {0xfffffc00, 0x9e790000, FCVTZU, instArgs{arg_Xd, arg_Dn}, nil}, 2090 // FCVTZU <V><d>, <V><n>, #<fbits> 2091 {0xff80fc00, 0x7f00fc00, FCVTZU, instArgs{arg_Vd_19_4__S_4__D_8, arg_Vn_19_4__S_4__D_8, arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__64UIntimmhimmb_4__128UIntimmhimmb_8}, fcvtzu_asisdshf_c_cond}, 2092 // FCVTZU <Vd>.<t>, <Vn>.<t>, #<fbits> 2093 {0xbf80fc00, 0x2f00fc00, FCVTZU, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__2S_40__4S_41__2D_81, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__2S_40__4S_41__2D_81, arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__64UIntimmhimmb_4__128UIntimmhimmb_8}, fcvtzu_asimdshf_c_cond}, 2094 // FCVTZU <V><d>, <V><n> 2095 {0xffbffc00, 0x7ea1b800, FCVTZU, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1}, nil}, 2096 // FCVTZU <Vd>.<t>, <Vn>.<t> 2097 {0xbfbffc00, 0x2ea1b800, FCVTZU, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 2098 // FDIV <Sd>, <Sn>, <Sm> 2099 {0xffe0fc00, 0x1e201800, FDIV, instArgs{arg_Sd, arg_Sn, arg_Sm}, nil}, 2100 // FDIV <Dd>, <Dn>, <Dm> 2101 {0xffe0fc00, 0x1e601800, FDIV, instArgs{arg_Dd, arg_Dn, arg_Dm}, nil}, 2102 // FDIV <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2103 {0xbfa0fc00, 0x2e20fc00, FDIV, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 2104 // FMADD <Sd>, <Sn>, <Sm>, <Sa> 2105 {0xffe08000, 0x1f000000, FMADD, instArgs{arg_Sd, arg_Sn, arg_Sm, arg_Sa}, nil}, 2106 // FMADD <Dd>, <Dn>, <Dm>, <Da> 2107 {0xffe08000, 0x1f400000, FMADD, instArgs{arg_Dd, arg_Dn, arg_Dm, arg_Da}, nil}, 2108 // FMAX <Sd>, <Sn>, <Sm> 2109 {0xffe0fc00, 0x1e204800, FMAX, instArgs{arg_Sd, arg_Sn, arg_Sm}, nil}, 2110 // FMAX <Dd>, <Dn>, <Dm> 2111 {0xffe0fc00, 0x1e604800, FMAX, instArgs{arg_Dd, arg_Dn, arg_Dm}, nil}, 2112 // FMAX <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2113 {0xbfa0fc00, 0x0e20f400, FMAX, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 2114 // FMAXNM <Sd>, <Sn>, <Sm> 2115 {0xffe0fc00, 0x1e206800, FMAXNM, instArgs{arg_Sd, arg_Sn, arg_Sm}, nil}, 2116 // FMAXNM <Dd>, <Dn>, <Dm> 2117 {0xffe0fc00, 0x1e606800, FMAXNM, instArgs{arg_Dd, arg_Dn, arg_Dm}, nil}, 2118 // FMAXNM <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2119 {0xbfa0fc00, 0x0e20c400, FMAXNM, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 2120 // FMAXNMP <V><d>, <Vn>.<t> 2121 {0xffbffc00, 0x7e30c800, FMAXNMP, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_arrangement_sz___2S_0__2D_1}, nil}, 2122 // FMAXNMP <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2123 {0xbfa0fc00, 0x2e20c400, FMAXNMP, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 2124 // FMAXNMV <V><d>, <Vn>.<t> 2125 {0xbfbffc00, 0x2e30c800, FMAXNMV, instArgs{arg_Vd_22_1__S_0, arg_Vn_arrangement_Q_sz___4S_10}, nil}, 2126 // FMAXP <V><d>, <Vn>.<t> 2127 {0xffbffc00, 0x7e30f800, FMAXP, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_arrangement_sz___2S_0__2D_1}, nil}, 2128 // FMAXP <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2129 {0xbfa0fc00, 0x2e20f400, FMAXP, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 2130 // FMAXV <V><d>, <Vn>.<t> 2131 {0xbfbffc00, 0x2e30f800, FMAXV, instArgs{arg_Vd_22_1__S_0, arg_Vn_arrangement_Q_sz___4S_10}, nil}, 2132 // FMIN <Sd>, <Sn>, <Sm> 2133 {0xffe0fc00, 0x1e205800, FMIN, instArgs{arg_Sd, arg_Sn, arg_Sm}, nil}, 2134 // FMIN <Dd>, <Dn>, <Dm> 2135 {0xffe0fc00, 0x1e605800, FMIN, instArgs{arg_Dd, arg_Dn, arg_Dm}, nil}, 2136 // FMIN <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2137 {0xbfa0fc00, 0x0ea0f400, FMIN, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 2138 // FMINNM <Sd>, <Sn>, <Sm> 2139 {0xffe0fc00, 0x1e207800, FMINNM, instArgs{arg_Sd, arg_Sn, arg_Sm}, nil}, 2140 // FMINNM <Dd>, <Dn>, <Dm> 2141 {0xffe0fc00, 0x1e607800, FMINNM, instArgs{arg_Dd, arg_Dn, arg_Dm}, nil}, 2142 // FMINNM <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2143 {0xbfa0fc00, 0x0ea0c400, FMINNM, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 2144 // FMINNMP <V><d>, <Vn>.<t> 2145 {0xffbffc00, 0x7eb0c800, FMINNMP, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_arrangement_sz___2S_0__2D_1}, nil}, 2146 // FMINNMP <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2147 {0xbfa0fc00, 0x2ea0c400, FMINNMP, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 2148 // FMINNMV <V><d>, <Vn>.<t> 2149 {0xbfbffc00, 0x2eb0c800, FMINNMV, instArgs{arg_Vd_22_1__S_0, arg_Vn_arrangement_Q_sz___4S_10}, nil}, 2150 // FMINP <V><d>, <Vn>.<t> 2151 {0xffbffc00, 0x7eb0f800, FMINP, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_arrangement_sz___2S_0__2D_1}, nil}, 2152 // FMINP <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2153 {0xbfa0fc00, 0x2ea0f400, FMINP, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 2154 // FMINV <V><d>, <Vn>.<t> 2155 {0xbfbffc00, 0x2eb0f800, FMINV, instArgs{arg_Vd_22_1__S_0, arg_Vn_arrangement_Q_sz___4S_10}, nil}, 2156 // FMLA <V><d>, <V><n>, <Vm>.<ts_1>[<index_1>] 2157 {0xff80f400, 0x5f801000, FMLA, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1, arg_Vm_arrangement_sz___S_0__D_1_index__sz_L_H__HL_00__H_10_1}, nil}, 2158 // FMLA <Vd>.<t>, <Vn>.<t>, <Vm>.<ts>[<index>] 2159 {0xbf80f400, 0x0f801000, FMLA, instArgs{arg_Vd_arrangement_Q_sz___2S_00__4S_10__2D_11, arg_Vn_arrangement_Q_sz___2S_00__4S_10__2D_11, arg_Vm_arrangement_sz___S_0__D_1_index__sz_L_H__HL_00__H_10_1}, nil}, 2160 // FMLA <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2161 {0xbfa0fc00, 0x0e20cc00, FMLA, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 2162 // FMLS <V><d>, <V><n>, <Vm>.<ts_1>[<index_1>] 2163 {0xff80f400, 0x5f805000, FMLS, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1, arg_Vm_arrangement_sz___S_0__D_1_index__sz_L_H__HL_00__H_10_1}, nil}, 2164 // FMLS <Vd>.<t>, <Vn>.<t>, <Vm>.<ts>[<index>] 2165 {0xbf80f400, 0x0f805000, FMLS, instArgs{arg_Vd_arrangement_Q_sz___2S_00__4S_10__2D_11, arg_Vn_arrangement_Q_sz___2S_00__4S_10__2D_11, arg_Vm_arrangement_sz___S_0__D_1_index__sz_L_H__HL_00__H_10_1}, nil}, 2166 // FMLS <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2167 {0xbfa0fc00, 0x0ea0cc00, FMLS, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 2168 // FMOV <Sd>, <Wn> 2169 {0xfffffc00, 0x1e270000, FMOV, instArgs{arg_Sd, arg_Wn}, nil}, 2170 // FMOV <Wd>, <Sn> 2171 {0xfffffc00, 0x1e260000, FMOV, instArgs{arg_Wd, arg_Sn}, nil}, 2172 // FMOV <Dd>, <Xn> 2173 {0xfffffc00, 0x9e670000, FMOV, instArgs{arg_Dd, arg_Xn}, nil}, 2174 // FMOV <Vd>.D[1], <Xn> 2175 {0xfffffc00, 0x9eaf0000, FMOV, instArgs{arg_Vd_arrangement_D_index__1, arg_Xn}, nil}, 2176 // FMOV <Xd>, <Dn> 2177 {0xfffffc00, 0x9e660000, FMOV, instArgs{arg_Xd, arg_Dn}, nil}, 2178 // FMOV <Xd>, <Vn>.D[1] 2179 {0xfffffc00, 0x9eae0000, FMOV, instArgs{arg_Xd, arg_Vn_arrangement_D_index__1}, nil}, 2180 // FMOV <Sd>, <Sn> 2181 {0xfffffc00, 0x1e204000, FMOV, instArgs{arg_Sd, arg_Sn}, nil}, 2182 // FMOV <Dd>, <Dn> 2183 {0xfffffc00, 0x1e604000, FMOV, instArgs{arg_Dd, arg_Dn}, nil}, 2184 // FMOV <Sd>, #<imm> 2185 {0xffe01fe0, 0x1e201000, FMOV, instArgs{arg_Sd, arg_immediate_exp_3_pre_4_imm8}, nil}, 2186 // FMOV <Dd>, #<imm> 2187 {0xffe01fe0, 0x1e601000, FMOV, instArgs{arg_Dd, arg_immediate_exp_3_pre_4_imm8}, nil}, 2188 // FMOV <Vd>.<t>, #<imm> 2189 {0xbff8fc00, 0x0f00f400, FMOV, instArgs{arg_Vd_arrangement_Q___2S_0__4S_1, arg_immediate_exp_3_pre_4_a_b_c_d_e_f_g_h}, nil}, 2190 // FMOV <Vd>.2D, #<imm> 2191 {0xfff8fc00, 0x6f00f400, FMOV, instArgs{arg_Vd_arrangement_2D, arg_immediate_exp_3_pre_4_a_b_c_d_e_f_g_h}, nil}, 2192 // FMSUB <Sd>, <Sn>, <Sm>, <Sa> 2193 {0xffe08000, 0x1f008000, FMSUB, instArgs{arg_Sd, arg_Sn, arg_Sm, arg_Sa}, nil}, 2194 // FMSUB <Dd>, <Dn>, <Dm>, <Da> 2195 {0xffe08000, 0x1f408000, FMSUB, instArgs{arg_Dd, arg_Dn, arg_Dm, arg_Da}, nil}, 2196 // FMUL <V><d>, <V><n>, <Vm>.<ts_1>[<index_1>] 2197 {0xff80f400, 0x5f809000, FMUL, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1, arg_Vm_arrangement_sz___S_0__D_1_index__sz_L_H__HL_00__H_10_1}, nil}, 2198 // FMUL <Vd>.<t>, <Vn>.<t>, <Vm>.<ts>[<index>] 2199 {0xbf80f400, 0x0f809000, FMUL, instArgs{arg_Vd_arrangement_Q_sz___2S_00__4S_10__2D_11, arg_Vn_arrangement_Q_sz___2S_00__4S_10__2D_11, arg_Vm_arrangement_sz___S_0__D_1_index__sz_L_H__HL_00__H_10_1}, nil}, 2200 // FMUL <Sd>, <Sn>, <Sm> 2201 {0xffe0fc00, 0x1e200800, FMUL, instArgs{arg_Sd, arg_Sn, arg_Sm}, nil}, 2202 // FMUL <Dd>, <Dn>, <Dm> 2203 {0xffe0fc00, 0x1e600800, FMUL, instArgs{arg_Dd, arg_Dn, arg_Dm}, nil}, 2204 // FMUL <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2205 {0xbfa0fc00, 0x2e20dc00, FMUL, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 2206 // FMULX <V><d>, <V><n>, <V><m> 2207 {0xffa0fc00, 0x5e20dc00, FMULX, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1, arg_Vm_22_1__S_0__D_1}, nil}, 2208 // FMULX <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2209 {0xbfa0fc00, 0x0e20dc00, FMULX, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 2210 // FMULX <V><d>, <V><n>, <Vm>.<ts_1>[<index_1>] 2211 {0xff80f400, 0x7f809000, FMULX, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1, arg_Vm_arrangement_sz___S_0__D_1_index__sz_L_H__HL_00__H_10_1}, nil}, 2212 // FMULX <Vd>.<t>, <Vn>.<t>, <Vm>.<ts>[<index>] 2213 {0xbf80f400, 0x2f809000, FMULX, instArgs{arg_Vd_arrangement_Q_sz___2S_00__4S_10__2D_11, arg_Vn_arrangement_Q_sz___2S_00__4S_10__2D_11, arg_Vm_arrangement_sz___S_0__D_1_index__sz_L_H__HL_00__H_10_1}, nil}, 2214 // FNEG <Sd>, <Sn> 2215 {0xfffffc00, 0x1e214000, FNEG, instArgs{arg_Sd, arg_Sn}, nil}, 2216 // FNEG <Dd>, <Dn> 2217 {0xfffffc00, 0x1e614000, FNEG, instArgs{arg_Dd, arg_Dn}, nil}, 2218 // FNEG <Vd>.<t>, <Vn>.<t> 2219 {0xbfbffc00, 0x2ea0f800, FNEG, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 2220 // FNMADD <Sd>, <Sn>, <Sm>, <Sa> 2221 {0xffe08000, 0x1f200000, FNMADD, instArgs{arg_Sd, arg_Sn, arg_Sm, arg_Sa}, nil}, 2222 // FNMADD <Dd>, <Dn>, <Dm>, <Da> 2223 {0xffe08000, 0x1f600000, FNMADD, instArgs{arg_Dd, arg_Dn, arg_Dm, arg_Da}, nil}, 2224 // FNMSUB <Sd>, <Sn>, <Sm>, <Sa> 2225 {0xffe08000, 0x1f208000, FNMSUB, instArgs{arg_Sd, arg_Sn, arg_Sm, arg_Sa}, nil}, 2226 // FNMSUB <Dd>, <Dn>, <Dm>, <Da> 2227 {0xffe08000, 0x1f608000, FNMSUB, instArgs{arg_Dd, arg_Dn, arg_Dm, arg_Da}, nil}, 2228 // FNMUL <Sd>, <Sn>, <Sm> 2229 {0xffe0fc00, 0x1e208800, FNMUL, instArgs{arg_Sd, arg_Sn, arg_Sm}, nil}, 2230 // FNMUL <Dd>, <Dn>, <Dm> 2231 {0xffe0fc00, 0x1e608800, FNMUL, instArgs{arg_Dd, arg_Dn, arg_Dm}, nil}, 2232 // FRECPE <V><d>, <V><n> 2233 {0xffbffc00, 0x5ea1d800, FRECPE, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1}, nil}, 2234 // FRECPE <Vd>.<t>, <Vn>.<t> 2235 {0xbfbffc00, 0x0ea1d800, FRECPE, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 2236 // FRECPS <V><d>, <V><n>, <V><m> 2237 {0xffa0fc00, 0x5e20fc00, FRECPS, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1, arg_Vm_22_1__S_0__D_1}, nil}, 2238 // FRECPS <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2239 {0xbfa0fc00, 0x0e20fc00, FRECPS, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 2240 // FRECPX <V><d>, <V><n> 2241 {0xffbffc00, 0x5ea1f800, FRECPX, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1}, nil}, 2242 // FRINTA <Sd>, <Sn> 2243 {0xfffffc00, 0x1e264000, FRINTA, instArgs{arg_Sd, arg_Sn}, nil}, 2244 // FRINTA <Dd>, <Dn> 2245 {0xfffffc00, 0x1e664000, FRINTA, instArgs{arg_Dd, arg_Dn}, nil}, 2246 // FRINTA <Vd>.<t>, <Vn>.<t> 2247 {0xbfbffc00, 0x2e218800, FRINTA, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 2248 // FRINTI <Sd>, <Sn> 2249 {0xfffffc00, 0x1e27c000, FRINTI, instArgs{arg_Sd, arg_Sn}, nil}, 2250 // FRINTI <Dd>, <Dn> 2251 {0xfffffc00, 0x1e67c000, FRINTI, instArgs{arg_Dd, arg_Dn}, nil}, 2252 // FRINTI <Vd>.<t>, <Vn>.<t> 2253 {0xbfbffc00, 0x2ea19800, FRINTI, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 2254 // FRINTM <Sd>, <Sn> 2255 {0xfffffc00, 0x1e254000, FRINTM, instArgs{arg_Sd, arg_Sn}, nil}, 2256 // FRINTM <Dd>, <Dn> 2257 {0xfffffc00, 0x1e654000, FRINTM, instArgs{arg_Dd, arg_Dn}, nil}, 2258 // FRINTM <Vd>.<t>, <Vn>.<t> 2259 {0xbfbffc00, 0x0e219800, FRINTM, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 2260 // FRINTN <Sd>, <Sn> 2261 {0xfffffc00, 0x1e244000, FRINTN, instArgs{arg_Sd, arg_Sn}, nil}, 2262 // FRINTN <Dd>, <Dn> 2263 {0xfffffc00, 0x1e644000, FRINTN, instArgs{arg_Dd, arg_Dn}, nil}, 2264 // FRINTN <Vd>.<t>, <Vn>.<t> 2265 {0xbfbffc00, 0x0e218800, FRINTN, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 2266 // FRINTP <Sd>, <Sn> 2267 {0xfffffc00, 0x1e24c000, FRINTP, instArgs{arg_Sd, arg_Sn}, nil}, 2268 // FRINTP <Dd>, <Dn> 2269 {0xfffffc00, 0x1e64c000, FRINTP, instArgs{arg_Dd, arg_Dn}, nil}, 2270 // FRINTP <Vd>.<t>, <Vn>.<t> 2271 {0xbfbffc00, 0x0ea18800, FRINTP, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 2272 // FRINTX <Sd>, <Sn> 2273 {0xfffffc00, 0x1e274000, FRINTX, instArgs{arg_Sd, arg_Sn}, nil}, 2274 // FRINTX <Dd>, <Dn> 2275 {0xfffffc00, 0x1e674000, FRINTX, instArgs{arg_Dd, arg_Dn}, nil}, 2276 // FRINTX <Vd>.<t>, <Vn>.<t> 2277 {0xbfbffc00, 0x2e219800, FRINTX, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 2278 // FRINTZ <Sd>, <Sn> 2279 {0xfffffc00, 0x1e25c000, FRINTZ, instArgs{arg_Sd, arg_Sn}, nil}, 2280 // FRINTZ <Dd>, <Dn> 2281 {0xfffffc00, 0x1e65c000, FRINTZ, instArgs{arg_Dd, arg_Dn}, nil}, 2282 // FRINTZ <Vd>.<t>, <Vn>.<t> 2283 {0xbfbffc00, 0x0ea19800, FRINTZ, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 2284 // FRSQRTE <V><d>, <V><n> 2285 {0xffbffc00, 0x7ea1d800, FRSQRTE, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1}, nil}, 2286 // FRSQRTE <Vd>.<t>, <Vn>.<t> 2287 {0xbfbffc00, 0x2ea1d800, FRSQRTE, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 2288 // FRSQRTS <V><d>, <V><n>, <V><m> 2289 {0xffa0fc00, 0x5ea0fc00, FRSQRTS, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1, arg_Vm_22_1__S_0__D_1}, nil}, 2290 // FRSQRTS <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2291 {0xbfa0fc00, 0x0ea0fc00, FRSQRTS, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 2292 // FSQRT <Sd>, <Sn> 2293 {0xfffffc00, 0x1e21c000, FSQRT, instArgs{arg_Sd, arg_Sn}, nil}, 2294 // FSQRT <Dd>, <Dn> 2295 {0xfffffc00, 0x1e61c000, FSQRT, instArgs{arg_Dd, arg_Dn}, nil}, 2296 // FSQRT <Vd>.<t>, <Vn>.<t> 2297 {0xbfbffc00, 0x2ea1f800, FSQRT, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 2298 // FSUB <Sd>, <Sn>, <Sm> 2299 {0xffe0fc00, 0x1e203800, FSUB, instArgs{arg_Sd, arg_Sn, arg_Sm}, nil}, 2300 // FSUB <Dd>, <Dn>, <Dm> 2301 {0xffe0fc00, 0x1e603800, FSUB, instArgs{arg_Dd, arg_Dn, arg_Dm}, nil}, 2302 // FSUB <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2303 {0xbfa0fc00, 0x0ea0d400, FSUB, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 2304 // MOV <Vd>.<ts>[<index1>], <Vn>.<ts>[<index2>] 2305 {0xffe08400, 0x6e000400, MOV, instArgs{arg_Vd_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4__imm5lt4gt_8_1, arg_Vn_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5_imm4__imm4lt30gt_1__imm4lt31gt_2__imm4lt32gt_4__imm4lt3gt_8_1}, nil}, 2306 // INS <Vd>.<ts>[<index1>], <Vn>.<ts>[<index2>] 2307 {0xffe08400, 0x6e000400, INS, instArgs{arg_Vd_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4__imm5lt4gt_8_1, arg_Vn_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5_imm4__imm4lt30gt_1__imm4lt31gt_2__imm4lt32gt_4__imm4lt3gt_8_1}, nil}, 2308 // MOV <Vd>.<ts>[<index>], <R><n> 2309 {0xffe0fc00, 0x4e001c00, MOV, instArgs{arg_Vd_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4__imm5lt4gt_8_1, arg_Rn_16_5__W_1__W_2__W_4__X_8}, nil}, 2310 // INS <Vd>.<ts>[<index>], <R><n> 2311 {0xffe0fc00, 0x4e001c00, INS, instArgs{arg_Vd_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4__imm5lt4gt_8_1, arg_Rn_16_5__W_1__W_2__W_4__X_8}, nil}, 2312 // LD1 <Vt>.<t>, [<Xn|SP>] 2313 {0xbffff000, 0x0c407000, LD1, instArgs{arg_Vt_1_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_offset}, nil}, 2314 // LD1 <Vt>.<t>, [<Xn|SP>] 2315 {0xbffff000, 0x0c40a000, LD1, instArgs{arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_offset}, nil}, 2316 // LD1 <Vt>.<t>, [<Xn|SP>] 2317 {0xbffff000, 0x0c406000, LD1, instArgs{arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_offset}, nil}, 2318 // LD1 <Vt>.<t>, [<Xn|SP>] 2319 {0xbffff000, 0x0c402000, LD1, instArgs{arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_offset}, nil}, 2320 // LD1 <Vt>.<t>, [<Xn|SP>], #<imm> 2321 {0xbffff000, 0x0cdf7000, LD1, instArgs{arg_Vt_1_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Q__8_0__16_1}, nil}, 2322 // LD1 <Vt>.<t>, [<Xn|SP>], #<Xm> 2323 {0xbfe0f000, 0x0cc07000, LD1, instArgs{arg_Vt_1_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Xm}, nil}, 2324 // LD1 <Vt>.<t>, [<Xn|SP>], #<imm_1> 2325 {0xbffff000, 0x0cdfa000, LD1, instArgs{arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Q__16_0__32_1}, nil}, 2326 // LD1 <Vt>.<t>, [<Xn|SP>], #<Xm> 2327 {0xbfe0f000, 0x0cc0a000, LD1, instArgs{arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Xm}, nil}, 2328 // LD1 <Vt>.<t>, [<Xn|SP>], #<imm_2> 2329 {0xbffff000, 0x0cdf6000, LD1, instArgs{arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Q__24_0__48_1}, nil}, 2330 // LD1 <Vt>.<t>, [<Xn|SP>], #<Xm> 2331 {0xbfe0f000, 0x0cc06000, LD1, instArgs{arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Xm}, nil}, 2332 // LD1 <Vt>.<t>, [<Xn|SP>], #<imm_3> 2333 {0xbffff000, 0x0cdf2000, LD1, instArgs{arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Q__32_0__64_1}, nil}, 2334 // LD1 <Vt>.<t>, [<Xn|SP>], #<Xm> 2335 {0xbfe0f000, 0x0cc02000, LD1, instArgs{arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Xm}, nil}, 2336 // LD1 <Vt>.B[<index>], [<Xn|SP>] 2337 {0xbfffe000, 0x0d400000, LD1, instArgs{arg_Vt_1_arrangement_B_index__Q_S_size_1, arg_Xns_mem_offset}, nil}, 2338 // LD1 <Vt>.H[<index_2>], [<Xn|SP>] 2339 {0xbfffe400, 0x0d404000, LD1, instArgs{arg_Vt_1_arrangement_H_index__Q_S_size_1, arg_Xns_mem_offset}, nil}, 2340 // LD1 <Vt>.S[<index_3>], [<Xn|SP>] 2341 {0xbfffec00, 0x0d408000, LD1, instArgs{arg_Vt_1_arrangement_S_index__Q_S_1, arg_Xns_mem_offset}, nil}, 2342 // LD1 <Vt>.D[<index_1>], [<Xn|SP>] 2343 {0xbffffc00, 0x0d408400, LD1, instArgs{arg_Vt_1_arrangement_D_index__Q_1, arg_Xns_mem_offset}, nil}, 2344 // LD1 <Vt>.B[<index>], [<Xn|SP>], #1 2345 {0xbfffe000, 0x0ddf0000, LD1, instArgs{arg_Vt_1_arrangement_B_index__Q_S_size_1, arg_Xns_mem_post_fixedimm_1}, nil}, 2346 // LD1 <Vt>.B[<index>], [<Xn|SP>], #<Xm> 2347 {0xbfe0e000, 0x0dc00000, LD1, instArgs{arg_Vt_1_arrangement_B_index__Q_S_size_1, arg_Xns_mem_post_Xm}, nil}, 2348 // LD1 <Vt>.H[<index_2>], [<Xn|SP>], #2 2349 {0xbfffe400, 0x0ddf4000, LD1, instArgs{arg_Vt_1_arrangement_H_index__Q_S_size_1, arg_Xns_mem_post_fixedimm_2}, nil}, 2350 // LD1 <Vt>.H[<index_2>], [<Xn|SP>], #<Xm> 2351 {0xbfe0e400, 0x0dc04000, LD1, instArgs{arg_Vt_1_arrangement_H_index__Q_S_size_1, arg_Xns_mem_post_Xm}, nil}, 2352 // LD1 <Vt>.S[<index_3>], [<Xn|SP>], #4 2353 {0xbfffec00, 0x0ddf8000, LD1, instArgs{arg_Vt_1_arrangement_S_index__Q_S_1, arg_Xns_mem_post_fixedimm_4}, nil}, 2354 // LD1 <Vt>.S[<index_3>], [<Xn|SP>], #<Xm> 2355 {0xbfe0ec00, 0x0dc08000, LD1, instArgs{arg_Vt_1_arrangement_S_index__Q_S_1, arg_Xns_mem_post_Xm}, nil}, 2356 // LD1 <Vt>.D[<index_1>], [<Xn|SP>], #8 2357 {0xbffffc00, 0x0ddf8400, LD1, instArgs{arg_Vt_1_arrangement_D_index__Q_1, arg_Xns_mem_post_fixedimm_8}, nil}, 2358 // LD1 <Vt>.D[<index_1>], [<Xn|SP>], #<Xm> 2359 {0xbfe0fc00, 0x0dc08400, LD1, instArgs{arg_Vt_1_arrangement_D_index__Q_1, arg_Xns_mem_post_Xm}, nil}, 2360 // LD1R <Vt>.<t>, [<Xn|SP>] 2361 {0xbffff000, 0x0d40c000, LD1R, instArgs{arg_Vt_1_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_offset}, nil}, 2362 // LD1R <Vt>.<t>, [<Xn|SP>], #<imm> 2363 {0xbffff000, 0x0ddfc000, LD1R, instArgs{arg_Vt_1_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_size__1_0__2_1__4_2__8_3}, nil}, 2364 // LD1R <Vt>.<t>, [<Xn|SP>], #<Xm> 2365 {0xbfe0f000, 0x0dc0c000, LD1R, instArgs{arg_Vt_1_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Xm}, nil}, 2366 // LD2 <Vt>.<t>, [<Xn|SP>] 2367 {0xbffff000, 0x0c408000, LD2, instArgs{arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Xns_mem_offset}, nil}, 2368 // LD2 <Vt>.<t>, [<Xn|SP>], #<imm> 2369 {0xbffff000, 0x0cdf8000, LD2, instArgs{arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Xns_mem_post_Q__16_0__32_1}, nil}, 2370 // LD2 <Vt>.<t>, [<Xn|SP>], #<Xm> 2371 {0xbfe0f000, 0x0cc08000, LD2, instArgs{arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Xns_mem_post_Xm}, nil}, 2372 // LD2 <Vt>.B[<index>], [<Xn|SP>] 2373 {0xbfffe000, 0x0d600000, LD2, instArgs{arg_Vt_2_arrangement_B_index__Q_S_size_1, arg_Xns_mem_offset}, nil}, 2374 // LD2 <Vt>.H[<index_2>], [<Xn|SP>] 2375 {0xbfffe400, 0x0d604000, LD2, instArgs{arg_Vt_2_arrangement_H_index__Q_S_size_1, arg_Xns_mem_offset}, nil}, 2376 // LD2 <Vt>.S[<index_3>], [<Xn|SP>] 2377 {0xbfffec00, 0x0d608000, LD2, instArgs{arg_Vt_2_arrangement_S_index__Q_S_1, arg_Xns_mem_offset}, nil}, 2378 // LD2 <Vt>.D[<index_1>], [<Xn|SP>] 2379 {0xbffffc00, 0x0d608400, LD2, instArgs{arg_Vt_2_arrangement_D_index__Q_1, arg_Xns_mem_offset}, nil}, 2380 // LD2 <Vt>.B[<index>], [<Xn|SP>], #2 2381 {0xbfffe000, 0x0dff0000, LD2, instArgs{arg_Vt_2_arrangement_B_index__Q_S_size_1, arg_Xns_mem_post_fixedimm_2}, nil}, 2382 // LD2 <Vt>.B[<index>], [<Xn|SP>], #<Xm> 2383 {0xbfe0e000, 0x0de00000, LD2, instArgs{arg_Vt_2_arrangement_B_index__Q_S_size_1, arg_Xns_mem_post_Xm}, nil}, 2384 // LD2 <Vt>.H[<index_2>], [<Xn|SP>], #4 2385 {0xbfffe400, 0x0dff4000, LD2, instArgs{arg_Vt_2_arrangement_H_index__Q_S_size_1, arg_Xns_mem_post_fixedimm_4}, nil}, 2386 // LD2 <Vt>.H[<index_2>], [<Xn|SP>], #<Xm> 2387 {0xbfe0e400, 0x0de04000, LD2, instArgs{arg_Vt_2_arrangement_H_index__Q_S_size_1, arg_Xns_mem_post_Xm}, nil}, 2388 // LD2 <Vt>.S[<index_3>], [<Xn|SP>], #8 2389 {0xbfffec00, 0x0dff8000, LD2, instArgs{arg_Vt_2_arrangement_S_index__Q_S_1, arg_Xns_mem_post_fixedimm_8}, nil}, 2390 // LD2 <Vt>.S[<index_3>], [<Xn|SP>], #<Xm> 2391 {0xbfe0ec00, 0x0de08000, LD2, instArgs{arg_Vt_2_arrangement_S_index__Q_S_1, arg_Xns_mem_post_Xm}, nil}, 2392 // LD2 <Vt>.D[<index_1>], [<Xn|SP>], #16 2393 {0xbffffc00, 0x0dff8400, LD2, instArgs{arg_Vt_2_arrangement_D_index__Q_1, arg_Xns_mem_post_fixedimm_16}, nil}, 2394 // LD2 <Vt>.D[<index_1>], [<Xn|SP>], #<Xm> 2395 {0xbfe0fc00, 0x0de08400, LD2, instArgs{arg_Vt_2_arrangement_D_index__Q_1, arg_Xns_mem_post_Xm}, nil}, 2396 // LD2R <Vt>.<t>, [<Xn|SP>] 2397 {0xbffff000, 0x0d60c000, LD2R, instArgs{arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_offset}, nil}, 2398 // LD2R <Vt>.<t>, [<Xn|SP>], #<imm> 2399 {0xbffff000, 0x0dffc000, LD2R, instArgs{arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_size__2_0__4_1__8_2__16_3}, nil}, 2400 // LD2R <Vt>.<t>, [<Xn|SP>], #<Xm> 2401 {0xbfe0f000, 0x0de0c000, LD2R, instArgs{arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Xm}, nil}, 2402 // LD3 <Vt>.<t>, [<Xn|SP>] 2403 {0xbffff000, 0x0c404000, LD3, instArgs{arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Xns_mem_offset}, nil}, 2404 // LD3 <Vt>.<t>, [<Xn|SP>], #<imm> 2405 {0xbffff000, 0x0cdf4000, LD3, instArgs{arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Xns_mem_post_Q__24_0__48_1}, nil}, 2406 // LD3 <Vt>.<t>, [<Xn|SP>], #<Xm> 2407 {0xbfe0f000, 0x0cc04000, LD3, instArgs{arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Xns_mem_post_Xm}, nil}, 2408 // LD3 <Vt>.B[<index>], [<Xn|SP>] 2409 {0xbfffe000, 0x0d402000, LD3, instArgs{arg_Vt_3_arrangement_B_index__Q_S_size_1, arg_Xns_mem_offset}, nil}, 2410 // LD3 <Vt>.H[<index_2>], [<Xn|SP>] 2411 {0xbfffe400, 0x0d406000, LD3, instArgs{arg_Vt_3_arrangement_H_index__Q_S_size_1, arg_Xns_mem_offset}, nil}, 2412 // LD3 <Vt>.S[<index_3>], [<Xn|SP>] 2413 {0xbfffec00, 0x0d40a000, LD3, instArgs{arg_Vt_3_arrangement_S_index__Q_S_1, arg_Xns_mem_offset}, nil}, 2414 // LD3 <Vt>.D[<index_1>], [<Xn|SP>] 2415 {0xbffffc00, 0x0d40a400, LD3, instArgs{arg_Vt_3_arrangement_D_index__Q_1, arg_Xns_mem_offset}, nil}, 2416 // LD3 <Vt>.B[<index>], [<Xn|SP>], #3 2417 {0xbfffe000, 0x0ddf2000, LD3, instArgs{arg_Vt_3_arrangement_B_index__Q_S_size_1, arg_Xns_mem_post_fixedimm_3}, nil}, 2418 // LD3 <Vt>.B[<index>], [<Xn|SP>], #<Xm> 2419 {0xbfe0e000, 0x0dc02000, LD3, instArgs{arg_Vt_3_arrangement_B_index__Q_S_size_1, arg_Xns_mem_post_Xm}, nil}, 2420 // LD3 <Vt>.H[<index_2>], [<Xn|SP>], #6 2421 {0xbfffe400, 0x0ddf6000, LD3, instArgs{arg_Vt_3_arrangement_H_index__Q_S_size_1, arg_Xns_mem_post_fixedimm_6}, nil}, 2422 // LD3 <Vt>.H[<index_2>], [<Xn|SP>], #<Xm> 2423 {0xbfe0e400, 0x0dc06000, LD3, instArgs{arg_Vt_3_arrangement_H_index__Q_S_size_1, arg_Xns_mem_post_Xm}, nil}, 2424 // LD3 <Vt>.S[<index_3>], [<Xn|SP>], #12 2425 {0xbfffec00, 0x0ddfa000, LD3, instArgs{arg_Vt_3_arrangement_S_index__Q_S_1, arg_Xns_mem_post_fixedimm_12}, nil}, 2426 // LD3 <Vt>.S[<index_3>], [<Xn|SP>], #<Xm> 2427 {0xbfe0ec00, 0x0dc0a000, LD3, instArgs{arg_Vt_3_arrangement_S_index__Q_S_1, arg_Xns_mem_post_Xm}, nil}, 2428 // LD3 <Vt>.D[<index_1>], [<Xn|SP>], #24 2429 {0xbffffc00, 0x0ddfa400, LD3, instArgs{arg_Vt_3_arrangement_D_index__Q_1, arg_Xns_mem_post_fixedimm_24}, nil}, 2430 // LD3 <Vt>.D[<index_1>], [<Xn|SP>], #<Xm> 2431 {0xbfe0fc00, 0x0dc0a400, LD3, instArgs{arg_Vt_3_arrangement_D_index__Q_1, arg_Xns_mem_post_Xm}, nil}, 2432 // LD3R <Vt>.<t>, [<Xn|SP>] 2433 {0xbffff000, 0x0d40e000, LD3R, instArgs{arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_offset}, nil}, 2434 // LD3R <Vt>.<t>, [<Xn|SP>], #<imm> 2435 {0xbffff000, 0x0ddfe000, LD3R, instArgs{arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_size__3_0__6_1__12_2__24_3}, nil}, 2436 // LD3R <Vt>.<t>, [<Xn|SP>], #<Xm> 2437 {0xbfe0f000, 0x0dc0e000, LD3R, instArgs{arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Xm}, nil}, 2438 // LD4 <Vt>.<t>, [<Xn|SP>] 2439 {0xbffff000, 0x0c400000, LD4, instArgs{arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Xns_mem_offset}, nil}, 2440 // LD4 <Vt>.<t>, [<Xn|SP>], #<imm> 2441 {0xbffff000, 0x0cdf0000, LD4, instArgs{arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Xns_mem_post_Q__32_0__64_1}, nil}, 2442 // LD4 <Vt>.<t>, [<Xn|SP>], #<Xm> 2443 {0xbfe0f000, 0x0cc00000, LD4, instArgs{arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Xns_mem_post_Xm}, nil}, 2444 // LD4 <Vt>.B[<index>], [<Xn|SP>] 2445 {0xbfffe000, 0x0d602000, LD4, instArgs{arg_Vt_4_arrangement_B_index__Q_S_size_1, arg_Xns_mem_offset}, nil}, 2446 // LD4 <Vt>.H[<index_2>], [<Xn|SP>] 2447 {0xbfffe400, 0x0d606000, LD4, instArgs{arg_Vt_4_arrangement_H_index__Q_S_size_1, arg_Xns_mem_offset}, nil}, 2448 // LD4 <Vt>.S[<index_3>], [<Xn|SP>] 2449 {0xbfffec00, 0x0d60a000, LD4, instArgs{arg_Vt_4_arrangement_S_index__Q_S_1, arg_Xns_mem_offset}, nil}, 2450 // LD4 <Vt>.D[<index_1>], [<Xn|SP>] 2451 {0xbffffc00, 0x0d60a400, LD4, instArgs{arg_Vt_4_arrangement_D_index__Q_1, arg_Xns_mem_offset}, nil}, 2452 // LD4 <Vt>.B[<index>], [<Xn|SP>], #4 2453 {0xbfffe000, 0x0dff2000, LD4, instArgs{arg_Vt_4_arrangement_B_index__Q_S_size_1, arg_Xns_mem_post_fixedimm_4}, nil}, 2454 // LD4 <Vt>.B[<index>], [<Xn|SP>], #<Xm> 2455 {0xbfe0e000, 0x0de02000, LD4, instArgs{arg_Vt_4_arrangement_B_index__Q_S_size_1, arg_Xns_mem_post_Xm}, nil}, 2456 // LD4 <Vt>.H[<index_2>], [<Xn|SP>], #8 2457 {0xbfffe400, 0x0dff6000, LD4, instArgs{arg_Vt_4_arrangement_H_index__Q_S_size_1, arg_Xns_mem_post_fixedimm_8}, nil}, 2458 // LD4 <Vt>.H[<index_2>], [<Xn|SP>], #<Xm> 2459 {0xbfe0e400, 0x0de06000, LD4, instArgs{arg_Vt_4_arrangement_H_index__Q_S_size_1, arg_Xns_mem_post_Xm}, nil}, 2460 // LD4 <Vt>.S[<index_3>], [<Xn|SP>], #16 2461 {0xbfffec00, 0x0dffa000, LD4, instArgs{arg_Vt_4_arrangement_S_index__Q_S_1, arg_Xns_mem_post_fixedimm_16}, nil}, 2462 // LD4 <Vt>.S[<index_3>], [<Xn|SP>], #<Xm> 2463 {0xbfe0ec00, 0x0de0a000, LD4, instArgs{arg_Vt_4_arrangement_S_index__Q_S_1, arg_Xns_mem_post_Xm}, nil}, 2464 // LD4 <Vt>.D[<index_1>], [<Xn|SP>], #32 2465 {0xbffffc00, 0x0dffa400, LD4, instArgs{arg_Vt_4_arrangement_D_index__Q_1, arg_Xns_mem_post_fixedimm_32}, nil}, 2466 // LD4 <Vt>.D[<index_1>], [<Xn|SP>], #<Xm> 2467 {0xbfe0fc00, 0x0de0a400, LD4, instArgs{arg_Vt_4_arrangement_D_index__Q_1, arg_Xns_mem_post_Xm}, nil}, 2468 // LD4R <Vt>.<t>, [<Xn|SP>] 2469 {0xbffff000, 0x0d60e000, LD4R, instArgs{arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_offset}, nil}, 2470 // LD4R <Vt>.<t>, [<Xn|SP>], #<imm> 2471 {0xbffff000, 0x0dffe000, LD4R, instArgs{arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_size__4_0__8_1__16_2__32_3}, nil}, 2472 // LD4R <Vt>.<t>, [<Xn|SP>], #<Xm> 2473 {0xbfe0f000, 0x0de0e000, LD4R, instArgs{arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Xm}, nil}, 2474 // LDNP <St>, <St2>, [<Xn|SP>{, #<imm_2>}] 2475 {0xffc00000, 0x2c400000, LDNP, instArgs{arg_St, arg_St2, arg_Xns_mem_optional_imm7_4_signed}, nil}, 2476 // LDNP <Dt>, <Dt2>, [<Xn|SP>{, #<imm>}] 2477 {0xffc00000, 0x6c400000, LDNP, instArgs{arg_Dt, arg_Dt2, arg_Xns_mem_optional_imm7_8_signed}, nil}, 2478 // LDNP <Qt>, <Qt2>, [<Xn|SP>{, #<imm_1>}] 2479 {0xffc00000, 0xac400000, LDNP, instArgs{arg_Qt, arg_Qt2, arg_Xns_mem_optional_imm7_16_signed}, nil}, 2480 // LDP <St>, <St2>, [<Xn|SP>], #<imm_5> 2481 {0xffc00000, 0x2cc00000, LDP, instArgs{arg_St, arg_St2, arg_Xns_mem_post_imm7_4_signed}, nil}, 2482 // LDP <Dt>, <Dt2>, [<Xn|SP>], #<imm_1> 2483 {0xffc00000, 0x6cc00000, LDP, instArgs{arg_Dt, arg_Dt2, arg_Xns_mem_post_imm7_8_signed}, nil}, 2484 // LDP <Qt>, <Qt2>, [<Xn|SP>], #<imm_3> 2485 {0xffc00000, 0xacc00000, LDP, instArgs{arg_Qt, arg_Qt2, arg_Xns_mem_post_imm7_16_signed}, nil}, 2486 // LDP <St>, <St2>, [<Xn|SP>{, #<imm_5>}]! 2487 {0xffc00000, 0x2dc00000, LDP, instArgs{arg_St, arg_St2, arg_Xns_mem_wb_imm7_4_signed}, nil}, 2488 // LDP <Dt>, <Dt2>, [<Xn|SP>{, #<imm_1>}]! 2489 {0xffc00000, 0x6dc00000, LDP, instArgs{arg_Dt, arg_Dt2, arg_Xns_mem_wb_imm7_8_signed}, nil}, 2490 // LDP <Qt>, <Qt2>, [<Xn|SP>{, #<imm_3>}]! 2491 {0xffc00000, 0xadc00000, LDP, instArgs{arg_Qt, arg_Qt2, arg_Xns_mem_wb_imm7_16_signed}, nil}, 2492 // LDP <St>, <St2>, [<Xn|SP>{, #<imm_4>}] 2493 {0xffc00000, 0x2d400000, LDP, instArgs{arg_St, arg_St2, arg_Xns_mem_optional_imm7_4_signed}, nil}, 2494 // LDP <Dt>, <Dt2>, [<Xn|SP>{, #<imm>}] 2495 {0xffc00000, 0x6d400000, LDP, instArgs{arg_Dt, arg_Dt2, arg_Xns_mem_optional_imm7_8_signed}, nil}, 2496 // LDP <Qt>, <Qt2>, [<Xn|SP>{, #<imm_2>}] 2497 {0xffc00000, 0xad400000, LDP, instArgs{arg_Qt, arg_Qt2, arg_Xns_mem_optional_imm7_16_signed}, nil}, 2498 // LDR <Bt>, [<Xn|SP>], #<simm> 2499 {0xffe00c00, 0x3c400400, LDR, instArgs{arg_Bt, arg_Xns_mem_post_imm9_1_signed}, nil}, 2500 // LDR <Ht>, [<Xn|SP>], #<simm> 2501 {0xffe00c00, 0x7c400400, LDR, instArgs{arg_Ht, arg_Xns_mem_post_imm9_1_signed}, nil}, 2502 // LDR <St>, [<Xn|SP>], #<simm> 2503 {0xffe00c00, 0xbc400400, LDR, instArgs{arg_St, arg_Xns_mem_post_imm9_1_signed}, nil}, 2504 // LDR <Dt>, [<Xn|SP>], #<simm> 2505 {0xffe00c00, 0xfc400400, LDR, instArgs{arg_Dt, arg_Xns_mem_post_imm9_1_signed}, nil}, 2506 // LDR <Qt>, [<Xn|SP>], #<simm> 2507 {0xffe00c00, 0x3cc00400, LDR, instArgs{arg_Qt, arg_Xns_mem_post_imm9_1_signed}, nil}, 2508 // LDR <Bt>, [<Xn|SP>{, #<simm>}]! 2509 {0xffe00c00, 0x3c400c00, LDR, instArgs{arg_Bt, arg_Xns_mem_wb_imm9_1_signed}, nil}, 2510 // LDR <Ht>, [<Xn|SP>{, #<simm>}]! 2511 {0xffe00c00, 0x7c400c00, LDR, instArgs{arg_Ht, arg_Xns_mem_wb_imm9_1_signed}, nil}, 2512 // LDR <St>, [<Xn|SP>{, #<simm>}]! 2513 {0xffe00c00, 0xbc400c00, LDR, instArgs{arg_St, arg_Xns_mem_wb_imm9_1_signed}, nil}, 2514 // LDR <Dt>, [<Xn|SP>{, #<simm>}]! 2515 {0xffe00c00, 0xfc400c00, LDR, instArgs{arg_Dt, arg_Xns_mem_wb_imm9_1_signed}, nil}, 2516 // LDR <Qt>, [<Xn|SP>{, #<simm>}]! 2517 {0xffe00c00, 0x3cc00c00, LDR, instArgs{arg_Qt, arg_Xns_mem_wb_imm9_1_signed}, nil}, 2518 // LDR <Bt>, [<Xn|SP>{, #<pimm>}] 2519 {0xffc00000, 0x3d400000, LDR, instArgs{arg_Bt, arg_Xns_mem_optional_imm12_1_unsigned}, nil}, 2520 // LDR <Ht>, [<Xn|SP>{, #<pimm_2>}] 2521 {0xffc00000, 0x7d400000, LDR, instArgs{arg_Ht, arg_Xns_mem_optional_imm12_2_unsigned}, nil}, 2522 // LDR <St>, [<Xn|SP>{, #<pimm_4>}] 2523 {0xffc00000, 0xbd400000, LDR, instArgs{arg_St, arg_Xns_mem_optional_imm12_4_unsigned}, nil}, 2524 // LDR <Dt>, [<Xn|SP>{, #<pimm_1>}] 2525 {0xffc00000, 0xfd400000, LDR, instArgs{arg_Dt, arg_Xns_mem_optional_imm12_8_unsigned}, nil}, 2526 // LDR <Qt>, [<Xn|SP>{, #<pimm_3>}] 2527 {0xffc00000, 0x3dc00000, LDR, instArgs{arg_Qt, arg_Xns_mem_optional_imm12_16_unsigned}, nil}, 2528 // LDR <St>, <label> 2529 {0xff000000, 0x1c000000, LDR, instArgs{arg_St, arg_slabel_imm19_2}, nil}, 2530 // LDR <Dt>, <label> 2531 {0xff000000, 0x5c000000, LDR, instArgs{arg_Dt, arg_slabel_imm19_2}, nil}, 2532 // LDR <Qt>, <label> 2533 {0xff000000, 0x9c000000, LDR, instArgs{arg_Qt, arg_slabel_imm19_2}, nil}, 2534 // LDR <Bt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}] 2535 {0xffe00c00, 0x3c600800, LDR, instArgs{arg_Bt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__absent_0__0_1}, nil}, 2536 // LDR <Ht>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}] 2537 {0xffe00c00, 0x7c600800, LDR, instArgs{arg_Ht, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__1_1}, nil}, 2538 // LDR <St>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}] 2539 {0xffe00c00, 0xbc600800, LDR, instArgs{arg_St, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__2_1}, nil}, 2540 // LDR <Dt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}] 2541 {0xffe00c00, 0xfc600800, LDR, instArgs{arg_Dt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__3_1}, nil}, 2542 // LDR <Qt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}] 2543 {0xffe00c00, 0x3ce00800, LDR, instArgs{arg_Qt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__4_1}, nil}, 2544 // LDUR <Bt>, [<Xn|SP>{, #<simm>}] 2545 {0xffe00c00, 0x3c400000, LDUR, instArgs{arg_Bt, arg_Xns_mem_optional_imm9_1_signed}, nil}, 2546 // LDUR <Ht>, [<Xn|SP>{, #<simm>}] 2547 {0xffe00c00, 0x7c400000, LDUR, instArgs{arg_Ht, arg_Xns_mem_optional_imm9_1_signed}, nil}, 2548 // LDUR <St>, [<Xn|SP>{, #<simm>}] 2549 {0xffe00c00, 0xbc400000, LDUR, instArgs{arg_St, arg_Xns_mem_optional_imm9_1_signed}, nil}, 2550 // LDUR <Dt>, [<Xn|SP>{, #<simm>}] 2551 {0xffe00c00, 0xfc400000, LDUR, instArgs{arg_Dt, arg_Xns_mem_optional_imm9_1_signed}, nil}, 2552 // LDUR <Qt>, [<Xn|SP>{, #<simm>}] 2553 {0xffe00c00, 0x3cc00000, LDUR, instArgs{arg_Qt, arg_Xns_mem_optional_imm9_1_signed}, nil}, 2554 // MLA <Vd>.<t>, <Vn>.<t>, <Vm>.<ts>[<index>] 2555 {0xbf00f400, 0x2f000000, MLA, instArgs{arg_Vd_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil}, 2556 // MLA <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2557 {0xbf20fc00, 0x0e209400, MLA, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 2558 // MLS <Vd>.<t>, <Vn>.<t>, <Vm>.<ts>[<index>] 2559 {0xbf00f400, 0x2f004000, MLS, instArgs{arg_Vd_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil}, 2560 // MLS <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2561 {0xbf20fc00, 0x2e209400, MLS, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 2562 // MOV <Wd>, <Vn>.S[<index>] 2563 {0xffe0fc00, 0x0e003c00, MOV, instArgs{arg_Wd, arg_Vn_arrangement_S_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4_1}, mov_umov_asimdins_w_w_cond}, 2564 // UMOV <Wd>, <Vn>.<ts>[<index>] 2565 {0xffe0fc00, 0x0e003c00, UMOV, instArgs{arg_Wd, arg_Vn_arrangement_imm5___B_1__H_2__S_4_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4_1}, nil}, 2566 // MOV <Xd>, <Vn>.D[<index_1>] 2567 {0xffe0fc00, 0x4e003c00, MOV, instArgs{arg_Xd, arg_Vn_arrangement_D_index__imm5_1}, mov_umov_asimdins_x_x_cond}, 2568 // UMOV <Xd>, <Vn>.<ts_1>[<index_1>] 2569 {0xffe0fc00, 0x4e003c00, UMOV, instArgs{arg_Xd, arg_Vn_arrangement_imm5___D_8_index__imm5_1}, nil}, 2570 // MOV <Vd>.<t>, <Vn>.<t> 2571 {0xbfe0fc00, 0x0ea01c00, MOV, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_arrangement_Q___8B_0__16B_1}, mov_orr_asimdsame_only_cond}, 2572 // ORR <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2573 {0xbfe0fc00, 0x0ea01c00, ORR, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_arrangement_Q___8B_0__16B_1, arg_Vm_arrangement_Q___8B_0__16B_1}, nil}, 2574 // MOVI <Vd>.<t_2>, #<imm8>{, LSL #0} 2575 {0xbff8fc00, 0x0f00e400, MOVI, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_immediate_OptLSLZero__a_b_c_d_e_f_g_h}, nil}, 2576 // MOVI <Vd>.<t>, #<imm8>{, LSL #<amount>} 2577 {0xbff8dc00, 0x0f008400, MOVI, instArgs{arg_Vd_arrangement_Q___4H_0__8H_1, arg_immediate_OptLSL__a_b_c_d_e_f_g_h_cmode__0_0__8_1}, nil}, 2578 // MOVI <Vd>.<t_1>, #<imm8>{, LSL #<amount>} 2579 {0xbff89c00, 0x0f000400, MOVI, instArgs{arg_Vd_arrangement_Q___2S_0__4S_1, arg_immediate_OptLSL__a_b_c_d_e_f_g_h_cmode__0_0__8_1__16_2__24_3}, nil}, 2580 // MOVI <Vd>.<t_1>, #<imm8>, MSL #<amount> 2581 {0xbff8ec00, 0x0f00c400, MOVI, instArgs{arg_Vd_arrangement_Q___2S_0__4S_1, arg_immediate_MSL__a_b_c_d_e_f_g_h_cmode__8_0__16_1}, nil}, 2582 // MOVI <Dd>, #<imm> 2583 {0xfff8fc00, 0x2f00e400, MOVI, instArgs{arg_Dd, arg_immediate_8x8_a_b_c_d_e_f_g_h}, nil}, 2584 // MOVI <Vd>.2D, #<imm> 2585 {0xfff8fc00, 0x6f00e400, MOVI, instArgs{arg_Vd_arrangement_2D, arg_immediate_8x8_a_b_c_d_e_f_g_h}, nil}, 2586 // MUL <Vd>.<t>, <Vn>.<t>, <Vm>.<ts>[<index>] 2587 {0xbf00f400, 0x0f008000, MUL, instArgs{arg_Vd_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil}, 2588 // MUL <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2589 {0xbf20fc00, 0x0e209c00, MUL, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 2590 // MVN <Vd>.<t>, <Vn>.<t> 2591 {0xbffffc00, 0x2e205800, MVN, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_arrangement_Q___8B_0__16B_1}, nil}, 2592 // NOT <Vd>.<t>, <Vn>.<t> 2593 {0xbffffc00, 0x2e205800, NOT, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_arrangement_Q___8B_0__16B_1}, nil}, 2594 // MVNI <Vd>.<t>, #<imm8>{, LSL #<amount>} 2595 {0xbff8dc00, 0x2f008400, MVNI, instArgs{arg_Vd_arrangement_Q___4H_0__8H_1, arg_immediate_OptLSL__a_b_c_d_e_f_g_h_cmode__0_0__8_1}, nil}, 2596 // MVNI <Vd>.<t_1>, #<imm8>{, LSL #<amount>} 2597 {0xbff89c00, 0x2f000400, MVNI, instArgs{arg_Vd_arrangement_Q___2S_0__4S_1, arg_immediate_OptLSL__a_b_c_d_e_f_g_h_cmode__0_0__8_1__16_2__24_3}, nil}, 2598 // MVNI <Vd>.<t_1>, #<imm8>, MSL #<amount> 2599 {0xbff8ec00, 0x2f00c400, MVNI, instArgs{arg_Vd_arrangement_Q___2S_0__4S_1, arg_immediate_MSL__a_b_c_d_e_f_g_h_cmode__8_0__16_1}, nil}, 2600 // NEG <V><d>, <V><n> 2601 {0xff3ffc00, 0x7e20b800, NEG, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3}, nil}, 2602 // NEG <Vd>.<t>, <Vn>.<t> 2603 {0xbf3ffc00, 0x2e20b800, NEG, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil}, 2604 // ORN <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2605 {0xbfe0fc00, 0x0ee01c00, ORN, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_arrangement_Q___8B_0__16B_1, arg_Vm_arrangement_Q___8B_0__16B_1}, nil}, 2606 // ORR <Vd>.<t>, #<imm8>{, LSL #<amount>} 2607 {0xbff8dc00, 0x0f009400, ORR, instArgs{arg_Vd_arrangement_Q___4H_0__8H_1, arg_immediate_OptLSL__a_b_c_d_e_f_g_h_cmode__0_0__8_1}, nil}, 2608 // ORR <Vd>.<t_1>, #<imm8>{, LSL #<amount>} 2609 {0xbff89c00, 0x0f001400, ORR, instArgs{arg_Vd_arrangement_Q___2S_0__4S_1, arg_immediate_OptLSL__a_b_c_d_e_f_g_h_cmode__0_0__8_1__16_2__24_3}, nil}, 2610 // PMUL <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2611 {0xbf20fc00, 0x2e209c00, PMUL, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01, arg_Vn_arrangement_size_Q___8B_00__16B_01, arg_Vm_arrangement_size_Q___8B_00__16B_01}, nil}, 2612 // PMULL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb> 2613 {0xff20fc00, 0x0e20e000, PMULL, instArgs{arg_Vd_arrangement_size___8H_0__1Q_3, arg_Vn_arrangement_size_Q___8B_00__16B_01__1D_30__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__1D_30__2D_31}, nil}, 2614 // PMULL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb> 2615 {0xff20fc00, 0x4e20e000, PMULL2, instArgs{arg_Vd_arrangement_size___8H_0__1Q_3, arg_Vn_arrangement_size_Q___8B_00__16B_01__1D_30__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__1D_30__2D_31}, nil}, 2616 // RADDHN <Vd>.<tb>, <Vn>.<ta>, <Vm>.<ta> 2617 {0xff20fc00, 0x2e204000, RADDHN, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size___8H_0__4S_1__2D_2, arg_Vm_arrangement_size___8H_0__4S_1__2D_2}, nil}, 2618 // RADDHN2 <Vd>.<tb>, <Vn>.<ta>, <Vm>.<ta> 2619 {0xff20fc00, 0x6e204000, RADDHN2, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size___8H_0__4S_1__2D_2, arg_Vm_arrangement_size___8H_0__4S_1__2D_2}, nil}, 2620 // RBIT <Vd>.<t>, <Vn>.<t> 2621 {0xbffffc00, 0x2e605800, RBIT, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_arrangement_Q___8B_0__16B_1}, nil}, 2622 // REV16 <Vd>.<t>, <Vn>.<t> 2623 {0xbf3ffc00, 0x0e201800, REV16, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01, arg_Vn_arrangement_size_Q___8B_00__16B_01}, nil}, 2624 // REV32 <Vd>.<t>, <Vn>.<t> 2625 {0xbf3ffc00, 0x2e200800, REV32, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11}, nil}, 2626 // REV64 <Vd>.<t>, <Vn>.<t> 2627 {0xbf3ffc00, 0x0e200800, REV64, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 2628 // RSHRN <Vd>.<tb>, <Vn>.<ta>, #<shift> 2629 {0xff80fc00, 0x0f008c00, RSHRN, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, rshrn_asimdshf_n_cond}, 2630 // RSHRN2 <Vd>.<tb>, <Vn>.<ta>, #<shift> 2631 {0xff80fc00, 0x4f008c00, RSHRN2, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, rshrn_asimdshf_n_cond}, 2632 // RSUBHN <Vd>.<tb>, <Vn>.<ta>, <Vm>.<ta> 2633 {0xff20fc00, 0x2e206000, RSUBHN, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size___8H_0__4S_1__2D_2, arg_Vm_arrangement_size___8H_0__4S_1__2D_2}, nil}, 2634 // RSUBHN2 <Vd>.<tb>, <Vn>.<ta>, <Vm>.<ta> 2635 {0xff20fc00, 0x6e206000, RSUBHN2, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size___8H_0__4S_1__2D_2, arg_Vm_arrangement_size___8H_0__4S_1__2D_2}, nil}, 2636 // SABA <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2637 {0xbf20fc00, 0x0e207c00, SABA, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 2638 // SABAL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb> 2639 {0xff20fc00, 0x0e205000, SABAL, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 2640 // SABAL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb> 2641 {0xff20fc00, 0x4e205000, SABAL2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 2642 // SABD <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2643 {0xbf20fc00, 0x0e207400, SABD, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 2644 // SABDL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb> 2645 {0xff20fc00, 0x0e207000, SABDL, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 2646 // SABDL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb> 2647 {0xff20fc00, 0x4e207000, SABDL2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 2648 // SADALP <Vd>.<ta>, <Vn>.<tb> 2649 {0xbf3ffc00, 0x0e206800, SADALP, instArgs{arg_Vd_arrangement_size_Q___4H_00__8H_01__2S_10__4S_11__1D_20__2D_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 2650 // SADDL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb> 2651 {0xff20fc00, 0x0e200000, SADDL, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 2652 // SADDL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb> 2653 {0xff20fc00, 0x4e200000, SADDL2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 2654 // SADDLP <Vd>.<ta>, <Vn>.<tb> 2655 {0xbf3ffc00, 0x0e202800, SADDLP, instArgs{arg_Vd_arrangement_size_Q___4H_00__8H_01__2S_10__4S_11__1D_20__2D_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 2656 // SADDLV <V><d>, <Vn>.<t> 2657 {0xbf3ffc00, 0x0e303800, SADDLV, instArgs{arg_Vd_22_2__H_0__S_1__D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__4S_21}, nil}, 2658 // SADDW <Vd>.<ta>, <Vn>.<ta>, <Vm>.<tb> 2659 {0xff20fc00, 0x0e201000, SADDW, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size___8H_0__4S_1__2D_2, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 2660 // SADDW2 <Vd>.<ta>, <Vn>.<ta>, <Vm>.<tb> 2661 {0xff20fc00, 0x4e201000, SADDW2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size___8H_0__4S_1__2D_2, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 2662 // SCVTF <Sd>, <Wn>, #<fbits> 2663 {0xffff0000, 0x1e020000, SCVTF, instArgs{arg_Sd, arg_Wn, arg_immediate_fbits_min_1_max_32_sub_64_scale}, nil}, 2664 // SCVTF <Dd>, <Wn>, #<fbits> 2665 {0xffff0000, 0x1e420000, SCVTF, instArgs{arg_Dd, arg_Wn, arg_immediate_fbits_min_1_max_32_sub_64_scale}, nil}, 2666 // SCVTF <Sd>, <Xn>, #<fbits> 2667 {0xffff0000, 0x9e020000, SCVTF, instArgs{arg_Sd, arg_Xn, arg_immediate_fbits_min_1_max_64_sub_64_scale}, nil}, 2668 // SCVTF <Dd>, <Xn>, #<fbits> 2669 {0xffff0000, 0x9e420000, SCVTF, instArgs{arg_Dd, arg_Xn, arg_immediate_fbits_min_1_max_64_sub_64_scale}, nil}, 2670 // SCVTF <Sd>, <Wn> 2671 {0xfffffc00, 0x1e220000, SCVTF, instArgs{arg_Sd, arg_Wn}, nil}, 2672 // SCVTF <Dd>, <Wn> 2673 {0xfffffc00, 0x1e620000, SCVTF, instArgs{arg_Dd, arg_Wn}, nil}, 2674 // SCVTF <Sd>, <Xn> 2675 {0xfffffc00, 0x9e220000, SCVTF, instArgs{arg_Sd, arg_Xn}, nil}, 2676 // SCVTF <Dd>, <Xn> 2677 {0xfffffc00, 0x9e620000, SCVTF, instArgs{arg_Dd, arg_Xn}, nil}, 2678 // SCVTF <V><d>, <V><n>, #<fbits> 2679 {0xff80fc00, 0x5f00e400, SCVTF, instArgs{arg_Vd_19_4__S_4__D_8, arg_Vn_19_4__S_4__D_8, arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__64UIntimmhimmb_4__128UIntimmhimmb_8}, scvtf_asisdshf_c_cond}, 2680 // SCVTF <Vd>.<t>, <Vn>.<t>, #<fbits> 2681 {0xbf80fc00, 0x0f00e400, SCVTF, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__2S_40__4S_41__2D_81, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__2S_40__4S_41__2D_81, arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__64UIntimmhimmb_4__128UIntimmhimmb_8}, scvtf_asimdshf_c_cond}, 2682 // SCVTF <V><d>, <V><n> 2683 {0xffbffc00, 0x5e21d800, SCVTF, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1}, nil}, 2684 // SCVTF <Vd>.<t>, <Vn>.<t> 2685 {0xbfbffc00, 0x0e21d800, SCVTF, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 2686 // SHA1C <Qd>, <Sn>, <Vm>.4S 2687 {0xffe0fc00, 0x5e000000, SHA1C, instArgs{arg_Qd, arg_Sn, arg_Vm_arrangement_4S}, nil}, 2688 // SHA1H <Sd>, <Sn> 2689 {0xfffffc00, 0x5e280800, SHA1H, instArgs{arg_Sd, arg_Sn}, nil}, 2690 // SHA1M <Qd>, <Sn>, <Vm>.4S 2691 {0xffe0fc00, 0x5e002000, SHA1M, instArgs{arg_Qd, arg_Sn, arg_Vm_arrangement_4S}, nil}, 2692 // SHA1P <Qd>, <Sn>, <Vm>.4S 2693 {0xffe0fc00, 0x5e001000, SHA1P, instArgs{arg_Qd, arg_Sn, arg_Vm_arrangement_4S}, nil}, 2694 // SHA1SU0 <Vd>.4S, <Vn>.4S, <Vm>.4S 2695 {0xffe0fc00, 0x5e003000, SHA1SU0, instArgs{arg_Vd_arrangement_4S, arg_Vn_arrangement_4S, arg_Vm_arrangement_4S}, nil}, 2696 // SHA1SU1 <Vd>.4S, <Vn>.4S 2697 {0xfffffc00, 0x5e281800, SHA1SU1, instArgs{arg_Vd_arrangement_4S, arg_Vn_arrangement_4S}, nil}, 2698 // SHA256H <Qd>, <Qn>, <Vm>.4S 2699 {0xffe0fc00, 0x5e004000, SHA256H, instArgs{arg_Qd, arg_Qn, arg_Vm_arrangement_4S}, nil}, 2700 // SHA256H2 <Qd>, <Qn>, <Vm>.4S 2701 {0xffe0fc00, 0x5e005000, SHA256H2, instArgs{arg_Qd, arg_Qn, arg_Vm_arrangement_4S}, nil}, 2702 // SHA256SU0 <Vd>.4S, <Vn>.4S 2703 {0xfffffc00, 0x5e282800, SHA256SU0, instArgs{arg_Vd_arrangement_4S, arg_Vn_arrangement_4S}, nil}, 2704 // SHA256SU1 <Vd>.4S, <Vn>.4S, <Vm>.4S 2705 {0xffe0fc00, 0x5e006000, SHA256SU1, instArgs{arg_Vd_arrangement_4S, arg_Vn_arrangement_4S, arg_Vm_arrangement_4S}, nil}, 2706 // SHADD <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2707 {0xbf20fc00, 0x0e200400, SHADD, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 2708 // SHL <V><d>, <V><n>, #<shift> 2709 {0xff80fc00, 0x5f005400, SHL, instArgs{arg_Vd_19_4__D_8, arg_Vn_19_4__D_8, arg_immediate_0_63_immh_immb__UIntimmhimmb64_8}, shl_asisdshf_r_cond}, 2710 // SHL <Vd>.<t>, <Vn>.<t>, #<shift> 2711 {0xbf80fc00, 0x0f005400, SHL, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8}, shl_asimdshf_r_cond}, 2712 // SHLL <Vd>.<ta>, <Vn>.<tb>, #<shift> 2713 {0xff3ffc00, 0x2e213800, SHLL, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_immediate_0_width_size__8_0__16_1__32_2}, nil}, 2714 // SHLL2 <Vd>.<ta>, <Vn>.<tb>, #<shift> 2715 {0xff3ffc00, 0x6e213800, SHLL2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_immediate_0_width_size__8_0__16_1__32_2}, nil}, 2716 // SHRN <Vd>.<tb>, <Vn>.<ta>, #<shift> 2717 {0xff80fc00, 0x0f008400, SHRN, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, shrn_asimdshf_n_cond}, 2718 // SHRN2 <Vd>.<tb>, <Vn>.<ta>, #<shift> 2719 {0xff80fc00, 0x4f008400, SHRN2, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, shrn_asimdshf_n_cond}, 2720 // SHSUB <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2721 {0xbf20fc00, 0x0e202400, SHSUB, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 2722 // SLI <V><d>, <V><n>, #<shift> 2723 {0xff80fc00, 0x7f005400, SLI, instArgs{arg_Vd_19_4__D_8, arg_Vn_19_4__D_8, arg_immediate_0_63_immh_immb__UIntimmhimmb64_8}, sli_asisdshf_r_cond}, 2724 // SLI <Vd>.<t>, <Vn>.<t>, #<shift> 2725 {0xbf80fc00, 0x2f005400, SLI, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8}, sli_asimdshf_r_cond}, 2726 // SMAX <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2727 {0xbf20fc00, 0x0e206400, SMAX, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 2728 // SMAXP <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2729 {0xbf20fc00, 0x0e20a400, SMAXP, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 2730 // SMAXV <V><d>, <Vn>.<t> 2731 {0xbf3ffc00, 0x0e30a800, SMAXV, instArgs{arg_Vd_22_2__B_0__H_1__S_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__4S_21}, nil}, 2732 // SMIN <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2733 {0xbf20fc00, 0x0e206c00, SMIN, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 2734 // SMINP <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2735 {0xbf20fc00, 0x0e20ac00, SMINP, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 2736 // SMINV <V><d>, <Vn>.<t> 2737 {0xbf3ffc00, 0x0e31a800, SMINV, instArgs{arg_Vd_22_2__B_0__H_1__S_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__4S_21}, nil}, 2738 // SMLAL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<ts>[<index>] 2739 {0xff00f400, 0x0f002000, SMLAL, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil}, 2740 // SMLAL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<ts>[<index>] 2741 {0xff00f400, 0x4f002000, SMLAL2, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil}, 2742 // SMLAL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb> 2743 {0xff20fc00, 0x0e208000, SMLAL, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 2744 // SMLAL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb> 2745 {0xff20fc00, 0x4e208000, SMLAL2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 2746 // SMLSL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<ts>[<index>] 2747 {0xff00f400, 0x0f006000, SMLSL, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil}, 2748 // SMLSL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<ts>[<index>] 2749 {0xff00f400, 0x4f006000, SMLSL2, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil}, 2750 // SMLSL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb> 2751 {0xff20fc00, 0x0e20a000, SMLSL, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 2752 // SMLSL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb> 2753 {0xff20fc00, 0x4e20a000, SMLSL2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 2754 // SMOV <Wd>, <Vn>.<ts>[<index>] 2755 {0xffe0fc00, 0x0e002c00, SMOV, instArgs{arg_Wd, arg_Vn_arrangement_imm5___B_1__H_2_index__imm5__imm5lt41gt_1__imm5lt42gt_2_1}, nil}, 2756 // SMOV <Xd>, <Vn>.<ts_1>[<index_1>] 2757 {0xffe0fc00, 0x4e002c00, SMOV, instArgs{arg_Xd, arg_Vn_arrangement_imm5___B_1__H_2__S_4_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4_1}, nil}, 2758 // SMULL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<ts>[<index>] 2759 {0xff00f400, 0x0f00a000, SMULL, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil}, 2760 // SMULL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<ts>[<index>] 2761 {0xff00f400, 0x4f00a000, SMULL2, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil}, 2762 // SMULL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb> 2763 {0xff20fc00, 0x0e20c000, SMULL, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 2764 // SMULL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb> 2765 {0xff20fc00, 0x4e20c000, SMULL2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 2766 // SQABS <V><d>, <V><n> 2767 {0xff3ffc00, 0x5e207800, SQABS, instArgs{arg_Vd_22_2__B_0__H_1__S_2__D_3, arg_Vn_22_2__B_0__H_1__S_2__D_3}, nil}, 2768 // SQABS <Vd>.<t>, <Vn>.<t> 2769 {0xbf3ffc00, 0x0e207800, SQABS, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil}, 2770 // SQADD <V><d>, <V><n>, <V><m> 2771 {0xff20fc00, 0x5e200c00, SQADD, instArgs{arg_Vd_22_2__B_0__H_1__S_2__D_3, arg_Vn_22_2__B_0__H_1__S_2__D_3, arg_Vm_22_2__B_0__H_1__S_2__D_3}, nil}, 2772 // SQADD <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2773 {0xbf20fc00, 0x0e200c00, SQADD, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil}, 2774 // SQDMLAL <V><d>, <V><n>, <Vm>.<ts_1>[<index_1>] 2775 {0xff00f400, 0x5f003000, SQDMLAL, instArgs{arg_Vd_22_2__S_1__D_2, arg_Vn_22_2__H_1__S_2, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil}, 2776 // SQDMLAL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<ts>[<index>] 2777 {0xff00f400, 0x0f003000, SQDMLAL, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil}, 2778 // SQDMLAL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<ts>[<index>] 2779 {0xff00f400, 0x4f003000, SQDMLAL2, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil}, 2780 // SQDMLAL <V><d>, <V><n>, <V><m> 2781 {0xff20fc00, 0x5e209000, SQDMLAL, instArgs{arg_Vd_22_2__S_1__D_2, arg_Vn_22_2__H_1__S_2, arg_Vm_22_2__H_1__S_2}, nil}, 2782 // SQDMLAL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb> 2783 {0xff20fc00, 0x0e209000, SQDMLAL, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21}, nil}, 2784 // SQDMLAL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb> 2785 {0xff20fc00, 0x4e209000, SQDMLAL2, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21}, nil}, 2786 // SQDMLSL <V><d>, <V><n>, <Vm>.<ts_1>[<index_1>] 2787 {0xff00f400, 0x5f007000, SQDMLSL, instArgs{arg_Vd_22_2__S_1__D_2, arg_Vn_22_2__H_1__S_2, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil}, 2788 // SQDMLSL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<ts>[<index>] 2789 {0xff00f400, 0x0f007000, SQDMLSL, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil}, 2790 // SQDMLSL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<ts>[<index>] 2791 {0xff00f400, 0x4f007000, SQDMLSL2, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil}, 2792 // SQDMLSL <V><d>, <V><n>, <V><m> 2793 {0xff20fc00, 0x5e20b000, SQDMLSL, instArgs{arg_Vd_22_2__S_1__D_2, arg_Vn_22_2__H_1__S_2, arg_Vm_22_2__H_1__S_2}, nil}, 2794 // SQDMLSL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb> 2795 {0xff20fc00, 0x0e20b000, SQDMLSL, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21}, nil}, 2796 // SQDMLSL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb> 2797 {0xff20fc00, 0x4e20b000, SQDMLSL2, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21}, nil}, 2798 // SQDMULH <V><d>, <V><n>, <Vm>.<ts_1>[<index_1>] 2799 {0xff00f400, 0x5f00c000, SQDMULH, instArgs{arg_Vd_22_2__H_1__S_2, arg_Vn_22_2__H_1__S_2, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil}, 2800 // SQDMULH <Vd>.<t>, <Vn>.<t>, <Vm>.<ts>[<index>] 2801 {0xbf00f400, 0x0f00c000, SQDMULH, instArgs{arg_Vd_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil}, 2802 // SQDMULH <V><d>, <V><n>, <V><m> 2803 {0xff20fc00, 0x5e20b400, SQDMULH, instArgs{arg_Vd_22_2__H_1__S_2, arg_Vn_22_2__H_1__S_2, arg_Vm_22_2__H_1__S_2}, nil}, 2804 // SQDMULH <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2805 {0xbf20fc00, 0x0e20b400, SQDMULH, instArgs{arg_Vd_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21}, nil}, 2806 // SQDMULL <V><d>, <V><n>, <Vm>.<ts_1>[<index_1>] 2807 {0xff00f400, 0x5f00b000, SQDMULL, instArgs{arg_Vd_22_2__S_1__D_2, arg_Vn_22_2__H_1__S_2, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil}, 2808 // SQDMULL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<ts>[<index>] 2809 {0xff00f400, 0x0f00b000, SQDMULL, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil}, 2810 // SQDMULL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<ts>[<index>] 2811 {0xff00f400, 0x4f00b000, SQDMULL2, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil}, 2812 // SQDMULL <V><d>, <V><n>, <V><m> 2813 {0xff20fc00, 0x5e20d000, SQDMULL, instArgs{arg_Vd_22_2__S_1__D_2, arg_Vn_22_2__H_1__S_2, arg_Vm_22_2__H_1__S_2}, nil}, 2814 // SQDMULL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb> 2815 {0xff20fc00, 0x0e20d000, SQDMULL, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21}, nil}, 2816 // SQDMULL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb> 2817 {0xff20fc00, 0x4e20d000, SQDMULL2, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21}, nil}, 2818 // SQNEG <V><d>, <V><n> 2819 {0xff3ffc00, 0x7e207800, SQNEG, instArgs{arg_Vd_22_2__B_0__H_1__S_2__D_3, arg_Vn_22_2__B_0__H_1__S_2__D_3}, nil}, 2820 // SQNEG <Vd>.<t>, <Vn>.<t> 2821 {0xbf3ffc00, 0x2e207800, SQNEG, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil}, 2822 // SQRDMULH <V><d>, <V><n>, <Vm>.<ts_1>[<index_1>] 2823 {0xff00f400, 0x5f00d000, SQRDMULH, instArgs{arg_Vd_22_2__H_1__S_2, arg_Vn_22_2__H_1__S_2, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil}, 2824 // SQRDMULH <Vd>.<t>, <Vn>.<t>, <Vm>.<ts>[<index>] 2825 {0xbf00f400, 0x0f00d000, SQRDMULH, instArgs{arg_Vd_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil}, 2826 // SQRDMULH <V><d>, <V><n>, <V><m> 2827 {0xff20fc00, 0x7e20b400, SQRDMULH, instArgs{arg_Vd_22_2__H_1__S_2, arg_Vn_22_2__H_1__S_2, arg_Vm_22_2__H_1__S_2}, nil}, 2828 // SQRDMULH <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2829 {0xbf20fc00, 0x2e20b400, SQRDMULH, instArgs{arg_Vd_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21}, nil}, 2830 // SQRSHL <V><d>, <V><n>, <V><m> 2831 {0xff20fc00, 0x5e205c00, SQRSHL, instArgs{arg_Vd_22_2__B_0__H_1__S_2__D_3, arg_Vn_22_2__B_0__H_1__S_2__D_3, arg_Vm_22_2__B_0__H_1__S_2__D_3}, nil}, 2832 // SQRSHL <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2833 {0xbf20fc00, 0x0e205c00, SQRSHL, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil}, 2834 // SQRSHRN <V><d>, <V><n>, #<shift> 2835 {0xff80fc00, 0x5f009c00, SQRSHRN, instArgs{arg_Vd_19_4__B_1__H_2__S_4, arg_Vn_19_4__H_1__S_2__D_4, arg_immediate_1_width_immh_immb__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, sqrshrn_asisdshf_n_cond}, 2836 // SQRSHRN <Vd>.<tb>, <Vn>.<ta>, #<shift> 2837 {0xff80fc00, 0x0f009c00, SQRSHRN, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, sqrshrn_asimdshf_n_cond}, 2838 // SQRSHRN2 <Vd>.<tb>, <Vn>.<ta>, #<shift> 2839 {0xff80fc00, 0x4f009c00, SQRSHRN2, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, sqrshrn_asimdshf_n_cond}, 2840 // SQRSHRUN <V><d>, <V><n>, #<shift> 2841 {0xff80fc00, 0x7f008c00, SQRSHRUN, instArgs{arg_Vd_19_4__B_1__H_2__S_4, arg_Vn_19_4__H_1__S_2__D_4, arg_immediate_1_width_immh_immb__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, sqrshrun_asisdshf_n_cond}, 2842 // SQRSHRUN <Vd>.<tb>, <Vn>.<ta>, #<shift> 2843 {0xff80fc00, 0x2f008c00, SQRSHRUN, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, sqrshrun_asimdshf_n_cond}, 2844 // SQRSHRUN2 <Vd>.<tb>, <Vn>.<ta>, #<shift> 2845 {0xff80fc00, 0x6f008c00, SQRSHRUN2, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, sqrshrun_asimdshf_n_cond}, 2846 // SQSHL <V><d>, <V><n>, #<shift> 2847 {0xff80fc00, 0x5f007400, SQSHL, instArgs{arg_Vd_19_4__B_1__H_2__S_4__D_8, arg_Vn_19_4__B_1__H_2__S_4__D_8, arg_immediate_0_width_m1_immh_immb__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8}, sqshl_asisdshf_r_cond}, 2848 // SQSHL <Vd>.<t>, <Vn>.<t>, #<shift> 2849 {0xbf80fc00, 0x0f007400, SQSHL, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8}, sqshl_asimdshf_r_cond}, 2850 // SQSHL <V><d>, <V><n>, <V><m> 2851 {0xff20fc00, 0x5e204c00, SQSHL, instArgs{arg_Vd_22_2__B_0__H_1__S_2__D_3, arg_Vn_22_2__B_0__H_1__S_2__D_3, arg_Vm_22_2__B_0__H_1__S_2__D_3}, nil}, 2852 // SQSHL <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2853 {0xbf20fc00, 0x0e204c00, SQSHL, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil}, 2854 // SQSHLU <V><d>, <V><n>, #<shift> 2855 {0xff80fc00, 0x7f006400, SQSHLU, instArgs{arg_Vd_19_4__B_1__H_2__S_4__D_8, arg_Vn_19_4__B_1__H_2__S_4__D_8, arg_immediate_0_width_m1_immh_immb__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8}, sqshlu_asisdshf_r_cond}, 2856 // SQSHLU <Vd>.<t>, <Vn>.<t>, #<shift> 2857 {0xbf80fc00, 0x2f006400, SQSHLU, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8}, sqshlu_asimdshf_r_cond}, 2858 // SQSHRN <V><d>, <V><n>, #<shift> 2859 {0xff80fc00, 0x5f009400, SQSHRN, instArgs{arg_Vd_19_4__B_1__H_2__S_4, arg_Vn_19_4__H_1__S_2__D_4, arg_immediate_1_width_immh_immb__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, sqshrn_asisdshf_n_cond}, 2860 // SQSHRN <Vd>.<tb>, <Vn>.<ta>, #<shift> 2861 {0xff80fc00, 0x0f009400, SQSHRN, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, sqshrn_asimdshf_n_cond}, 2862 // SQSHRN2 <Vd>.<tb>, <Vn>.<ta>, #<shift> 2863 {0xff80fc00, 0x4f009400, SQSHRN2, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, sqshrn_asimdshf_n_cond}, 2864 // SQSHRUN <V><d>, <V><n>, #<shift> 2865 {0xff80fc00, 0x7f008400, SQSHRUN, instArgs{arg_Vd_19_4__B_1__H_2__S_4, arg_Vn_19_4__H_1__S_2__D_4, arg_immediate_1_width_immh_immb__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, sqshrun_asisdshf_n_cond}, 2866 // SQSHRUN <Vd>.<tb>, <Vn>.<ta>, #<shift> 2867 {0xff80fc00, 0x2f008400, SQSHRUN, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, sqshrun_asimdshf_n_cond}, 2868 // SQSHRUN2 <Vd>.<tb>, <Vn>.<ta>, #<shift> 2869 {0xff80fc00, 0x6f008400, SQSHRUN2, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, sqshrun_asimdshf_n_cond}, 2870 // SQSUB <V><d>, <V><n>, <V><m> 2871 {0xff20fc00, 0x5e202c00, SQSUB, instArgs{arg_Vd_22_2__B_0__H_1__S_2__D_3, arg_Vn_22_2__B_0__H_1__S_2__D_3, arg_Vm_22_2__B_0__H_1__S_2__D_3}, nil}, 2872 // SQSUB <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2873 {0xbf20fc00, 0x0e202c00, SQSUB, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil}, 2874 // SQXTN <V><d>, <V><n> 2875 {0xff3ffc00, 0x5e214800, SQXTN, instArgs{arg_Vd_22_2__B_0__H_1__S_2, arg_Vn_22_2__H_0__S_1__D_2}, nil}, 2876 // SQXTN <Vd>.<tb>, <Vn>.<ta> 2877 {0xff3ffc00, 0x0e214800, SQXTN, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size___8H_0__4S_1__2D_2}, nil}, 2878 // SQXTN2 <Vd>.<tb>, <Vn>.<ta> 2879 {0xff3ffc00, 0x4e214800, SQXTN2, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size___8H_0__4S_1__2D_2}, nil}, 2880 // SQXTUN <V><d>, <V><n> 2881 {0xff3ffc00, 0x7e212800, SQXTUN, instArgs{arg_Vd_22_2__B_0__H_1__S_2, arg_Vn_22_2__H_0__S_1__D_2}, nil}, 2882 // SQXTUN <Vd>.<tb>, <Vn>.<ta> 2883 {0xff3ffc00, 0x2e212800, SQXTUN, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size___8H_0__4S_1__2D_2}, nil}, 2884 // SQXTUN2 <Vd>.<tb>, <Vn>.<ta> 2885 {0xff3ffc00, 0x6e212800, SQXTUN2, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size___8H_0__4S_1__2D_2}, nil}, 2886 // SRHADD <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2887 {0xbf20fc00, 0x0e201400, SRHADD, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 2888 // SRI <V><d>, <V><n>, #<shift> 2889 {0xff80fc00, 0x7f004400, SRI, instArgs{arg_Vd_19_4__D_8, arg_Vn_19_4__D_8, arg_immediate_1_64_immh_immb__128UIntimmhimmb_8}, sri_asisdshf_r_cond}, 2890 // SRI <Vd>.<t>, <Vn>.<t>, #<shift> 2891 {0xbf80fc00, 0x2f004400, SRI, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4__128UIntimmhimmb_8}, sri_asimdshf_r_cond}, 2892 // SRSHL <V><d>, <V><n>, <V><m> 2893 {0xff20fc00, 0x5e205400, SRSHL, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3, arg_Vm_22_2__D_3}, nil}, 2894 // SRSHL <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2895 {0xbf20fc00, 0x0e205400, SRSHL, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil}, 2896 // SRSHR <V><d>, <V><n>, #<shift> 2897 {0xff80fc00, 0x5f002400, SRSHR, instArgs{arg_Vd_19_4__D_8, arg_Vn_19_4__D_8, arg_immediate_1_64_immh_immb__128UIntimmhimmb_8}, srshr_asisdshf_r_cond}, 2898 // SRSHR <Vd>.<t>, <Vn>.<t>, #<shift> 2899 {0xbf80fc00, 0x0f002400, SRSHR, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4__128UIntimmhimmb_8}, srshr_asimdshf_r_cond}, 2900 // SRSRA <V><d>, <V><n>, #<shift> 2901 {0xff80fc00, 0x5f003400, SRSRA, instArgs{arg_Vd_19_4__D_8, arg_Vn_19_4__D_8, arg_immediate_1_64_immh_immb__128UIntimmhimmb_8}, srsra_asisdshf_r_cond}, 2902 // SRSRA <Vd>.<t>, <Vn>.<t>, #<shift> 2903 {0xbf80fc00, 0x0f003400, SRSRA, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4__128UIntimmhimmb_8}, srsra_asimdshf_r_cond}, 2904 // SSHL <V><d>, <V><n>, <V><m> 2905 {0xff20fc00, 0x5e204400, SSHL, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3, arg_Vm_22_2__D_3}, nil}, 2906 // SSHL <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 2907 {0xbf20fc00, 0x0e204400, SSHL, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil}, 2908 // SXTL <Vd>.<ta>, <Vn>.<tb> 2909 {0xff87fc00, 0x0f00a400, SXTL, instArgs{arg_Vd_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41}, sxtl_sshll_asimdshf_l_cond}, 2910 // SXTL2 <Vd>.<ta>, <Vn>.<tb> 2911 {0xff87fc00, 0x4f00a400, SXTL2, instArgs{arg_Vd_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41}, sxtl_sshll_asimdshf_l_cond}, 2912 // SSHLL <Vd>.<ta>, <Vn>.<tb>, #<shift> 2913 {0xff80fc00, 0x0f00a400, SSHLL, instArgs{arg_Vd_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4}, sshll_asimdshf_l_cond}, 2914 // SSHLL2 <Vd>.<ta>, <Vn>.<tb>, #<shift> 2915 {0xff80fc00, 0x4f00a400, SSHLL2, instArgs{arg_Vd_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4}, sshll_asimdshf_l_cond}, 2916 // SSHR <V><d>, <V><n>, #<shift> 2917 {0xff80fc00, 0x5f000400, SSHR, instArgs{arg_Vd_19_4__D_8, arg_Vn_19_4__D_8, arg_immediate_1_64_immh_immb__128UIntimmhimmb_8}, sshr_asisdshf_r_cond}, 2918 // SSHR <Vd>.<t>, <Vn>.<t>, #<shift> 2919 {0xbf80fc00, 0x0f000400, SSHR, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4__128UIntimmhimmb_8}, sshr_asimdshf_r_cond}, 2920 // SSRA <V><d>, <V><n>, #<shift> 2921 {0xff80fc00, 0x5f001400, SSRA, instArgs{arg_Vd_19_4__D_8, arg_Vn_19_4__D_8, arg_immediate_1_64_immh_immb__128UIntimmhimmb_8}, ssra_asisdshf_r_cond}, 2922 // SSRA <Vd>.<t>, <Vn>.<t>, #<shift> 2923 {0xbf80fc00, 0x0f001400, SSRA, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4__128UIntimmhimmb_8}, ssra_asimdshf_r_cond}, 2924 // SSUBL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb> 2925 {0xff20fc00, 0x0e202000, SSUBL, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 2926 // SSUBL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb> 2927 {0xff20fc00, 0x4e202000, SSUBL2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 2928 // SSUBW <Vd>.<ta>, <Vn>.<ta>, <Vm>.<tb> 2929 {0xff20fc00, 0x0e203000, SSUBW, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size___8H_0__4S_1__2D_2, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 2930 // SSUBW2 <Vd>.<ta>, <Vn>.<ta>, <Vm>.<tb> 2931 {0xff20fc00, 0x4e203000, SSUBW2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size___8H_0__4S_1__2D_2, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 2932 // ST1 <Vt>.<t>, [<Xn|SP>] 2933 {0xbffff000, 0x0c007000, ST1, instArgs{arg_Vt_1_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_offset}, nil}, 2934 // ST1 <Vt>.<t>, [<Xn|SP>] 2935 {0xbffff000, 0x0c00a000, ST1, instArgs{arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_offset}, nil}, 2936 // ST1 <Vt>.<t>, [<Xn|SP>] 2937 {0xbffff000, 0x0c006000, ST1, instArgs{arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_offset}, nil}, 2938 // ST1 <Vt>.<t>, [<Xn|SP>] 2939 {0xbffff000, 0x0c002000, ST1, instArgs{arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_offset}, nil}, 2940 // ST1 <Vt>.<t>, [<Xn|SP>], #<imm> 2941 {0xbffff000, 0x0c9f7000, ST1, instArgs{arg_Vt_1_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Q__8_0__16_1}, nil}, 2942 // ST1 <Vt>.<t>, [<Xn|SP>], #<Xm> 2943 {0xbfe0f000, 0x0c807000, ST1, instArgs{arg_Vt_1_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Xm}, nil}, 2944 // ST1 <Vt>.<t>, [<Xn|SP>], #<imm_1> 2945 {0xbffff000, 0x0c9fa000, ST1, instArgs{arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Q__16_0__32_1}, nil}, 2946 // ST1 <Vt>.<t>, [<Xn|SP>], #<Xm> 2947 {0xbfe0f000, 0x0c80a000, ST1, instArgs{arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Xm}, nil}, 2948 // ST1 <Vt>.<t>, [<Xn|SP>], #<imm_2> 2949 {0xbffff000, 0x0c9f6000, ST1, instArgs{arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Q__24_0__48_1}, nil}, 2950 // ST1 <Vt>.<t>, [<Xn|SP>], #<Xm> 2951 {0xbfe0f000, 0x0c806000, ST1, instArgs{arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Xm}, nil}, 2952 // ST1 <Vt>.<t>, [<Xn|SP>], #<imm_3> 2953 {0xbffff000, 0x0c9f2000, ST1, instArgs{arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Q__32_0__64_1}, nil}, 2954 // ST1 <Vt>.<t>, [<Xn|SP>], #<Xm> 2955 {0xbfe0f000, 0x0c802000, ST1, instArgs{arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Xm}, nil}, 2956 // ST1 <Vt>.B[<index>], [<Xn|SP>] 2957 {0xbfffe000, 0x0d000000, ST1, instArgs{arg_Vt_1_arrangement_B_index__Q_S_size_1, arg_Xns_mem_offset}, nil}, 2958 // ST1 <Vt>.H[<index_2>], [<Xn|SP>] 2959 {0xbfffe400, 0x0d004000, ST1, instArgs{arg_Vt_1_arrangement_H_index__Q_S_size_1, arg_Xns_mem_offset}, nil}, 2960 // ST1 <Vt>.S[<index_3>], [<Xn|SP>] 2961 {0xbfffec00, 0x0d008000, ST1, instArgs{arg_Vt_1_arrangement_S_index__Q_S_1, arg_Xns_mem_offset}, nil}, 2962 // ST1 <Vt>.D[<index_1>], [<Xn|SP>] 2963 {0xbffffc00, 0x0d008400, ST1, instArgs{arg_Vt_1_arrangement_D_index__Q_1, arg_Xns_mem_offset}, nil}, 2964 // ST1 <Vt>.B[<index>], [<Xn|SP>], #1 2965 {0xbfffe000, 0x0d9f0000, ST1, instArgs{arg_Vt_1_arrangement_B_index__Q_S_size_1, arg_Xns_mem_post_fixedimm_1}, nil}, 2966 // ST1 <Vt>.B[<index>], [<Xn|SP>], #<Xm> 2967 {0xbfe0e000, 0x0d800000, ST1, instArgs{arg_Vt_1_arrangement_B_index__Q_S_size_1, arg_Xns_mem_post_Xm}, nil}, 2968 // ST1 <Vt>.H[<index_2>], [<Xn|SP>], #2 2969 {0xbfffe400, 0x0d9f4000, ST1, instArgs{arg_Vt_1_arrangement_H_index__Q_S_size_1, arg_Xns_mem_post_fixedimm_2}, nil}, 2970 // ST1 <Vt>.H[<index_2>], [<Xn|SP>], #<Xm> 2971 {0xbfe0e400, 0x0d804000, ST1, instArgs{arg_Vt_1_arrangement_H_index__Q_S_size_1, arg_Xns_mem_post_Xm}, nil}, 2972 // ST1 <Vt>.S[<index_3>], [<Xn|SP>], #4 2973 {0xbfffec00, 0x0d9f8000, ST1, instArgs{arg_Vt_1_arrangement_S_index__Q_S_1, arg_Xns_mem_post_fixedimm_4}, nil}, 2974 // ST1 <Vt>.S[<index_3>], [<Xn|SP>], #<Xm> 2975 {0xbfe0ec00, 0x0d808000, ST1, instArgs{arg_Vt_1_arrangement_S_index__Q_S_1, arg_Xns_mem_post_Xm}, nil}, 2976 // ST1 <Vt>.D[<index_1>], [<Xn|SP>], #8 2977 {0xbffffc00, 0x0d9f8400, ST1, instArgs{arg_Vt_1_arrangement_D_index__Q_1, arg_Xns_mem_post_fixedimm_8}, nil}, 2978 // ST1 <Vt>.D[<index_1>], [<Xn|SP>], #<Xm> 2979 {0xbfe0fc00, 0x0d808400, ST1, instArgs{arg_Vt_1_arrangement_D_index__Q_1, arg_Xns_mem_post_Xm}, nil}, 2980 // ST2 <Vt>.<t>, [<Xn|SP>] 2981 {0xbffff000, 0x0c008000, ST2, instArgs{arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Xns_mem_offset}, nil}, 2982 // ST2 <Vt>.<t>, [<Xn|SP>], #<imm> 2983 {0xbffff000, 0x0c9f8000, ST2, instArgs{arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Xns_mem_post_Q__16_0__32_1}, nil}, 2984 // ST2 <Vt>.<t>, [<Xn|SP>], #<Xm> 2985 {0xbfe0f000, 0x0c808000, ST2, instArgs{arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Xns_mem_post_Xm}, nil}, 2986 // ST2 <Vt>.B[<index>], [<Xn|SP>] 2987 {0xbfffe000, 0x0d200000, ST2, instArgs{arg_Vt_2_arrangement_B_index__Q_S_size_1, arg_Xns_mem_offset}, nil}, 2988 // ST2 <Vt>.H[<index_2>], [<Xn|SP>] 2989 {0xbfffe400, 0x0d204000, ST2, instArgs{arg_Vt_2_arrangement_H_index__Q_S_size_1, arg_Xns_mem_offset}, nil}, 2990 // ST2 <Vt>.S[<index_3>], [<Xn|SP>] 2991 {0xbfffec00, 0x0d208000, ST2, instArgs{arg_Vt_2_arrangement_S_index__Q_S_1, arg_Xns_mem_offset}, nil}, 2992 // ST2 <Vt>.D[<index_1>], [<Xn|SP>] 2993 {0xbffffc00, 0x0d208400, ST2, instArgs{arg_Vt_2_arrangement_D_index__Q_1, arg_Xns_mem_offset}, nil}, 2994 // ST2 <Vt>.B[<index>], [<Xn|SP>], #2 2995 {0xbfffe000, 0x0dbf0000, ST2, instArgs{arg_Vt_2_arrangement_B_index__Q_S_size_1, arg_Xns_mem_post_fixedimm_2}, nil}, 2996 // ST2 <Vt>.B[<index>], [<Xn|SP>], #<Xm> 2997 {0xbfe0e000, 0x0da00000, ST2, instArgs{arg_Vt_2_arrangement_B_index__Q_S_size_1, arg_Xns_mem_post_Xm}, nil}, 2998 // ST2 <Vt>.H[<index_2>], [<Xn|SP>], #4 2999 {0xbfffe400, 0x0dbf4000, ST2, instArgs{arg_Vt_2_arrangement_H_index__Q_S_size_1, arg_Xns_mem_post_fixedimm_4}, nil}, 3000 // ST2 <Vt>.H[<index_2>], [<Xn|SP>], #<Xm> 3001 {0xbfe0e400, 0x0da04000, ST2, instArgs{arg_Vt_2_arrangement_H_index__Q_S_size_1, arg_Xns_mem_post_Xm}, nil}, 3002 // ST2 <Vt>.S[<index_3>], [<Xn|SP>], #8 3003 {0xbfffec00, 0x0dbf8000, ST2, instArgs{arg_Vt_2_arrangement_S_index__Q_S_1, arg_Xns_mem_post_fixedimm_8}, nil}, 3004 // ST2 <Vt>.S[<index_3>], [<Xn|SP>], #<Xm> 3005 {0xbfe0ec00, 0x0da08000, ST2, instArgs{arg_Vt_2_arrangement_S_index__Q_S_1, arg_Xns_mem_post_Xm}, nil}, 3006 // ST2 <Vt>.D[<index_1>], [<Xn|SP>], #16 3007 {0xbffffc00, 0x0dbf8400, ST2, instArgs{arg_Vt_2_arrangement_D_index__Q_1, arg_Xns_mem_post_fixedimm_16}, nil}, 3008 // ST2 <Vt>.D[<index_1>], [<Xn|SP>], #<Xm> 3009 {0xbfe0fc00, 0x0da08400, ST2, instArgs{arg_Vt_2_arrangement_D_index__Q_1, arg_Xns_mem_post_Xm}, nil}, 3010 // ST3 <Vt>.<t>, [<Xn|SP>] 3011 {0xbffff000, 0x0c004000, ST3, instArgs{arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Xns_mem_offset}, nil}, 3012 // ST3 <Vt>.<t>, [<Xn|SP>], #<imm> 3013 {0xbffff000, 0x0c9f4000, ST3, instArgs{arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Xns_mem_post_Q__24_0__48_1}, nil}, 3014 // ST3 <Vt>.<t>, [<Xn|SP>], #<Xm> 3015 {0xbfe0f000, 0x0c804000, ST3, instArgs{arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Xns_mem_post_Xm}, nil}, 3016 // ST3 <Vt>.B[<index>], [<Xn|SP>] 3017 {0xbfffe000, 0x0d002000, ST3, instArgs{arg_Vt_3_arrangement_B_index__Q_S_size_1, arg_Xns_mem_offset}, nil}, 3018 // ST3 <Vt>.H[<index_2>], [<Xn|SP>] 3019 {0xbfffe400, 0x0d006000, ST3, instArgs{arg_Vt_3_arrangement_H_index__Q_S_size_1, arg_Xns_mem_offset}, nil}, 3020 // ST3 <Vt>.S[<index_3>], [<Xn|SP>] 3021 {0xbfffec00, 0x0d00a000, ST3, instArgs{arg_Vt_3_arrangement_S_index__Q_S_1, arg_Xns_mem_offset}, nil}, 3022 // ST3 <Vt>.D[<index_1>], [<Xn|SP>] 3023 {0xbffffc00, 0x0d00a400, ST3, instArgs{arg_Vt_3_arrangement_D_index__Q_1, arg_Xns_mem_offset}, nil}, 3024 // ST3 <Vt>.B[<index>], [<Xn|SP>], #3 3025 {0xbfffe000, 0x0d9f2000, ST3, instArgs{arg_Vt_3_arrangement_B_index__Q_S_size_1, arg_Xns_mem_post_fixedimm_3}, nil}, 3026 // ST3 <Vt>.B[<index>], [<Xn|SP>], #<Xm> 3027 {0xbfe0e000, 0x0d802000, ST3, instArgs{arg_Vt_3_arrangement_B_index__Q_S_size_1, arg_Xns_mem_post_Xm}, nil}, 3028 // ST3 <Vt>.H[<index_2>], [<Xn|SP>], #6 3029 {0xbfffe400, 0x0d9f6000, ST3, instArgs{arg_Vt_3_arrangement_H_index__Q_S_size_1, arg_Xns_mem_post_fixedimm_6}, nil}, 3030 // ST3 <Vt>.H[<index_2>], [<Xn|SP>], #<Xm> 3031 {0xbfe0e400, 0x0d806000, ST3, instArgs{arg_Vt_3_arrangement_H_index__Q_S_size_1, arg_Xns_mem_post_Xm}, nil}, 3032 // ST3 <Vt>.S[<index_3>], [<Xn|SP>], #12 3033 {0xbfffec00, 0x0d9fa000, ST3, instArgs{arg_Vt_3_arrangement_S_index__Q_S_1, arg_Xns_mem_post_fixedimm_12}, nil}, 3034 // ST3 <Vt>.S[<index_3>], [<Xn|SP>], #<Xm> 3035 {0xbfe0ec00, 0x0d80a000, ST3, instArgs{arg_Vt_3_arrangement_S_index__Q_S_1, arg_Xns_mem_post_Xm}, nil}, 3036 // ST3 <Vt>.D[<index_1>], [<Xn|SP>], #24 3037 {0xbffffc00, 0x0d9fa400, ST3, instArgs{arg_Vt_3_arrangement_D_index__Q_1, arg_Xns_mem_post_fixedimm_24}, nil}, 3038 // ST3 <Vt>.D[<index_1>], [<Xn|SP>], #<Xm> 3039 {0xbfe0fc00, 0x0d80a400, ST3, instArgs{arg_Vt_3_arrangement_D_index__Q_1, arg_Xns_mem_post_Xm}, nil}, 3040 // ST4 <Vt>.<t>, [<Xn|SP>] 3041 {0xbffff000, 0x0c000000, ST4, instArgs{arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Xns_mem_offset}, nil}, 3042 // ST4 <Vt>.<t>, [<Xn|SP>], #<imm> 3043 {0xbffff000, 0x0c9f0000, ST4, instArgs{arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Xns_mem_post_Q__32_0__64_1}, nil}, 3044 // ST4 <Vt>.<t>, [<Xn|SP>], #<Xm> 3045 {0xbfe0f000, 0x0c800000, ST4, instArgs{arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Xns_mem_post_Xm}, nil}, 3046 // ST4 <Vt>.B[<index>], [<Xn|SP>] 3047 {0xbfffe000, 0x0d202000, ST4, instArgs{arg_Vt_4_arrangement_B_index__Q_S_size_1, arg_Xns_mem_offset}, nil}, 3048 // ST4 <Vt>.H[<index_2>], [<Xn|SP>] 3049 {0xbfffe400, 0x0d206000, ST4, instArgs{arg_Vt_4_arrangement_H_index__Q_S_size_1, arg_Xns_mem_offset}, nil}, 3050 // ST4 <Vt>.S[<index_3>], [<Xn|SP>] 3051 {0xbfffec00, 0x0d20a000, ST4, instArgs{arg_Vt_4_arrangement_S_index__Q_S_1, arg_Xns_mem_offset}, nil}, 3052 // ST4 <Vt>.D[<index_1>], [<Xn|SP>] 3053 {0xbffffc00, 0x0d20a400, ST4, instArgs{arg_Vt_4_arrangement_D_index__Q_1, arg_Xns_mem_offset}, nil}, 3054 // ST4 <Vt>.B[<index>], [<Xn|SP>], #4 3055 {0xbfffe000, 0x0dbf2000, ST4, instArgs{arg_Vt_4_arrangement_B_index__Q_S_size_1, arg_Xns_mem_post_fixedimm_4}, nil}, 3056 // ST4 <Vt>.B[<index>], [<Xn|SP>], #<Xm> 3057 {0xbfe0e000, 0x0da02000, ST4, instArgs{arg_Vt_4_arrangement_B_index__Q_S_size_1, arg_Xns_mem_post_Xm}, nil}, 3058 // ST4 <Vt>.H[<index_2>], [<Xn|SP>], #8 3059 {0xbfffe400, 0x0dbf6000, ST4, instArgs{arg_Vt_4_arrangement_H_index__Q_S_size_1, arg_Xns_mem_post_fixedimm_8}, nil}, 3060 // ST4 <Vt>.H[<index_2>], [<Xn|SP>], #<Xm> 3061 {0xbfe0e400, 0x0da06000, ST4, instArgs{arg_Vt_4_arrangement_H_index__Q_S_size_1, arg_Xns_mem_post_Xm}, nil}, 3062 // ST4 <Vt>.S[<index_3>], [<Xn|SP>], #16 3063 {0xbfffec00, 0x0dbfa000, ST4, instArgs{arg_Vt_4_arrangement_S_index__Q_S_1, arg_Xns_mem_post_fixedimm_16}, nil}, 3064 // ST4 <Vt>.S[<index_3>], [<Xn|SP>], #<Xm> 3065 {0xbfe0ec00, 0x0da0a000, ST4, instArgs{arg_Vt_4_arrangement_S_index__Q_S_1, arg_Xns_mem_post_Xm}, nil}, 3066 // ST4 <Vt>.D[<index_1>], [<Xn|SP>], #32 3067 {0xbffffc00, 0x0dbfa400, ST4, instArgs{arg_Vt_4_arrangement_D_index__Q_1, arg_Xns_mem_post_fixedimm_32}, nil}, 3068 // ST4 <Vt>.D[<index_1>], [<Xn|SP>], #<Xm> 3069 {0xbfe0fc00, 0x0da0a400, ST4, instArgs{arg_Vt_4_arrangement_D_index__Q_1, arg_Xns_mem_post_Xm}, nil}, 3070 // STNP <St>, <St2>, [<Xn|SP>{, #<imm_2>}] 3071 {0xffc00000, 0x2c000000, STNP, instArgs{arg_St, arg_St2, arg_Xns_mem_optional_imm7_4_signed}, nil}, 3072 // STNP <Dt>, <Dt2>, [<Xn|SP>{, #<imm>}] 3073 {0xffc00000, 0x6c000000, STNP, instArgs{arg_Dt, arg_Dt2, arg_Xns_mem_optional_imm7_8_signed}, nil}, 3074 // STNP <Qt>, <Qt2>, [<Xn|SP>{, #<imm_1>}] 3075 {0xffc00000, 0xac000000, STNP, instArgs{arg_Qt, arg_Qt2, arg_Xns_mem_optional_imm7_16_signed}, nil}, 3076 // STP <St>, <St2>, [<Xn|SP>], #<imm_5> 3077 {0xffc00000, 0x2c800000, STP, instArgs{arg_St, arg_St2, arg_Xns_mem_post_imm7_4_signed}, nil}, 3078 // STP <Dt>, <Dt2>, [<Xn|SP>], #<imm_1> 3079 {0xffc00000, 0x6c800000, STP, instArgs{arg_Dt, arg_Dt2, arg_Xns_mem_post_imm7_8_signed}, nil}, 3080 // STP <Qt>, <Qt2>, [<Xn|SP>], #<imm_3> 3081 {0xffc00000, 0xac800000, STP, instArgs{arg_Qt, arg_Qt2, arg_Xns_mem_post_imm7_16_signed}, nil}, 3082 // STP <St>, <St2>, [<Xn|SP>{, #<imm_5>}]! 3083 {0xffc00000, 0x2d800000, STP, instArgs{arg_St, arg_St2, arg_Xns_mem_wb_imm7_4_signed}, nil}, 3084 // STP <Dt>, <Dt2>, [<Xn|SP>{, #<imm_1>}]! 3085 {0xffc00000, 0x6d800000, STP, instArgs{arg_Dt, arg_Dt2, arg_Xns_mem_wb_imm7_8_signed}, nil}, 3086 // STP <Qt>, <Qt2>, [<Xn|SP>{, #<imm_3>}]! 3087 {0xffc00000, 0xad800000, STP, instArgs{arg_Qt, arg_Qt2, arg_Xns_mem_wb_imm7_16_signed}, nil}, 3088 // STP <St>, <St2>, [<Xn|SP>{, #<imm_4>}] 3089 {0xffc00000, 0x2d000000, STP, instArgs{arg_St, arg_St2, arg_Xns_mem_optional_imm7_4_signed}, nil}, 3090 // STP <Dt>, <Dt2>, [<Xn|SP>{, #<imm>}] 3091 {0xffc00000, 0x6d000000, STP, instArgs{arg_Dt, arg_Dt2, arg_Xns_mem_optional_imm7_8_signed}, nil}, 3092 // STP <Qt>, <Qt2>, [<Xn|SP>{, #<imm_2>}] 3093 {0xffc00000, 0xad000000, STP, instArgs{arg_Qt, arg_Qt2, arg_Xns_mem_optional_imm7_16_signed}, nil}, 3094 // STR <Bt>, [<Xn|SP>], #<simm> 3095 {0xffe00c00, 0x3c000400, STR, instArgs{arg_Bt, arg_Xns_mem_post_imm9_1_signed}, nil}, 3096 // STR <Ht>, [<Xn|SP>], #<simm> 3097 {0xffe00c00, 0x7c000400, STR, instArgs{arg_Ht, arg_Xns_mem_post_imm9_1_signed}, nil}, 3098 // STR <St>, [<Xn|SP>], #<simm> 3099 {0xffe00c00, 0xbc000400, STR, instArgs{arg_St, arg_Xns_mem_post_imm9_1_signed}, nil}, 3100 // STR <Dt>, [<Xn|SP>], #<simm> 3101 {0xffe00c00, 0xfc000400, STR, instArgs{arg_Dt, arg_Xns_mem_post_imm9_1_signed}, nil}, 3102 // STR <Qt>, [<Xn|SP>], #<simm> 3103 {0xffe00c00, 0x3c800400, STR, instArgs{arg_Qt, arg_Xns_mem_post_imm9_1_signed}, nil}, 3104 // STR <Bt>, [<Xn|SP>{, #<simm>}]! 3105 {0xffe00c00, 0x3c000c00, STR, instArgs{arg_Bt, arg_Xns_mem_wb_imm9_1_signed}, nil}, 3106 // STR <Ht>, [<Xn|SP>{, #<simm>}]! 3107 {0xffe00c00, 0x7c000c00, STR, instArgs{arg_Ht, arg_Xns_mem_wb_imm9_1_signed}, nil}, 3108 // STR <St>, [<Xn|SP>{, #<simm>}]! 3109 {0xffe00c00, 0xbc000c00, STR, instArgs{arg_St, arg_Xns_mem_wb_imm9_1_signed}, nil}, 3110 // STR <Dt>, [<Xn|SP>{, #<simm>}]! 3111 {0xffe00c00, 0xfc000c00, STR, instArgs{arg_Dt, arg_Xns_mem_wb_imm9_1_signed}, nil}, 3112 // STR <Qt>, [<Xn|SP>{, #<simm>}]! 3113 {0xffe00c00, 0x3c800c00, STR, instArgs{arg_Qt, arg_Xns_mem_wb_imm9_1_signed}, nil}, 3114 // STR <Bt>, [<Xn|SP>{, #<pimm>}] 3115 {0xffc00000, 0x3d000000, STR, instArgs{arg_Bt, arg_Xns_mem_optional_imm12_1_unsigned}, nil}, 3116 // STR <Ht>, [<Xn|SP>{, #<pimm_2>}] 3117 {0xffc00000, 0x7d000000, STR, instArgs{arg_Ht, arg_Xns_mem_optional_imm12_2_unsigned}, nil}, 3118 // STR <St>, [<Xn|SP>{, #<pimm_4>}] 3119 {0xffc00000, 0xbd000000, STR, instArgs{arg_St, arg_Xns_mem_optional_imm12_4_unsigned}, nil}, 3120 // STR <Dt>, [<Xn|SP>{, #<pimm_1>}] 3121 {0xffc00000, 0xfd000000, STR, instArgs{arg_Dt, arg_Xns_mem_optional_imm12_8_unsigned}, nil}, 3122 // STR <Qt>, [<Xn|SP>{, #<pimm_3>}] 3123 {0xffc00000, 0x3d800000, STR, instArgs{arg_Qt, arg_Xns_mem_optional_imm12_16_unsigned}, nil}, 3124 // STR <Bt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}] 3125 {0xffe00c00, 0x3c200800, STR, instArgs{arg_Bt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__absent_0__0_1}, nil}, 3126 // STR <Ht>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}] 3127 {0xffe00c00, 0x7c200800, STR, instArgs{arg_Ht, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__1_1}, nil}, 3128 // STR <St>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}] 3129 {0xffe00c00, 0xbc200800, STR, instArgs{arg_St, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__2_1}, nil}, 3130 // STR <Dt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}] 3131 {0xffe00c00, 0xfc200800, STR, instArgs{arg_Dt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__3_1}, nil}, 3132 // STR <Qt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}] 3133 {0xffe00c00, 0x3ca00800, STR, instArgs{arg_Qt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__4_1}, nil}, 3134 // STUR <Bt>, [<Xn|SP>{, #<simm>}] 3135 {0xffe00c00, 0x3c000000, STUR, instArgs{arg_Bt, arg_Xns_mem_optional_imm9_1_signed}, nil}, 3136 // STUR <Ht>, [<Xn|SP>{, #<simm>}] 3137 {0xffe00c00, 0x7c000000, STUR, instArgs{arg_Ht, arg_Xns_mem_optional_imm9_1_signed}, nil}, 3138 // STUR <St>, [<Xn|SP>{, #<simm>}] 3139 {0xffe00c00, 0xbc000000, STUR, instArgs{arg_St, arg_Xns_mem_optional_imm9_1_signed}, nil}, 3140 // STUR <Dt>, [<Xn|SP>{, #<simm>}] 3141 {0xffe00c00, 0xfc000000, STUR, instArgs{arg_Dt, arg_Xns_mem_optional_imm9_1_signed}, nil}, 3142 // STUR <Qt>, [<Xn|SP>{, #<simm>}] 3143 {0xffe00c00, 0x3c800000, STUR, instArgs{arg_Qt, arg_Xns_mem_optional_imm9_1_signed}, nil}, 3144 // SUB <V><d>, <V><n>, <V><m> 3145 {0xff20fc00, 0x7e208400, SUB, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3, arg_Vm_22_2__D_3}, nil}, 3146 // SUB <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 3147 {0xbf20fc00, 0x2e208400, SUB, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil}, 3148 // SUBHN <Vd>.<tb>, <Vn>.<ta>, <Vm>.<ta> 3149 {0xff20fc00, 0x0e206000, SUBHN, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size___8H_0__4S_1__2D_2, arg_Vm_arrangement_size___8H_0__4S_1__2D_2}, nil}, 3150 // SUBHN2 <Vd>.<tb>, <Vn>.<ta>, <Vm>.<ta> 3151 {0xff20fc00, 0x4e206000, SUBHN2, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size___8H_0__4S_1__2D_2, arg_Vm_arrangement_size___8H_0__4S_1__2D_2}, nil}, 3152 // SUQADD <V><d>, <V><n> 3153 {0xff3ffc00, 0x5e203800, SUQADD, instArgs{arg_Vd_22_2__B_0__H_1__S_2__D_3, arg_Vn_22_2__B_0__H_1__S_2__D_3}, nil}, 3154 // SUQADD <Vd>.<t>, <Vn>.<t> 3155 {0xbf3ffc00, 0x0e203800, SUQADD, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil}, 3156 // TBL <Vd>.<ta>, <Vn>.16B, <Vm>.<ta> 3157 {0xbfe0fc00, 0x0e002000, TBL, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_2_arrangement_16B, arg_Vm_arrangement_Q___8B_0__16B_1}, nil}, 3158 // TBL <Vd>.<ta>, <Vn>.16B, <Vm>.<ta> 3159 {0xbfe0fc00, 0x0e004000, TBL, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_3_arrangement_16B, arg_Vm_arrangement_Q___8B_0__16B_1}, nil}, 3160 // TBL <Vd>.<ta>, <Vn>.16B, <Vm>.<ta> 3161 {0xbfe0fc00, 0x0e006000, TBL, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_4_arrangement_16B, arg_Vm_arrangement_Q___8B_0__16B_1}, nil}, 3162 // TBL <Vd>.<ta>, <Vn>.16B, <Vm>.<ta> 3163 {0xbfe0fc00, 0x0e000000, TBL, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_1_arrangement_16B, arg_Vm_arrangement_Q___8B_0__16B_1}, nil}, 3164 // TBX <Vd>.<ta>, <Vn>.16B, <Vm>.<ta> 3165 {0xbfe0fc00, 0x0e003000, TBX, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_2_arrangement_16B, arg_Vm_arrangement_Q___8B_0__16B_1}, nil}, 3166 // TBX <Vd>.<ta>, <Vn>.16B, <Vm>.<ta> 3167 {0xbfe0fc00, 0x0e005000, TBX, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_3_arrangement_16B, arg_Vm_arrangement_Q___8B_0__16B_1}, nil}, 3168 // TBX <Vd>.<ta>, <Vn>.16B, <Vm>.<ta> 3169 {0xbfe0fc00, 0x0e007000, TBX, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_4_arrangement_16B, arg_Vm_arrangement_Q___8B_0__16B_1}, nil}, 3170 // TBX <Vd>.<ta>, <Vn>.16B, <Vm>.<ta> 3171 {0xbfe0fc00, 0x0e001000, TBX, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_1_arrangement_16B, arg_Vm_arrangement_Q___8B_0__16B_1}, nil}, 3172 // TRN1 <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 3173 {0xbf20fc00, 0x0e002800, TRN1, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil}, 3174 // TRN2 <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 3175 {0xbf20fc00, 0x0e006800, TRN2, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil}, 3176 // UABA <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 3177 {0xbf20fc00, 0x2e207c00, UABA, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 3178 // UABAL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb> 3179 {0xff20fc00, 0x2e205000, UABAL, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 3180 // UABAL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb> 3181 {0xff20fc00, 0x6e205000, UABAL2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 3182 // UABD <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 3183 {0xbf20fc00, 0x2e207400, UABD, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 3184 // UABDL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb> 3185 {0xff20fc00, 0x2e207000, UABDL, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 3186 // UABDL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb> 3187 {0xff20fc00, 0x6e207000, UABDL2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 3188 // UADALP <Vd>.<ta>, <Vn>.<tb> 3189 {0xbf3ffc00, 0x2e206800, UADALP, instArgs{arg_Vd_arrangement_size_Q___4H_00__8H_01__2S_10__4S_11__1D_20__2D_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 3190 // UADDL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb> 3191 {0xff20fc00, 0x2e200000, UADDL, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 3192 // UADDL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb> 3193 {0xff20fc00, 0x6e200000, UADDL2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 3194 // UADDLP <Vd>.<ta>, <Vn>.<tb> 3195 {0xbf3ffc00, 0x2e202800, UADDLP, instArgs{arg_Vd_arrangement_size_Q___4H_00__8H_01__2S_10__4S_11__1D_20__2D_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 3196 // UADDLV <V><d>, <Vn>.<t> 3197 {0xbf3ffc00, 0x2e303800, UADDLV, instArgs{arg_Vd_22_2__H_0__S_1__D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__4S_21}, nil}, 3198 // UADDW <Vd>.<ta>, <Vn>.<ta>, <Vm>.<tb> 3199 {0xff20fc00, 0x2e201000, UADDW, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size___8H_0__4S_1__2D_2, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 3200 // UADDW2 <Vd>.<ta>, <Vn>.<ta>, <Vm>.<tb> 3201 {0xff20fc00, 0x6e201000, UADDW2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size___8H_0__4S_1__2D_2, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 3202 // UCVTF <Sd>, <Wn>, #<fbits> 3203 {0xffff0000, 0x1e030000, UCVTF, instArgs{arg_Sd, arg_Wn, arg_immediate_fbits_min_1_max_32_sub_64_scale}, nil}, 3204 // UCVTF <Dd>, <Wn>, #<fbits> 3205 {0xffff0000, 0x1e430000, UCVTF, instArgs{arg_Dd, arg_Wn, arg_immediate_fbits_min_1_max_32_sub_64_scale}, nil}, 3206 // UCVTF <Sd>, <Xn>, #<fbits> 3207 {0xffff0000, 0x9e030000, UCVTF, instArgs{arg_Sd, arg_Xn, arg_immediate_fbits_min_1_max_64_sub_64_scale}, nil}, 3208 // UCVTF <Dd>, <Xn>, #<fbits> 3209 {0xffff0000, 0x9e430000, UCVTF, instArgs{arg_Dd, arg_Xn, arg_immediate_fbits_min_1_max_64_sub_64_scale}, nil}, 3210 // UCVTF <Sd>, <Wn> 3211 {0xfffffc00, 0x1e230000, UCVTF, instArgs{arg_Sd, arg_Wn}, nil}, 3212 // UCVTF <Dd>, <Wn> 3213 {0xfffffc00, 0x1e630000, UCVTF, instArgs{arg_Dd, arg_Wn}, nil}, 3214 // UCVTF <Sd>, <Xn> 3215 {0xfffffc00, 0x9e230000, UCVTF, instArgs{arg_Sd, arg_Xn}, nil}, 3216 // UCVTF <Dd>, <Xn> 3217 {0xfffffc00, 0x9e630000, UCVTF, instArgs{arg_Dd, arg_Xn}, nil}, 3218 // UCVTF <V><d>, <V><n>, #<fbits> 3219 {0xff80fc00, 0x7f00e400, UCVTF, instArgs{arg_Vd_19_4__S_4__D_8, arg_Vn_19_4__S_4__D_8, arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__64UIntimmhimmb_4__128UIntimmhimmb_8}, ucvtf_asisdshf_c_cond}, 3220 // UCVTF <Vd>.<t>, <Vn>.<t>, #<fbits> 3221 {0xbf80fc00, 0x2f00e400, UCVTF, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__2S_40__4S_41__2D_81, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__2S_40__4S_41__2D_81, arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__64UIntimmhimmb_4__128UIntimmhimmb_8}, ucvtf_asimdshf_c_cond}, 3222 // UCVTF <V><d>, <V><n> 3223 {0xffbffc00, 0x7e21d800, UCVTF, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1}, nil}, 3224 // UCVTF <Vd>.<t>, <Vn>.<t> 3225 {0xbfbffc00, 0x2e21d800, UCVTF, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil}, 3226 // UHADD <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 3227 {0xbf20fc00, 0x2e200400, UHADD, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 3228 // UHSUB <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 3229 {0xbf20fc00, 0x2e202400, UHSUB, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 3230 // UMAX <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 3231 {0xbf20fc00, 0x2e206400, UMAX, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 3232 // UMAXP <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 3233 {0xbf20fc00, 0x2e20a400, UMAXP, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 3234 // UMAXV <V><d>, <Vn>.<t> 3235 {0xbf3ffc00, 0x2e30a800, UMAXV, instArgs{arg_Vd_22_2__B_0__H_1__S_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__4S_21}, nil}, 3236 // UMIN <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 3237 {0xbf20fc00, 0x2e206c00, UMIN, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 3238 // UMINP <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 3239 {0xbf20fc00, 0x2e20ac00, UMINP, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 3240 // UMINV <V><d>, <Vn>.<t> 3241 {0xbf3ffc00, 0x2e31a800, UMINV, instArgs{arg_Vd_22_2__B_0__H_1__S_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__4S_21}, nil}, 3242 // UMLAL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<ts>[<index>] 3243 {0xff00f400, 0x2f002000, UMLAL, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil}, 3244 // UMLAL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<ts>[<index>] 3245 {0xff00f400, 0x6f002000, UMLAL2, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil}, 3246 // UMLAL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb> 3247 {0xff20fc00, 0x2e208000, UMLAL, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 3248 // UMLAL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb> 3249 {0xff20fc00, 0x6e208000, UMLAL2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 3250 // UMLSL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<ts>[<index>] 3251 {0xff00f400, 0x2f006000, UMLSL, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil}, 3252 // UMLSL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<ts>[<index>] 3253 {0xff00f400, 0x6f006000, UMLSL2, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil}, 3254 // UMLSL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb> 3255 {0xff20fc00, 0x2e20a000, UMLSL, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 3256 // UMLSL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb> 3257 {0xff20fc00, 0x6e20a000, UMLSL2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 3258 // UMULL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<ts>[<index>] 3259 {0xff00f400, 0x2f00a000, UMULL, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil}, 3260 // UMULL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<ts>[<index>] 3261 {0xff00f400, 0x6f00a000, UMULL2, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil}, 3262 // UMULL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb> 3263 {0xff20fc00, 0x2e20c000, UMULL, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 3264 // UMULL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb> 3265 {0xff20fc00, 0x6e20c000, UMULL2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 3266 // UQADD <V><d>, <V><n>, <V><m> 3267 {0xff20fc00, 0x7e200c00, UQADD, instArgs{arg_Vd_22_2__B_0__H_1__S_2__D_3, arg_Vn_22_2__B_0__H_1__S_2__D_3, arg_Vm_22_2__B_0__H_1__S_2__D_3}, nil}, 3268 // UQADD <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 3269 {0xbf20fc00, 0x2e200c00, UQADD, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil}, 3270 // UQRSHL <V><d>, <V><n>, <V><m> 3271 {0xff20fc00, 0x7e205c00, UQRSHL, instArgs{arg_Vd_22_2__B_0__H_1__S_2__D_3, arg_Vn_22_2__B_0__H_1__S_2__D_3, arg_Vm_22_2__B_0__H_1__S_2__D_3}, nil}, 3272 // UQRSHL <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 3273 {0xbf20fc00, 0x2e205c00, UQRSHL, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil}, 3274 // UQRSHRN <V><d>, <V><n>, #<shift> 3275 {0xff80fc00, 0x7f009c00, UQRSHRN, instArgs{arg_Vd_19_4__B_1__H_2__S_4, arg_Vn_19_4__H_1__S_2__D_4, arg_immediate_1_width_immh_immb__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, uqrshrn_asisdshf_n_cond}, 3276 // UQRSHRN <Vd>.<tb>, <Vn>.<ta>, #<shift> 3277 {0xff80fc00, 0x2f009c00, UQRSHRN, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, uqrshrn_asimdshf_n_cond}, 3278 // UQRSHRN2 <Vd>.<tb>, <Vn>.<ta>, #<shift> 3279 {0xff80fc00, 0x6f009c00, UQRSHRN2, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, uqrshrn_asimdshf_n_cond}, 3280 // UQSHL <V><d>, <V><n>, #<shift> 3281 {0xff80fc00, 0x7f007400, UQSHL, instArgs{arg_Vd_19_4__B_1__H_2__S_4__D_8, arg_Vn_19_4__B_1__H_2__S_4__D_8, arg_immediate_0_width_m1_immh_immb__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8}, uqshl_asisdshf_r_cond}, 3282 // UQSHL <Vd>.<t>, <Vn>.<t>, #<shift> 3283 {0xbf80fc00, 0x2f007400, UQSHL, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8}, uqshl_asimdshf_r_cond}, 3284 // UQSHL <V><d>, <V><n>, <V><m> 3285 {0xff20fc00, 0x7e204c00, UQSHL, instArgs{arg_Vd_22_2__B_0__H_1__S_2__D_3, arg_Vn_22_2__B_0__H_1__S_2__D_3, arg_Vm_22_2__B_0__H_1__S_2__D_3}, nil}, 3286 // UQSHL <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 3287 {0xbf20fc00, 0x2e204c00, UQSHL, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil}, 3288 // UQSHRN <V><d>, <V><n>, #<shift> 3289 {0xff80fc00, 0x7f009400, UQSHRN, instArgs{arg_Vd_19_4__B_1__H_2__S_4, arg_Vn_19_4__H_1__S_2__D_4, arg_immediate_1_width_immh_immb__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, uqshrn_asisdshf_n_cond}, 3290 // UQSHRN <Vd>.<tb>, <Vn>.<ta>, #<shift> 3291 {0xff80fc00, 0x2f009400, UQSHRN, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, uqshrn_asimdshf_n_cond}, 3292 // UQSHRN2 <Vd>.<tb>, <Vn>.<ta>, #<shift> 3293 {0xff80fc00, 0x6f009400, UQSHRN2, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, uqshrn_asimdshf_n_cond}, 3294 // UQSUB <V><d>, <V><n>, <V><m> 3295 {0xff20fc00, 0x7e202c00, UQSUB, instArgs{arg_Vd_22_2__B_0__H_1__S_2__D_3, arg_Vn_22_2__B_0__H_1__S_2__D_3, arg_Vm_22_2__B_0__H_1__S_2__D_3}, nil}, 3296 // UQSUB <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 3297 {0xbf20fc00, 0x2e202c00, UQSUB, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil}, 3298 // UQXTN <V><d>, <V><n> 3299 {0xff3ffc00, 0x7e214800, UQXTN, instArgs{arg_Vd_22_2__B_0__H_1__S_2, arg_Vn_22_2__H_0__S_1__D_2}, nil}, 3300 // UQXTN <Vd>.<tb>, <Vn>.<ta> 3301 {0xff3ffc00, 0x2e214800, UQXTN, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size___8H_0__4S_1__2D_2}, nil}, 3302 // UQXTN2 <Vd>.<tb>, <Vn>.<ta> 3303 {0xff3ffc00, 0x6e214800, UQXTN2, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size___8H_0__4S_1__2D_2}, nil}, 3304 // URECPE <Vd>.<t>, <Vn>.<t> 3305 {0xbfbffc00, 0x0ea1c800, URECPE, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01, arg_Vn_arrangement_sz_Q___2S_00__4S_01}, nil}, 3306 // URHADD <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 3307 {0xbf20fc00, 0x2e201400, URHADD, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 3308 // URSHL <V><d>, <V><n>, <V><m> 3309 {0xff20fc00, 0x7e205400, URSHL, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3, arg_Vm_22_2__D_3}, nil}, 3310 // URSHL <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 3311 {0xbf20fc00, 0x2e205400, URSHL, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil}, 3312 // URSHR <V><d>, <V><n>, #<shift> 3313 {0xff80fc00, 0x7f002400, URSHR, instArgs{arg_Vd_19_4__D_8, arg_Vn_19_4__D_8, arg_immediate_1_64_immh_immb__128UIntimmhimmb_8}, urshr_asisdshf_r_cond}, 3314 // URSHR <Vd>.<t>, <Vn>.<t>, #<shift> 3315 {0xbf80fc00, 0x2f002400, URSHR, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4__128UIntimmhimmb_8}, urshr_asimdshf_r_cond}, 3316 // URSQRTE <Vd>.<t>, <Vn>.<t> 3317 {0xbfbffc00, 0x2ea1c800, URSQRTE, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01, arg_Vn_arrangement_sz_Q___2S_00__4S_01}, nil}, 3318 // URSRA <V><d>, <V><n>, #<shift> 3319 {0xff80fc00, 0x7f003400, URSRA, instArgs{arg_Vd_19_4__D_8, arg_Vn_19_4__D_8, arg_immediate_1_64_immh_immb__128UIntimmhimmb_8}, ursra_asisdshf_r_cond}, 3320 // URSRA <Vd>.<t>, <Vn>.<t>, #<shift> 3321 {0xbf80fc00, 0x2f003400, URSRA, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4__128UIntimmhimmb_8}, ursra_asimdshf_r_cond}, 3322 // USHL <V><d>, <V><n>, <V><m> 3323 {0xff20fc00, 0x7e204400, USHL, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3, arg_Vm_22_2__D_3}, nil}, 3324 // USHL <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 3325 {0xbf20fc00, 0x2e204400, USHL, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil}, 3326 // UXTL <Vd>.<ta>, <Vn>.<tb> 3327 {0xff87fc00, 0x2f00a400, UXTL, instArgs{arg_Vd_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41}, uxtl_ushll_asimdshf_l_cond}, 3328 // UXTL2 <Vd>.<ta>, <Vn>.<tb> 3329 {0xff87fc00, 0x6f00a400, UXTL2, instArgs{arg_Vd_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41}, uxtl_ushll_asimdshf_l_cond}, 3330 // USHLL <Vd>.<ta>, <Vn>.<tb>, #<shift> 3331 {0xff80fc00, 0x2f00a400, USHLL, instArgs{arg_Vd_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4}, ushll_asimdshf_l_cond}, 3332 // USHLL2 <Vd>.<ta>, <Vn>.<tb>, #<shift> 3333 {0xff80fc00, 0x6f00a400, USHLL2, instArgs{arg_Vd_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4}, ushll_asimdshf_l_cond}, 3334 // USHR <V><d>, <V><n>, #<shift> 3335 {0xff80fc00, 0x7f000400, USHR, instArgs{arg_Vd_19_4__D_8, arg_Vn_19_4__D_8, arg_immediate_1_64_immh_immb__128UIntimmhimmb_8}, ushr_asisdshf_r_cond}, 3336 // USHR <Vd>.<t>, <Vn>.<t>, #<shift> 3337 {0xbf80fc00, 0x2f000400, USHR, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4__128UIntimmhimmb_8}, ushr_asimdshf_r_cond}, 3338 // USQADD <V><d>, <V><n> 3339 {0xff3ffc00, 0x7e203800, USQADD, instArgs{arg_Vd_22_2__B_0__H_1__S_2__D_3, arg_Vn_22_2__B_0__H_1__S_2__D_3}, nil}, 3340 // USQADD <Vd>.<t>, <Vn>.<t> 3341 {0xbf3ffc00, 0x2e203800, USQADD, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil}, 3342 // USRA <V><d>, <V><n>, #<shift> 3343 {0xff80fc00, 0x7f001400, USRA, instArgs{arg_Vd_19_4__D_8, arg_Vn_19_4__D_8, arg_immediate_1_64_immh_immb__128UIntimmhimmb_8}, usra_asisdshf_r_cond}, 3344 // USRA <Vd>.<t>, <Vn>.<t>, #<shift> 3345 {0xbf80fc00, 0x2f001400, USRA, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4__128UIntimmhimmb_8}, usra_asimdshf_r_cond}, 3346 // USUBL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb> 3347 {0xff20fc00, 0x2e202000, USUBL, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 3348 // USUBL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb> 3349 {0xff20fc00, 0x6e202000, USUBL2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 3350 // USUBW <Vd>.<ta>, <Vn>.<ta>, <Vm>.<tb> 3351 {0xff20fc00, 0x2e203000, USUBW, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size___8H_0__4S_1__2D_2, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 3352 // USUBW2 <Vd>.<ta>, <Vn>.<ta>, <Vm>.<tb> 3353 {0xff20fc00, 0x6e203000, USUBW2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size___8H_0__4S_1__2D_2, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil}, 3354 // UZP1 <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 3355 {0xbf20fc00, 0x0e001800, UZP1, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil}, 3356 // UZP2 <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 3357 {0xbf20fc00, 0x0e005800, UZP2, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil}, 3358 // XTN <Vd>.<tb>, <Vn>.<ta> 3359 {0xff3ffc00, 0x0e212800, XTN, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size___8H_0__4S_1__2D_2}, nil}, 3360 // XTN2 <Vd>.<tb>, <Vn>.<ta> 3361 {0xff3ffc00, 0x4e212800, XTN2, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size___8H_0__4S_1__2D_2}, nil}, 3362 // ZIP1 <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 3363 {0xbf20fc00, 0x0e003800, ZIP1, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil}, 3364 // ZIP2 <Vd>.<t>, <Vn>.<t>, <Vm>.<t> 3365 {0xbf20fc00, 0x0e007800, ZIP2, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil}, 3366} 3367