1 /* 2 * Copyright (c) 2024, Rockchip, Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __SOC_H__ 8 #define __SOC_H__ 9 10 enum pll_id { 11 APLL_ID, 12 DPLL_ID, 13 GPLL_ID, 14 CPLL_ID, 15 NPLL_ID, 16 VPLL_ID, 17 }; 18 19 enum pmu_pll_id { 20 PPLL_ID = 0, 21 HPLL_ID 22 }; 23 24 enum cru_mode_con00 { 25 CLK_APLL, 26 CLK_DPLL, 27 CLK_CPLL, 28 CLK_GPLL, 29 CLK_REVSERVED, 30 CLK_NPLL, 31 CLK_VPLL, 32 CLK_USBPLL, 33 }; 34 35 #define KHz 1000 36 #define MHz (1000 * KHz) 37 #define OSC_HZ (24 * MHz) 38 39 /* CRU */ 40 #define GLB_SRST_FST_CFG_VAL 0xfdb9 41 42 #define CRU_PLLS_CON(pll_id, i) (0x160 + (pll_id) * 0x20 + (i) * 0x4) 43 #define CRU_PLL_CON(i) ((i) * 0x4) 44 #define CRU_MODE_CON0 0x280 45 #define CRU_CLKSEL_CON(i) ((i) * 0x4 + 0x300) 46 #define CRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800) 47 #define CRU_CLKGATE_CON_CNT 78 48 #define CRU_SOFTRST_CON(i) ((i) * 0x4 + 0xa00) 49 #define CRU_GLB_CNT_TH 0xc00 50 #define CRU_GLB_SRST_FST 0xc08 51 #define CRU_GLB_SRST_SND 0xc0c 52 #define CRU_GLB_RST_CON 0xc10 53 #define CRU_GLB_RST_ST 0xc04 54 #define CRU_SDIO_CON0 0xc24 55 #define CRU_SDIO_CON1 0xc28 56 #define CRU_SDMMC_CON0 0xc30 57 #define CRU_SDMMC_CON1 0xc34 58 #define CRU_AUTOCS_CON0(id) (0xd00 + (id) * 8) 59 #define CRU_AUTOCS_CON1(id) (0xd04 + (id) * 8) 60 61 #define CRU_AUTOCS_ID_CNT 74 62 63 #define CRU_PLLCON0_M_MASK 0x3ff 64 #define CRU_PLLCON0_M_SHIFT 0 65 #define CRU_PLLCON1_P_MASK 0x3f 66 #define CRU_PLLCON1_P_SHIFT 0 67 #define CRU_PLLCON1_S_MASK 0x7 68 #define CRU_PLLCON1_S_SHIFT 6 69 #define CRU_PLLCON2_K_MASK 0xffff 70 #define CRU_PLLCON2_K_SHIFT 0 71 #define CRU_PLLCON1_PWRDOWN BIT(13) 72 #define CRU_PLLCON6_LOCK_STATUS BIT(15) 73 74 #define CRU_BIGCPU02_RST_MSK 0x30 75 #define CRU_BIGCPU13_RST_MSK 0x300 76 77 #define PHPCRU_CLKGATE_CON 0x800 78 #define PHPCRU_CLKGATE_CON_CNT 1 79 80 #define SECURECRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800) 81 #define SECURECRU_CLKGATE_CON_CNT 4 82 83 #define PMU1CRU_CLKGATE_CON_CNT 6 84 85 /* CENTER GRF */ 86 #define CENTER_GRF_CON(i) ((i) * 4) 87 88 /* PMU1GRF */ 89 #define PMU1GRF_SOC_CON(n) ((n) * 4) 90 #define PMU1GRF_SOC_ST 0x60 91 #define PMU1GRF_OS_REG(n) (0x200 + ((n) * 4)) 92 93 #define PMU_MCU_HALT BIT(7) 94 #define PMU_MCU_SLEEP BIT(9) 95 #define PMU_MCU_DEEPSLEEP BIT(10) 96 #define PMU_MCU_STOP_MSK \ 97 (PMU_MCU_HALT | PMU_MCU_SLEEP | PMU_MCU_DEEPSLEEP) 98 99 /* SYSGRF */ 100 #define SYS_GRF_NOC_CON(n) (0x100 + (n) * 4) 101 #define SYS_GRF_SOC_CON(n) (0x300 + (n) * 4) 102 #define SYS_GRF_SOC_STATUS(n) (0x380 + (n) * 4) 103 104 #define SYS_GRF_LITTLE_CPUS_WFE 0xf 105 #define SYS_GRF_CORE0_CPUS_WFE 0x30 106 #define SYS_GRF_CORE1_CPUS_WFE 0xc0 107 #define SYS_GRF_BIG_CPUS_WFE 0xf0 108 #define SYS_GRF_LITTLE_CPUS_WFI 0xf00 109 #define SYS_GRF_CORE0_CPUS_WFI 0x3000 110 #define SYS_GRF_CORE1_CPUS_WFI 0xc000 111 112 /* pvtm */ 113 #define PVTM_CON(i) (0x4 + (i) * 4) 114 #define PVTM_INTEN 0x70 115 #define PVTM_INTSTS 0x74 116 #define PVTM_STATUS(i) (0x80 + (i) * 4) 117 #define PVTM_CALC_CNT 0x200 118 119 enum pvtm_con0 { 120 pvtm_start = 0, 121 pvtm_osc_en = 1, 122 pvtm_osc_sel = 2, 123 pvtm_rnd_seed_en = 5, 124 }; 125 126 /* timer */ 127 #define TIMER_LOAD_COUNT0 0x00 128 #define TIMER_LOAD_COUNT1 0x04 129 #define TIMER_CURRENT_VALUE0 0x08 130 #define TIMER_CURRENT_VALUE1 0x0c 131 #define TIMER_CONTROL_REG 0x10 132 #define TIMER_INTSTATUS 0x18 133 134 #define TIMER_DIS 0x0 135 #define TIMER_EN 0x1 136 137 #define TIMER_FMODE (0x0 << 1) 138 #define TIMER_RMODE (0x1 << 1) 139 140 #define STIMER0_CHN_BASE(n) (STIMER0_BASE + 0x20 * (n)) 141 #define STIMER1_CHN_BASE(n) (STIMER1_BASE + 0x20 * (n)) 142 143 /* cpu timer */ 144 #define TIMER_HP_REVISION 0x0 145 #define TIMER_HP_CTRL 0x4 146 #define TIMER_HP_INT_EN 0x8 147 #define TIMER_HP_T24_GCD 0xc 148 #define TIMER_HP_T32_GCD 0x10 149 #define TIMER_HP_LOAD_COUNT0 0x14 150 #define TIMER_HP_LOAD_COUNT1 0x18 151 #define TIMER_HP_T24_DELAT_COUNT0 0x1c 152 #define TIMER_HP_T24_DELAT_COUNT1 0x20 153 #define TIMER_HP_CURR_32K_VALUE0 0x24 154 #define TIMER_HP_CURR_32K_VALUE1 0x28 155 #define TIMER_HP_CURR_TIMER_VALUE0 0x2c 156 #define TIMER_HP_CURR_TIMER_VALUE1 0x30 157 #define TIMER_HP_T24_32BEGIN0 0x34 158 #define TIMER_HP_T24_32BEGIN1 0x38 159 #define TIMER_HP_T32_24END0 0x3c 160 #define TIMER_HP_T32_24END1 0x40 161 #define TIMER_HP_BEGIN_END_VALID 0x44 162 #define TIMER_HP_SYNC_REQ 0x48 163 #define TIMER_HP_INTR_STATUS 0x4c 164 165 /* GPIO */ 166 #define GPIO_SWPORT_DR_L 0x0000 167 #define GPIO_SWPORT_DR_H 0x0004 168 #define GPIO_SWPORT_DDR_L 0x0008 169 #define GPIO_SWPORT_DDR_H 0x000c 170 #define GPIO_INT_EN_L 0x0010 171 #define GPIO_INT_EN_H 0x0014 172 #define GPIO_INT_MASK_L 0x0018 173 #define GPIO_INT_MASK_H 0x001c 174 #define GPIO_INT_TYPE_L 0x0020 175 #define GPIO_INT_TYPE_H 0x0024 176 #define GPIO_INT_POLARITY_L 0x0028 177 #define GPIO_INT_POLARITY_H 0x002c 178 #define GPIO_INT_BOTHEDGE_L 0x0030 179 #define GPIO_INT_BOTHEDGE_H 0x0034 180 #define GPIO_DEBOUNCE_L 0x0038 181 #define GPIO_DEBOUNCE_H 0x003c 182 #define GPIO_DBCLK_DIV_EN_L 0x0040 183 #define GPIO_DBCLK_DIV_EN_H 0x0044 184 #define GPIO_DBCLK_DIV_CON 0x0048 185 #define GPIO_INT_STATUS 0x0050 186 #define GPIO_INT_RAWSTATUS 0x0058 187 #define GPIO_PORT_EOI_L 0x0060 188 #define GPIO_PORT_EOI_H 0x0064 189 #define GPIO_EXT_PORT 0x0070 190 #define GPIO_VER_ID 0x0078 191 192 /* DDRGRF */ 193 #define DDRGRF_CHA_CON(i) ((i) * 4) 194 #define DDRGRF_CHB_CON(i) (0x30 + (i) * 4) 195 196 #define DDR_CHN_CNT 4 197 198 #endif /* __SOC_H__ */ 199