1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 3 #ifndef _SOC_APOLLOLAKE_PM_H_ 4 #define _SOC_APOLLOLAKE_PM_H_ 5 6 #include <stdint.h> 7 #include <acpi/acpi.h> 8 #include <soc/gpe.h> 9 #include <soc/iomap.h> 10 11 /* ACPI_BASE_ADDRESS */ 12 13 #define PM1_STS 0x00 14 #define WAK_STS (1 << 15) 15 #define PCIEXPWAK_STS (1 << 14) 16 #define PRBTNOR_STS (1 << 11) 17 #define RTC_STS (1 << 10) 18 #define PWRBTN_STS (1 << 8) 19 #define GBL_STS (1 << 5) 20 21 #define PM1_EN 0x02 22 #define PCIEXPWAK_DIS (1 << 14) 23 #define RTC_EN (1 << 10) 24 #define PWRBTN_EN (1 << 8) 25 #define GBL_EN (1 << 5) 26 27 #define PM1_CNT 0x04 28 #define SCI_EN (1 << 0) 29 30 #define PM1_TMR 0x08 31 32 #define SMI_EN 0x40 33 34 #define SMI_ESPI 28 /* This bit is present in GLK*/ 35 #define SMI_OCP_CSE 27 36 #define SMI_SPI 26 37 #define SMI_SPI_SSMI 25 38 #define SMI_SCC2 21 39 #define SMI_PCIE 20 40 #define SMI_SCS 19 41 #define SMI_HOST_SMBUS 18 42 #define SMI_XHCI 17 43 #define SMI_SMBUS 16 44 #define SMI_SERIRQ 15 45 #define SMI_PERIODIC 14 46 #define SMI_TCO 13 47 #define SMI_MCSMI 12 48 #define SMI_GPIO_UNLOCK_SSMI 11 49 #define SMI_GPIO 10 50 #define SMI_BIOS_RLS 7 51 #define SMI_SWSMI_TMR 6 52 #define SMI_APMC 5 53 #define SMI_SLP 4 54 #define SMI_LEGACY_USB 3 55 #define SMI_BIOS 2 56 #define SMI_EOS 1 57 #define SMI_GBL 0 58 59 #if CONFIG(SOC_ESPI) 60 #define ESPI_SMI_EN (1 << SMI_ESPI) /* Valid for GLK with ESPI */ 61 #else 62 #define ESPI_SMI_EN 0 63 #endif 64 #define USB_EN (1 << SMI_XHCI) /* Legacy USB2 SMI logic */ 65 #define PERIODIC_EN (1 << SMI_PERIODIC) /* SMI on PERIODIC_STS in SMI_STS */ 66 #define TCO_SMI_EN (1 << SMI_TCO) /* Enable TCO Logic (BIOSWE et al) */ 67 #define GPIO_EN (1 << SMI_GPIO) /* Enable GPIO SMI */ 68 #define BIOS_RLS (1 << SMI_BIOS_RLS) /* asserts SCI on bit set */ 69 /* start software smi timer on bit set */ 70 #define SWSMI_TMR_EN (1 << SMI_SWSMI_TMR) 71 #define APMC_EN (1 << SMI_APMC) /* Writes to APM_CNT cause SMI# */ 72 /* Write to SLP_EN in PM1_CNT asserts SMI# */ 73 #define SLP_SMI_EN (1 << SMI_SLP) 74 #define BIOS_EN (1 << SMI_BIOS) /* Assert SMI# on GBL_RLS bit */ 75 #define EOS (1 << SMI_EOS) /* End of SMI (deassert SMI#) */ 76 #define GBL_SMI_EN (1 << SMI_GBL) /* Global SMI Enable */ 77 78 /* SMI_EN Params for this platform to pass to enable_smi 79 * 80 * Enable SMI generation: 81 * - on APMC writes (io 0xb2) 82 * - on writes to SLP_EN (sleep states) 83 * - on writes to GBL_RLS (bios commands) 84 * - on eSPI events (does nothing on LPC systems) 85 * No SMIs: 86 * - on microcontroller writes (io 0x62/0x66) 87 * - on TCO events, unless enabled in common code 88 */ 89 #define ENABLE_SMI_PARAMS \ 90 (ESPI_SMI_EN | APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS | GPIO_EN) 91 92 #define SMI_STS 0x44 93 #define SMI_STS_BITS 32 94 /* Bits for SMI status */ 95 #define ESPI_SMI_STS_BIT 28 96 #define PMC_OCP_SMI_STS_BIT 27 97 #define SPI_SMI_STS_BIT 26 98 #define SPI_SSMI_STS_BIT 25 99 #define SCC2_SMI_STS_BIT 21 100 #define PCI_EXP_SMI_STS_BIT 20 101 #define SCS_SMI_STS_BIT 19 102 #define HSMBUS_SMI_STS_BIT 18 103 #define XHCI_SMI_STS_BIT 17 104 #define SMBUS_SMI_STS_BIT 16 105 #define SERIRQ_SMI_STS_BIT 15 106 #define PERIODIC_STS_BIT 14 107 #define TCO_STS_BIT 13 108 #define MC_SMI_STS_BIT 12 109 #define GPIO_UNLOCK_SMI_STS_BIT 11 110 #define GPIO_STS_BIT 10 111 #define GPE0_STS_BIT 9 /* Datasheet says this is reserved */ 112 #define PM1_STS_BIT 8 113 #define SWSMI_TMR_STS_BIT 6 114 #define APM_STS_BIT 5 115 #define SMI_ON_SLP_EN_STS_BIT 4 116 #define LEGACY_USB_STS_BIT 3 117 #define BIOS_STS_BIT 2 118 119 #define GPE_CNTL 0x50 120 #define DEVACT_STS 0x4c 121 122 #define GPE0_REG_MAX 4 123 #define GPE0_REG_SIZE 32 124 #define GPE0_STS(x) (0x20 + ((x) * 4)) 125 #define GPE0_A 0 126 #define GPE0_B 1 127 #define GPE0_C 2 128 #define GPE0_D 3 129 #define GPE_STD GPE0_A 130 #define ESPI_STS (1 << 20) /* This bit is present in GLK */ 131 #define SATA_PME_STS (1 << 17) 132 #define SMB_WAK_STS (1 << 16) 133 #define AVS_PME_STS (1 << 14) 134 #define XHCI_PME_STS (1 << 13) 135 #define XDCI_PME_STS (1 << 12) 136 #define CSE_PME_STS (1 << 11) 137 #define BATLOW_STS (1 << 10) 138 #define PCIE_GPE_STS (1 << 9) 139 #define SWGPE_STS (1 << 2) 140 #define GPE0_EN(x) (0x30 + ((x) * 4)) 141 #define ESPI_EN (1 << 20) /* This bit is present in GLK */ 142 #define SATA_PME_EN (1 << 17) 143 #define SMB_WAK_EN (1 << 16) 144 #define AVS_PME_EN (1 << 14) 145 #define PME_B0_EN (1 << 13) 146 #define XDCI_PME_EN (1 << 12) 147 #define CSE_PME_EN (1 << 11) 148 #define BATLOW_EN (1 << 10) 149 #define PCIE_GPE_EN (1 << 9) 150 #define SWGPE_EN (1 << 2) 151 152 /* P-state configuration */ 153 #define PSS_MAX_ENTRIES 8 154 #define PSS_RATIO_STEP 2 155 #define PSS_LATENCY_TRANSITION 10 156 #define PSS_LATENCY_BUSMASTER 10 157 158 #if !defined(__ACPI__) 159 160 #include <soc/pmc.h> 161 162 /* Track power state from reset to log events. */ 163 struct chipset_power_state { 164 uint16_t pm1_sts; 165 uint16_t pm1_en; 166 uint32_t pm1_cnt; 167 uint32_t gpe0_sts[GPE0_REG_MAX]; 168 uint32_t gpe0_en[GPE0_REG_MAX]; 169 uint16_t tco1_sts; 170 uint16_t tco2_sts; 171 uint32_t prsts; 172 uint32_t gen_pmcon1; 173 uint32_t gen_pmcon2; 174 uint32_t gen_pmcon3; 175 uint32_t prev_sleep_state; 176 } __packed; 177 178 void pch_log_state(void); 179 180 /* Get base address PMC memory mapped registers. */ 181 uint8_t *pmc_mmio_regs(void); 182 183 /* STM Support */ 184 uint16_t get_pmbase(void); 185 #endif /* !defined(__ACPI__) */ 186 #endif 187