1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 3 #ifndef __DDRPHY_NAO_REGS_H__ 4 #define __DDRPHY_NAO_REGS_H__ 5 6 #define Channel_A_DDRPHY_NAO_BASE_ADDRESS 0x10236000 7 #define Channel_B_DDRPHY_NAO_BASE_ADDRESS 0x10246000 8 9 #define DDRPHY_NAO_BASE_ADDRESS Channel_A_DDRPHY_NAO_BASE_VIRTUAL 10 11 #define DDRPHY_REG_MISC_STA_EXTLB0 (DDRPHY_NAO_BASE_ADDRESS + 0x0000) 12 #define MISC_STA_EXTLB0_STA_EXTLB_DONE Fld(32, 0) //[31:0] 13 14 #define DDRPHY_REG_MISC_STA_EXTLB1 (DDRPHY_NAO_BASE_ADDRESS + 0x0004) 15 #define MISC_STA_EXTLB1_STA_EXTLB_FAIL Fld(32, 0) //[31:0] 16 17 #define DDRPHY_REG_MISC_STA_EXTLB2 (DDRPHY_NAO_BASE_ADDRESS + 0x0008) 18 #define MISC_STA_EXTLB2_STA_EXTLB_DBG_INFO Fld(32, 0) //[31:0] 19 20 #define DDRPHY_REG_MISC_DMA_DEBUG0 (DDRPHY_NAO_BASE_ADDRESS + 0x0010) 21 #define MISC_DMA_DEBUG0_WPTR Fld(2, 0) //[1:0] 22 #define MISC_DMA_DEBUG0_RPTR Fld(2, 2) //[3:2] 23 #define MISC_DMA_DEBUG0_CMD_CNT Fld(3, 4) //[6:4] 24 #define MISC_DMA_DEBUG0_DATA_CNT Fld(3, 8) //[10:8] 25 #define MISC_DMA_DEBUG0_FIFO_EMPTY Fld(1, 12) //[12:12] 26 #define MISC_DMA_DEBUG0_FIFO_FULL Fld(1, 13) //[13:13] 27 #define MISC_DMA_DEBUG0_DMA_FIRE Fld(1, 14) //[14:14] 28 #define MISC_DMA_DEBUG0_SHU_REG_PTR Fld(1, 15) //[15:15] 29 #define MISC_DMA_DEBUG0_SRAM_DONE Fld(1, 16) //[16:16] 30 #define MISC_DMA_DEBUG0_APB_DONE Fld(1, 17) //[17:17] 31 #define MISC_DMA_DEBUG0_SRAM_DONE_EARLY Fld(1, 18) //[18:18] 32 #define MISC_DMA_DEBUG0_APB_DONE_EARLY Fld(1, 19) //[19:19] 33 #define MISC_DMA_DEBUG0_SRAM_STEP Fld(4, 20) //[23:20] 34 #define MISC_DMA_DEBUG0_APB_STEP Fld(4, 24) //[27:24] 35 #define MISC_DMA_DEBUG0_SC_DR_SRAM_PLL_LOAD_ACK Fld(1, 28) //[28:28] 36 #define MISC_DMA_DEBUG0_SC_DR_SRAM_LOAD_ACK Fld(1, 29) //[29:29] 37 #define MISC_DMA_DEBUG0_SC_DR_SRAM_RESTORE_ACK Fld(1, 30) //[30:30] 38 39 #define DDRPHY_REG_MISC_DMA_DEBUG1 (DDRPHY_NAO_BASE_ADDRESS + 0x0014) 40 #define MISC_DMA_DEBUG1_DMA_TIMER_EARLY Fld(6, 0) //[5:0] 41 #define MISC_DMA_DEBUG1_DMA_TIMER_ALL Fld(12, 8) //[19:8] 42 #define MISC_DMA_DEBUG1_PSEL_DDRPHY Fld(1, 20) //[20:20] 43 #define MISC_DMA_DEBUG1_PSEL_DRAMC Fld(1, 21) //[21:21] 44 #define MISC_DMA_DEBUG1_PSEL_DDRPHY2 Fld(1, 22) //[22:22] 45 #define MISC_DMA_DEBUG1_PSEL_DRAMC2 Fld(1, 23) //[23:23] 46 #define MISC_DMA_DEBUG1_DMA_PENABLE Fld(1, 24) //[24:24] 47 #define MISC_DMA_DEBUG1_PREADY Fld(1, 25) //[25:25] 48 #define MISC_DMA_DEBUG1_KEEP_APB_ARB Fld(1, 26) //[26:26] 49 #define MISC_DMA_DEBUG1_WR_APB Fld(1, 27) //[27:27] 50 #define MISC_DMA_DEBUG1_SRAM_CS Fld(1, 28) //[28:28] 51 #define MISC_DMA_DEBUG1_SRAM_GRANT Fld(1, 29) //[29:29] 52 #define MISC_DMA_DEBUG1_KEEP_SRAM_ARB Fld(1, 30) //[30:30] 53 #define MISC_DMA_DEBUG1_WR_SRAM Fld(1, 31) //[31:31] 54 55 #define DDRPHY_REG_MISC_RETRY_DBG0 (DDRPHY_NAO_BASE_ADDRESS + 0x0018) 56 #define MISC_RETRY_DBG0_PRECAL_CONF_CAL_DONE_ALL Fld(1, 0) //[0:0] 57 #define MISC_RETRY_DBG0_RETRY_DONE_ALL Fld(1, 1) //[1:1] 58 #define MISC_RETRY_DBG0_RK0_RETRY_DONE0 Fld(1, 4) //[4:4] 59 #define MISC_RETRY_DBG0_RK0_RETRY_DONE1 Fld(1, 5) //[5:5] 60 #define MISC_RETRY_DBG0_RK0_RETRY_DONE2 Fld(1, 6) //[6:6] 61 #define MISC_RETRY_DBG0_RK0_RETRY_FAIL0 Fld(1, 8) //[8:8] 62 #define MISC_RETRY_DBG0_RK0_RETRY_FAIL1 Fld(1, 9) //[9:9] 63 #define MISC_RETRY_DBG0_RK0_RETRY_FAIL2 Fld(1, 10) //[10:10] 64 #define MISC_RETRY_DBG0_RK1_RETRY_DONE0 Fld(1, 12) //[12:12] 65 #define MISC_RETRY_DBG0_RK1_RETRY_DONE1 Fld(1, 13) //[13:13] 66 #define MISC_RETRY_DBG0_RK1_RETRY_DONE2 Fld(1, 14) //[14:14] 67 #define MISC_RETRY_DBG0_RK1_RETRY_FAIL0 Fld(1, 16) //[16:16] 68 #define MISC_RETRY_DBG0_RK1_RETRY_FAIL1 Fld(1, 17) //[17:17] 69 #define MISC_RETRY_DBG0_RK1_RETRY_FAIL2 Fld(1, 18) //[18:18] 70 71 #define DDRPHY_REG_MISC_RETRY_DBG1 (DDRPHY_NAO_BASE_ADDRESS + 0x001C) 72 #define MISC_RETRY_DBG1_DQSG_RETRY_1ST_ST Fld(8, 0) //[7:0] 73 #define MISC_RETRY_DBG1_DQSG_RETRY_2ND_ST Fld(8, 8) //[15:8] 74 #define MISC_RETRY_DBG1_DQSG_RETRY_3RD_ST Fld(8, 16) //[23:16] 75 #define MISC_RETRY_DBG1_DQSG_RETRY_4TH_ST Fld(8, 24) //[31:24] 76 77 #define DDRPHY_REG_MISC_RETRY_DBG2 (DDRPHY_NAO_BASE_ADDRESS + 0x0020) 78 #define MISC_RETRY_DBG2_DQSG_RETRY_5TH_ST Fld(8, 0) //[7:0] 79 80 #define DDRPHY_REG_MISC_RDSEL_TRACK_DBG (DDRPHY_NAO_BASE_ADDRESS + 0x0024) 81 #define MISC_RDSEL_TRACK_DBG_RDSEL_TRK_SLOW_ST Fld(1, 2) //[2:2] 82 #define MISC_RDSEL_TRACK_DBG_RDSEL_TRK_FAST_ST Fld(1, 3) //[3:3] 83 #define MISC_RDSEL_TRACK_DBG_RDSEL_TRK_INI2SLOW Fld(1, 4) //[4:4] 84 #define MISC_RDSEL_TRACK_DBG_RDSEL_TRK_INI2FAST Fld(1, 5) //[5:5] 85 #define MISC_RDSEL_TRACK_DBG_RDSEL_TRK_SLOW2INI Fld(1, 6) //[6:6] 86 #define MISC_RDSEL_TRACK_DBG_RDSEL_TRK_FAST2INI Fld(1, 7) //[7:7] 87 88 #define DDRPHY_REG_MISC_DQ_RXDLY_TRRO0 (DDRPHY_NAO_BASE_ADDRESS + 0x0080) 89 #define MISC_DQ_RXDLY_TRRO0_DVS_RKX_BX_SW_LAG_CNT_OUT_B0 Fld(8, 0) //[7:0] 90 #define MISC_DQ_RXDLY_TRRO0_DVS_RKX_BX_SW_LEAD_CNT_OUT_B0 Fld(8, 8) //[15:8] 91 #define MISC_DQ_RXDLY_TRRO0_DVS_RKX_BX_SW_LAG_CNT_OUT_B1 Fld(8, 16) //[23:16] 92 #define MISC_DQ_RXDLY_TRRO0_DVS_RKX_BX_SW_LEAD_CNT_OUT_B1 Fld(8, 24) //[31:24] 93 94 #define DDRPHY_REG_MISC_DQ_RXDLY_TRRO1 (DDRPHY_NAO_BASE_ADDRESS + 0x0084) 95 #define MISC_DQ_RXDLY_TRRO1_DVS_RKX_BX_SW_LAG_CNT_OUT_B2 Fld(8, 0) //[7:0] 96 #define MISC_DQ_RXDLY_TRRO1_DVS_RKX_BX_SW_LEAD_CNT_OUT_B2 Fld(8, 8) //[15:8] 97 #define MISC_DQ_RXDLY_TRRO1_DVS_RKX_BX_SW_LAG_CNT_OUT_B3 Fld(8, 16) //[23:16] 98 #define MISC_DQ_RXDLY_TRRO1_DVS_RKX_BX_SW_LEAD_CNT_OUT_B3 Fld(8, 24) //[31:24] 99 100 #define DDRPHY_REG_MISC_DQ_RXDLY_TRRO2 (DDRPHY_NAO_BASE_ADDRESS + 0x0088) 101 #define MISC_DQ_RXDLY_TRRO2_DVS_RKX_BX_SW_LAG_CNT_OUT_B4 Fld(8, 0) //[7:0] 102 #define MISC_DQ_RXDLY_TRRO2_DVS_RKX_BX_SW_LEAD_CNT_OUT_B4 Fld(8, 8) //[15:8] 103 #define MISC_DQ_RXDLY_TRRO2_DVS_RKX_BX_SW_LAG_CNT_OUT_B5 Fld(8, 16) //[23:16] 104 #define MISC_DQ_RXDLY_TRRO2_DVS_RKX_BX_SW_LEAD_CNT_OUT_B5 Fld(8, 24) //[31:24] 105 106 #define DDRPHY_REG_MISC_DQ_RXDLY_TRRO3 (DDRPHY_NAO_BASE_ADDRESS + 0x008C) 107 #define MISC_DQ_RXDLY_TRRO3_DVS_RKX_BX_SW_LAG_CNT_OUT_B6 Fld(8, 0) //[7:0] 108 #define MISC_DQ_RXDLY_TRRO3_DVS_RKX_BX_SW_LEAD_CNT_OUT_B6 Fld(8, 8) //[15:8] 109 #define MISC_DQ_RXDLY_TRRO3_DVS_RKX_BX_SW_LAG_CNT_OUT_B7 Fld(8, 16) //[23:16] 110 #define MISC_DQ_RXDLY_TRRO3_DVS_RKX_BX_SW_LEAD_CNT_OUT_B7 Fld(8, 24) //[31:24] 111 112 #define DDRPHY_REG_MISC_DQ_RXDLY_TRRO4 (DDRPHY_NAO_BASE_ADDRESS + 0x0090) 113 #define MISC_DQ_RXDLY_TRRO4_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B0 Fld(8, 0) //[7:0] 114 #define MISC_DQ_RXDLY_TRRO4_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B1 Fld(8, 8) //[15:8] 115 #define MISC_DQ_RXDLY_TRRO4_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B2 Fld(8, 16) //[23:16] 116 #define MISC_DQ_RXDLY_TRRO4_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B3 Fld(8, 24) //[31:24] 117 118 #define DDRPHY_REG_MISC_DQ_RXDLY_TRRO5 (DDRPHY_NAO_BASE_ADDRESS + 0x0094) 119 #define MISC_DQ_RXDLY_TRRO5_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B4 Fld(8, 0) //[7:0] 120 #define MISC_DQ_RXDLY_TRRO5_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B5 Fld(8, 8) //[15:8] 121 #define MISC_DQ_RXDLY_TRRO5_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B6 Fld(8, 16) //[23:16] 122 #define MISC_DQ_RXDLY_TRRO5_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B7 Fld(8, 24) //[31:24] 123 124 #define DDRPHY_REG_MISC_DQ_RXDLY_TRRO6 (DDRPHY_NAO_BASE_ADDRESS + 0x0098) 125 #define MISC_DQ_RXDLY_TRRO6_DVS_RKX_BX_SW_LAG_CNT_OUT_DQM0 Fld(8, 0) //[7:0] 126 #define MISC_DQ_RXDLY_TRRO6_DVS_RKX_BX_SW_LEAD_CNT_OUT_DQM0 Fld(8, 8) //[15:8] 127 #define MISC_DQ_RXDLY_TRRO6_DVS_RKX_BX_LEAD_LAG_CNT_OUT_DQM0 Fld(8, 24) //[31:24] 128 129 #define DDRPHY_REG_MISC_DQ_RXDLY_TRRO7 (DDRPHY_NAO_BASE_ADDRESS + 0x009C) 130 #define MISC_DQ_RXDLY_TRRO7_DVS_RK0_B0_SW_UP_DONE Fld(1, 0) //[0:0] 131 #define MISC_DQ_RXDLY_TRRO7_DVS_RK0_B1_SW_UP_DONE Fld(1, 4) //[4:4] 132 #define MISC_DQ_RXDLY_TRRO7_DVS_RK1_B0_SW_UP_DONE Fld(1, 8) //[8:8] 133 #define MISC_DQ_RXDLY_TRRO7_DVS_RK1_B1_SW_UP_DONE Fld(1, 12) //[12:12] 134 #define MISC_DQ_RXDLY_TRRO7_DVS_RK2_B0_SW_UP_DONE Fld(1, 16) //[16:16] 135 #define MISC_DQ_RXDLY_TRRO7_DVS_RK2_B1_SW_UP_DONE Fld(1, 20) //[20:20] 136 137 #define DDRPHY_REG_MISC_DQ_RXDLY_TRRO8 (DDRPHY_NAO_BASE_ADDRESS + 0x00A0) 138 #define MISC_DQ_RXDLY_TRRO8_DVS_RKX_BX_TH_CNT_OUT_B0 Fld(9, 0) //[8:0] 139 #define MISC_DQ_RXDLY_TRRO8_DVS_RKX_BX_TH_CNT_OUT_B1 Fld(9, 16) //[24:16] 140 141 #define DDRPHY_REG_MISC_DQ_RXDLY_TRRO9 (DDRPHY_NAO_BASE_ADDRESS + 0x00A4) 142 #define MISC_DQ_RXDLY_TRRO9_DVS_RKX_BX_TH_CNT_OUT_B2 Fld(9, 0) //[8:0] 143 #define MISC_DQ_RXDLY_TRRO9_DVS_RKX_BX_TH_CNT_OUT_B3 Fld(9, 16) //[24:16] 144 145 #define DDRPHY_REG_MISC_DQ_RXDLY_TRRO10 (DDRPHY_NAO_BASE_ADDRESS + 0x00A8) 146 #define MISC_DQ_RXDLY_TRRO10_DVS_RKX_BX_TH_CNT_OUT_B4 Fld(9, 0) //[8:0] 147 #define MISC_DQ_RXDLY_TRRO10_DVS_RKX_BX_TH_CNT_OUT_B5 Fld(9, 16) //[24:16] 148 149 #define DDRPHY_REG_MISC_DQ_RXDLY_TRRO11 (DDRPHY_NAO_BASE_ADDRESS + 0x00AC) 150 #define MISC_DQ_RXDLY_TRRO11_DVS_RKX_BX_TH_CNT_OUT_B6 Fld(9, 0) //[8:0] 151 #define MISC_DQ_RXDLY_TRRO11_DVS_RKX_BX_TH_CNT_OUT_B7 Fld(9, 16) //[24:16] 152 153 #define DDRPHY_REG_MISC_DQ_RXDLY_TRRO12 (DDRPHY_NAO_BASE_ADDRESS + 0x00B0) 154 #define MISC_DQ_RXDLY_TRRO12_DVS_RKX_BX_TH_CNT_OUT_DQM0 Fld(9, 0) //[8:0] 155 156 #define DDRPHY_REG_MISC_DQ_RXDLY_TRRO13 (DDRPHY_NAO_BASE_ADDRESS + 0x00B4) 157 #define MISC_DQ_RXDLY_TRRO13_DA_RK0_DQX_B0_R_DLY Fld(6, 0) //[5:0] 158 #define MISC_DQ_RXDLY_TRRO13_DA_RK0_DQS0_R_DLY Fld(7, 8) //[14:8] 159 #define MISC_DQ_RXDLY_TRRO13_DA_RK0_DQX_B1_R_DLY Fld(6, 16) //[21:16] 160 #define MISC_DQ_RXDLY_TRRO13_DA_RK0_DQS1_R_DLY Fld(7, 24) //[30:24] 161 162 #define DDRPHY_REG_MISC_DQ_RXDLY_TRRO14 (DDRPHY_NAO_BASE_ADDRESS + 0x00B8) 163 #define MISC_DQ_RXDLY_TRRO14_DA_RK1_DQX_B0_R_DLY Fld(6, 0) //[5:0] 164 #define MISC_DQ_RXDLY_TRRO14_DA_RK1_DQS0_R_DLY Fld(7, 8) //[14:8] 165 #define MISC_DQ_RXDLY_TRRO14_DA_RK1_DQX_B1_R_DLY Fld(6, 16) //[21:16] 166 #define MISC_DQ_RXDLY_TRRO14_DA_RK1_DQS1_R_DLY Fld(7, 24) //[30:24] 167 168 #define DDRPHY_REG_MISC_DQ_RXDLY_TRRO15 (DDRPHY_NAO_BASE_ADDRESS + 0x00BC) 169 #define MISC_DQ_RXDLY_TRRO15_DA_RK2_DQX_B0_R_DLY Fld(6, 0) //[5:0] 170 #define MISC_DQ_RXDLY_TRRO15_DA_RK2_DQS0_R_DLY Fld(7, 8) //[14:8] 171 #define MISC_DQ_RXDLY_TRRO15_DA_RK2_DQX_B1_R_DLY Fld(6, 16) //[21:16] 172 #define MISC_DQ_RXDLY_TRRO15_DA_RK2_DQS1_R_DLY Fld(7, 24) //[30:24] 173 174 #define DDRPHY_REG_MISC_DQ_RXDLY_TRRO16 (DDRPHY_NAO_BASE_ADDRESS + 0x00C0) 175 #define MISC_DQ_RXDLY_TRRO16_DVS_RXDLY_STS_ERR_CNT_ALL Fld(32, 0) //[31:0] 176 177 #define DDRPHY_REG_MISC_DQ_RXDLY_TRRO17 (DDRPHY_NAO_BASE_ADDRESS + 0x00C4) 178 #define MISC_DQ_RXDLY_TRRO17_DVS_RXDLY_STS_ERR_CNT_ALL_47_32 Fld(16, 0) //[15:0] 179 #define MISC_DQ_RXDLY_TRRO17_PBYTE_LEADLAG_STUCK_B0 Fld(1, 16) //[16:16] 180 #define MISC_DQ_RXDLY_TRRO17_PBYTE_LEADLAG_STUCK_B1 Fld(1, 24) //[24:24] 181 182 #define DDRPHY_REG_MISC_DQ_RXDLY_TRRO18 (DDRPHY_NAO_BASE_ADDRESS + 0x00C8) 183 #define MISC_DQ_RXDLY_TRRO18_RXDLY_DBG_MON_VALID Fld(1, 0) //[0:0] 184 #define MISC_DQ_RXDLY_TRRO18_RXDLY_RK0_FAIL_LAT Fld(1, 1) //[1:1] 185 #define MISC_DQ_RXDLY_TRRO18_RXDLY_RK1_FAIL_LAT Fld(1, 2) //[2:2] 186 #define MISC_DQ_RXDLY_TRRO18_RXDLY_RK2_FAIL_LAT Fld(1, 3) //[3:3] 187 #define MISC_DQ_RXDLY_TRRO18_DFS_SHU_GP_FAIL_LAT Fld(2, 4) //[5:4] 188 189 #define DDRPHY_REG_MISC_DQ_RXDLY_TRRO19 (DDRPHY_NAO_BASE_ADDRESS + 0x00CC) 190 #define MISC_DQ_RXDLY_TRRO19_RESERVED_0X00C Fld(32, 0) //[31:0] 191 192 #define DDRPHY_REG_MISC_DQ_RXDLY_TRRO20 (DDRPHY_NAO_BASE_ADDRESS + 0x00D0) 193 #define MISC_DQ_RXDLY_TRRO20_RESERVED_0X0D0 Fld(32, 0) //[31:0] 194 195 #define DDRPHY_REG_MISC_DQ_RXDLY_TRRO21 (DDRPHY_NAO_BASE_ADDRESS + 0x00D4) 196 #define MISC_DQ_RXDLY_TRRO21_RESERVED_0X0D4 Fld(32, 0) //[31:0] 197 198 #define DDRPHY_REG_MISC_DQ_RXDLY_TRRO22 (DDRPHY_NAO_BASE_ADDRESS + 0x00D8) 199 #define MISC_DQ_RXDLY_TRRO22_RESERVED_0X0D8 Fld(32, 0) //[31:0] 200 201 #define DDRPHY_REG_MISC_DQ_RXDLY_TRRO23 (DDRPHY_NAO_BASE_ADDRESS + 0x00DC) 202 #define MISC_DQ_RXDLY_TRRO23_RESERVED_0X0DC Fld(32, 0) //[31:0] 203 204 #define DDRPHY_REG_MISC_DQ_RXDLY_TRRO24 (DDRPHY_NAO_BASE_ADDRESS + 0x00E0) 205 #define MISC_DQ_RXDLY_TRRO24_RESERVED_0X0E0 Fld(32, 0) //[31:0] 206 207 #define DDRPHY_REG_MISC_DQ_RXDLY_TRRO25 (DDRPHY_NAO_BASE_ADDRESS + 0x00E4) 208 #define MISC_DQ_RXDLY_TRRO25_RESERVED_0X0E4 Fld(32, 0) //[31:0] 209 210 #define DDRPHY_REG_MISC_DQ_RXDLY_TRRO26 (DDRPHY_NAO_BASE_ADDRESS + 0x00E8) 211 #define MISC_DQ_RXDLY_TRRO26_RESERVED_0X0E8 Fld(32, 0) //[31:0] 212 213 #define DDRPHY_REG_MISC_DQ_RXDLY_TRRO27 (DDRPHY_NAO_BASE_ADDRESS + 0x00EC) 214 #define MISC_DQ_RXDLY_TRRO27_RESERVED_0X0EC Fld(32, 0) //[31:0] 215 216 #define DDRPHY_REG_MISC_DQ_RXDLY_TRRO28 (DDRPHY_NAO_BASE_ADDRESS + 0x00F0) 217 #define MISC_DQ_RXDLY_TRRO28_RESERVED_0X0F0 Fld(32, 0) //[31:0] 218 219 #define DDRPHY_REG_MISC_DQ_RXDLY_TRRO29 (DDRPHY_NAO_BASE_ADDRESS + 0x00F4) 220 #define MISC_DQ_RXDLY_TRRO29_RESERVED_0X0F4 Fld(32, 0) //[31:0] 221 222 #define DDRPHY_REG_MISC_DQ_RXDLY_TRRO30 (DDRPHY_NAO_BASE_ADDRESS + 0x00F8) 223 #define MISC_DQ_RXDLY_TRRO30_RESERVED_0X0F8 Fld(32, 0) //[31:0] 224 225 #define DDRPHY_REG_MISC_DQ_RXDLY_TRRO31 (DDRPHY_NAO_BASE_ADDRESS + 0x00FC) 226 #define MISC_DQ_RXDLY_TRRO31_RESERVED_0X0FC Fld(32, 0) //[31:0] 227 228 #define DDRPHY_REG_MISC_CA_RXDLY_TRRO20 (DDRPHY_NAO_BASE_ADDRESS + 0x0150) 229 #define MISC_CA_RXDLY_TRRO20_RESERVED_0X150 Fld(32, 0) //[31:0] 230 231 #define DDRPHY_REG_MISC_CA_RXDLY_TRRO21 (DDRPHY_NAO_BASE_ADDRESS + 0x0154) 232 #define MISC_CA_RXDLY_TRRO21_RESERVED_0X154 Fld(32, 0) //[31:0] 233 234 #define DDRPHY_REG_MISC_CA_RXDLY_TRRO22 (DDRPHY_NAO_BASE_ADDRESS + 0x0158) 235 #define MISC_CA_RXDLY_TRRO22_RESERVED_0X158 Fld(32, 0) //[31:0] 236 237 #define DDRPHY_REG_MISC_CA_RXDLY_TRRO23 (DDRPHY_NAO_BASE_ADDRESS + 0x015C) 238 #define MISC_CA_RXDLY_TRRO23_RESERVED_0X15C Fld(32, 0) //[31:0] 239 240 #define DDRPHY_REG_MISC_CA_RXDLY_TRRO24 (DDRPHY_NAO_BASE_ADDRESS + 0x0160) 241 #define MISC_CA_RXDLY_TRRO24_RESERVED_0X160 Fld(32, 0) //[31:0] 242 243 #define DDRPHY_REG_MISC_CA_RXDLY_TRRO25 (DDRPHY_NAO_BASE_ADDRESS + 0x0164) 244 #define MISC_CA_RXDLY_TRRO25_RESERVED_0X164 Fld(32, 0) //[31:0] 245 246 #define DDRPHY_REG_MISC_CA_RXDLY_TRRO26 (DDRPHY_NAO_BASE_ADDRESS + 0x0168) 247 #define MISC_CA_RXDLY_TRRO26_RESERVED_0X168 Fld(32, 0) //[31:0] 248 249 #define DDRPHY_REG_MISC_CA_RXDLY_TRRO27 (DDRPHY_NAO_BASE_ADDRESS + 0x016C) 250 #define MISC_CA_RXDLY_TRRO27_RESERVED_0X16C Fld(32, 0) //[31:0] 251 252 #define DDRPHY_REG_MISC_CA_RXDLY_TRRO28 (DDRPHY_NAO_BASE_ADDRESS + 0x0170) 253 #define MISC_CA_RXDLY_TRRO28_RESERVED_0X170 Fld(32, 0) //[31:0] 254 255 #define DDRPHY_REG_MISC_CA_RXDLY_TRRO29 (DDRPHY_NAO_BASE_ADDRESS + 0x0174) 256 #define MISC_CA_RXDLY_TRRO29_RESERVED_0X174 Fld(32, 0) //[31:0] 257 258 #define DDRPHY_REG_MISC_CA_RXDLY_TRRO30 (DDRPHY_NAO_BASE_ADDRESS + 0x0178) 259 #define MISC_CA_RXDLY_TRRO30_RESERVED_0X178 Fld(32, 0) //[31:0] 260 261 #define DDRPHY_REG_MISC_CA_RXDLY_TRRO31 (DDRPHY_NAO_BASE_ADDRESS + 0x017C) 262 #define MISC_CA_RXDLY_TRRO31_RESERVED_0X17C Fld(32, 0) //[31:0] 263 264 #define DDRPHY_REG_MISC_DQO1 (DDRPHY_NAO_BASE_ADDRESS + 0x0180) 265 #define MISC_DQO1_DQO1_RO Fld(32, 0) //[31:0] 266 267 #define DDRPHY_REG_MISC_CAO1 (DDRPHY_NAO_BASE_ADDRESS + 0x0184) 268 #define MISC_CAO1_DQM0O1_RO Fld(1, 0) //[0:0] 269 #define MISC_CAO1_DQM1O1_RO Fld(1, 1) //[1:1] 270 #define MISC_CAO1_DQM2O1_RO Fld(1, 2) //[2:2] 271 #define MISC_CAO1_DQM3O1_RO Fld(1, 3) //[3:3] 272 273 #define DDRPHY_REG_MISC_AD_RX_DQ_O1 (DDRPHY_NAO_BASE_ADDRESS + 0x0188) 274 #define MISC_AD_RX_DQ_O1_AD_RX_ARDQ_O1_B0 Fld(8, 0) //[7:0] 275 #define MISC_AD_RX_DQ_O1_AD_RX_ARDQM0_O1_B0 Fld(1, 8) //[8:8] 276 #define MISC_AD_RX_DQ_O1_AD_RX_ARDQ_O1_B1 Fld(8, 16) //[23:16] 277 #define MISC_AD_RX_DQ_O1_AD_RX_ARDQM0_O1_B1 Fld(1, 24) //[24:24] 278 #define MISC_AD_RX_DQ_O1_AD_RX_ARDQ6_O1_C0 Fld(1, 25) //[25:25] 279 #define MISC_AD_RX_DQ_O1_AD_RX_ARDQ7_O1_C0 Fld(1, 26) //[26:26] 280 281 #define DDRPHY_REG_MISC_AD_RX_CMD_O1 (DDRPHY_NAO_BASE_ADDRESS + 0x018C) 282 #define MISC_AD_RX_CMD_O1_AD_RX_ARCA0_O1 Fld(1, 0) //[0:0] 283 #define MISC_AD_RX_CMD_O1_AD_RX_ARCA1_O1 Fld(1, 1) //[1:1] 284 #define MISC_AD_RX_CMD_O1_AD_RX_ARCA2_O1 Fld(1, 2) //[2:2] 285 #define MISC_AD_RX_CMD_O1_AD_RX_ARCA3_O1 Fld(1, 3) //[3:3] 286 #define MISC_AD_RX_CMD_O1_AD_RX_ARCA4_O1 Fld(1, 4) //[4:4] 287 #define MISC_AD_RX_CMD_O1_AD_RX_ARCA5_O1 Fld(1, 5) //[5:5] 288 #define MISC_AD_RX_CMD_O1_AD_RX_ARCA6_O1 Fld(1, 6) //[6:6] 289 #define MISC_AD_RX_CMD_O1_AD_RX_ARCA7_O1 Fld(1, 7) //[7:7] 290 #define MISC_AD_RX_CMD_O1_AD_RX_ARCA8_O1 Fld(1, 8) //[8:8] 291 #define MISC_AD_RX_CMD_O1_AD_RX_ARCA9_O1 Fld(1, 9) //[9:9] 292 #define MISC_AD_RX_CMD_O1_AD_RX_ARCKE0_O1 Fld(1, 10) //[10:10] 293 #define MISC_AD_RX_CMD_O1_AD_RX_ARCKE1_O1 Fld(1, 11) //[11:11] 294 #define MISC_AD_RX_CMD_O1_AD_RX_ARCKE2_O1 Fld(1, 12) //[12:12] 295 #define MISC_AD_RX_CMD_O1_AD_RX_ARCS0_O1 Fld(1, 13) //[13:13] 296 #define MISC_AD_RX_CMD_O1_AD_RX_ARCS1_O1 Fld(1, 14) //[14:14] 297 #define MISC_AD_RX_CMD_O1_AD_RX_ARCS2_O1 Fld(1, 15) //[15:15] 298 #define MISC_AD_RX_CMD_O1_AD_RX_ARCS1_O1_B1 Fld(1, 16) //[16:16] 299 #define MISC_AD_RX_CMD_O1_AD_RX_ARCKE0_O1_B1 Fld(1, 17) //[17:17] 300 #define MISC_AD_RX_CMD_O1_AD_RX_ARCKE1_O1_B1 Fld(1, 18) //[18:18] 301 302 #define DDRPHY_REG_MISC_PHY_RGS_DQ (DDRPHY_NAO_BASE_ADDRESS + 0x0190) 303 #define MISC_PHY_RGS_DQ_RGS_ARDQ_OFFSET_FLAG_B0 Fld(8, 0) //[7:0] 304 #define MISC_PHY_RGS_DQ_RGS_ARDQM0_OFFSET_FLAG_B0 Fld(1, 8) //[8:8] 305 #define MISC_PHY_RGS_DQ_RGS_RX_ARDQS0_RDY_EYE_B0 Fld(1, 9) //[9:9] 306 #define MISC_PHY_RGS_DQ_APB_ARB_M_DEBUG Fld(2, 12) //[13:12] 307 #define MISC_PHY_RGS_DQ_SRAM_ARB_M_DEBUG Fld(2, 14) //[15:14] 308 #define MISC_PHY_RGS_DQ_RGS_ARDQ_OFFSET_FLAG_B1 Fld(8, 16) //[23:16] 309 #define MISC_PHY_RGS_DQ_RGS_ARDQM0_OFFSET_FLAG_B1 Fld(1, 24) //[24:24] 310 #define MISC_PHY_RGS_DQ_RGS_RX_ARDQS0_RDY_EYE_B1 Fld(1, 25) //[25:25] 311 #define MISC_PHY_RGS_DQ_DA_RPHYPLLGP_CK_SEL Fld(1, 31) //[31:31] 312 313 #define DDRPHY_REG_MISC_PHY_RGS_CMD (DDRPHY_NAO_BASE_ADDRESS + 0x0194) 314 #define MISC_PHY_RGS_CMD_RGS_ARCA0_OFFSET_FLAG Fld(1, 0) //[0:0] 315 #define MISC_PHY_RGS_CMD_RGS_ARCA1_OFFSET_FLAG Fld(1, 1) //[1:1] 316 #define MISC_PHY_RGS_CMD_RGS_ARCA2_OFFSET_FLAG Fld(1, 2) //[2:2] 317 #define MISC_PHY_RGS_CMD_RGS_ARCA3_OFFSET_FLAG Fld(1, 3) //[3:3] 318 #define MISC_PHY_RGS_CMD_RGS_ARCA4_OFFSET_FLAG Fld(1, 4) //[4:4] 319 #define MISC_PHY_RGS_CMD_RGS_ARCA5_OFFSET_FLAG Fld(1, 5) //[5:5] 320 #define MISC_PHY_RGS_CMD_RGS_ARCA6_OFFSET_FLAG Fld(1, 6) //[6:6] 321 #define MISC_PHY_RGS_CMD_RGS_ARCA7_OFFSET_FLAG Fld(1, 7) //[7:7] 322 #define MISC_PHY_RGS_CMD_RGS_ARCA8_OFFSET_FLAG Fld(1, 8) //[8:8] 323 #define MISC_PHY_RGS_CMD_RGS_ARCA9_OFFSET_FLAG Fld(1, 9) //[9:9] 324 #define MISC_PHY_RGS_CMD_RGS_ARCKE0_OFFSET_FLAG Fld(1, 10) //[10:10] 325 #define MISC_PHY_RGS_CMD_RGS_ARCKE1_OFFSET_FLAG Fld(1, 11) //[11:11] 326 #define MISC_PHY_RGS_CMD_RGS_ARCKE2_OFFSET_FLAG Fld(1, 12) //[12:12] 327 #define MISC_PHY_RGS_CMD_RGS_ARCS0_OFFSET_FLAG Fld(1, 13) //[13:13] 328 #define MISC_PHY_RGS_CMD_RGS_ARCS1_OFFSET_FLAG Fld(1, 14) //[14:14] 329 #define MISC_PHY_RGS_CMD_RGS_ARCS2_OFFSET_FLAG Fld(1, 15) //[15:15] 330 #define MISC_PHY_RGS_CMD_RGS_RX_ARCLK_RDY_EYE Fld(1, 16) //[16:16] 331 #define MISC_PHY_RGS_CMD_RGS_RIMPCALOUT Fld(1, 24) //[24:24] 332 333 #define DDRPHY_REG_MISC_PHY_RGS_STBEN_B0 (DDRPHY_NAO_BASE_ADDRESS + 0x0198) 334 #define MISC_PHY_RGS_STBEN_B0_AD_RX_ARDQ0_STBEN_B0 Fld(9, 0) //[8:0] 335 #define MISC_PHY_RGS_STBEN_B0_AD_RX_ARDQS0_STBEN_LEAD_B0 Fld(1, 16) //[16:16] 336 #define MISC_PHY_RGS_STBEN_B0_AD_RX_ARDQS0_STBEN_LAG_B0 Fld(1, 17) //[17:17] 337 #define MISC_PHY_RGS_STBEN_B0_AD_ARDLL_PD_EN_B0 Fld(1, 18) //[18:18] 338 #define MISC_PHY_RGS_STBEN_B0_AD_ARDLL_MON_B0 Fld(8, 24) //[31:24] 339 340 #define DDRPHY_REG_MISC_PHY_RGS_STBEN_B1 (DDRPHY_NAO_BASE_ADDRESS + 0x019C) 341 #define MISC_PHY_RGS_STBEN_B1_AD_RX_ARDQ0_STBEN_B1 Fld(9, 0) //[8:0] 342 #define MISC_PHY_RGS_STBEN_B1_AD_RX_ARDQS0_STBEN_LEAD_B1 Fld(1, 16) //[16:16] 343 #define MISC_PHY_RGS_STBEN_B1_AD_RX_ARDQS0_STBEN_LAG_B1 Fld(1, 17) //[17:17] 344 #define MISC_PHY_RGS_STBEN_B1_AD_ARDLL_PD_EN_B1 Fld(1, 18) //[18:18] 345 #define MISC_PHY_RGS_STBEN_B1_AD_ARDLL_MON_B1 Fld(8, 24) //[31:24] 346 347 #define DDRPHY_REG_MISC_PHY_RGS_STBEN_CMD (DDRPHY_NAO_BASE_ADDRESS + 0x01A0) 348 #define MISC_PHY_RGS_STBEN_CMD_AD_RX_ARCA0_STBEN Fld(9, 0) //[8:0] 349 #define MISC_PHY_RGS_STBEN_CMD_AD_RX_ARCLK_STBEN_LEAD Fld(1, 16) //[16:16] 350 #define MISC_PHY_RGS_STBEN_CMD_AD_RX_ARCLK_STBEN_LAG Fld(1, 17) //[17:17] 351 #define MISC_PHY_RGS_STBEN_CMD_AD_ARDLL_PD_EN_CA Fld(1, 18) //[18:18] 352 #define MISC_PHY_RGS_STBEN_CMD_AD_ARDLL_MON_CA Fld(8, 24) //[31:24] 353 354 #define DDRPHY_REG_MISC_PHY_PICG_MON_S0 (DDRPHY_NAO_BASE_ADDRESS + 0x01A4) 355 #define MISC_PHY_PICG_MON_S0_PICG_MON_S0 Fld(32, 0) //[31:0] 356 357 #define DDRPHY_REG_MISC_PHY_PICG_MON_S1 (DDRPHY_NAO_BASE_ADDRESS + 0x01A8) 358 #define MISC_PHY_PICG_MON_S1_PICG_MON_S1 Fld(32, 0) //[31:0] 359 360 #define DDRPHY_REG_MISC_PHY_PICG_MON_S2 (DDRPHY_NAO_BASE_ADDRESS + 0x01AC) 361 #define MISC_PHY_PICG_MON_S2_PICG_MON_S2 Fld(32, 0) //[31:0] 362 363 #define DDRPHY_REG_MISC_PHY_PICG_MON_S3 (DDRPHY_NAO_BASE_ADDRESS + 0x01B0) 364 #define MISC_PHY_PICG_MON_S3_PICG_MON_S3 Fld(32, 0) //[31:0] 365 366 #define DDRPHY_REG_MISC_PHY_PICG_MON_S4 (DDRPHY_NAO_BASE_ADDRESS + 0x01B4) 367 #define MISC_PHY_PICG_MON_S4_PICG_MON_S4 Fld(32, 0) //[31:0] 368 369 #define DDRPHY_REG_MISC_PHY_PICG_MON_S5 (DDRPHY_NAO_BASE_ADDRESS + 0x01B8) 370 #define MISC_PHY_PICG_MON_S5_PICG_MON_S5 Fld(32, 0) //[31:0] 371 372 #define DDRPHY_REG_MISC_PHY_PICG_MON_S6 (DDRPHY_NAO_BASE_ADDRESS + 0x01BC) 373 #define MISC_PHY_PICG_MON_S6_PICG_MON_S6 Fld(32, 0) //[31:0] 374 375 #define DDRPHY_REG_MISC_PHY_PICG_MON_S7 (DDRPHY_NAO_BASE_ADDRESS + 0x01C0) 376 #define MISC_PHY_PICG_MON_S7_PICG_MON_S7 Fld(32, 0) //[31:0] 377 378 #define DDRPHY_REG_MISC_PHY_PICG_MON_S8 (DDRPHY_NAO_BASE_ADDRESS + 0x01C4) 379 #define MISC_PHY_PICG_MON_S8_PICG_MON_S8 Fld(32, 0) //[31:0] 380 381 #define DDRPHY_REG_MISC_MBIST_STATUS (DDRPHY_NAO_BASE_ADDRESS + 0x01C8) 382 #define MISC_MBIST_STATUS_MISC_MBIST_PRE_RP_FAIL Fld(1, 0) //[0:0] 383 #define MISC_MBIST_STATUS_MISC_MBIST_PRE_RP_OK Fld(1, 1) //[1:1] 384 #define MISC_MBIST_STATUS_MISC_MBIST_PRE_FUSE Fld(7, 2) //[8:2] 385 386 #define DDRPHY_REG_MISC_MBIST_STATUS2 (DDRPHY_NAO_BASE_ADDRESS + 0x01CC) 387 #define MISC_MBIST_STATUS2_MISC_MBIST_FAIL Fld(1, 0) //[0:0] 388 #define MISC_MBIST_STATUS2_MISC_MBIST_DONE Fld(1, 1) //[1:1] 389 390 #define DDRPHY_REG_MISC_IMPCAL_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x01D0) 391 #define MISC_IMPCAL_STATUS1_DRVNDQS_SAVE_1 Fld(5, 0) //[4:0] 392 #define MISC_IMPCAL_STATUS1_DRVPDQS_SAVE_1 Fld(5, 8) //[12:8] 393 #define MISC_IMPCAL_STATUS1_ODTNDQS_SAVE_1 Fld(5, 16) //[20:16] 394 395 #define DDRPHY_REG_MISC_IMPCAL_STATUS2 (DDRPHY_NAO_BASE_ADDRESS + 0x01D4) 396 #define MISC_IMPCAL_STATUS2_DRVNDQS_SAVE_2 Fld(5, 0) //[4:0] 397 #define MISC_IMPCAL_STATUS2_DRVPDQS_SAVE_2 Fld(5, 8) //[12:8] 398 #define MISC_IMPCAL_STATUS2_ODTNDQS_SAVE_2 Fld(5, 16) //[20:16] 399 400 #define DDRPHY_REG_MISC_IMPCAL_STATUS3 (DDRPHY_NAO_BASE_ADDRESS + 0x01D8) 401 #define MISC_IMPCAL_STATUS3_DRVNDQ_SAVE_1 Fld(5, 0) //[4:0] 402 #define MISC_IMPCAL_STATUS3_DRVPDQ_SAVE_1 Fld(5, 8) //[12:8] 403 #define MISC_IMPCAL_STATUS3_ODTNDQ_SAVE_1 Fld(5, 16) //[20:16] 404 405 #define DDRPHY_REG_MISC_IMPCAL_STATUS4 (DDRPHY_NAO_BASE_ADDRESS + 0x01DC) 406 #define MISC_IMPCAL_STATUS4_DRVNDQ_SAVE_2 Fld(5, 0) //[4:0] 407 #define MISC_IMPCAL_STATUS4_DRVPDQ_SAVE_2 Fld(5, 8) //[12:8] 408 #define MISC_IMPCAL_STATUS4_ODTNDQ_SAVE_2 Fld(5, 16) //[20:16] 409 410 #define DDRPHY_REG_MISC_IMPCAL_STATUS5 (DDRPHY_NAO_BASE_ADDRESS + 0x01E0) 411 #define MISC_IMPCAL_STATUS5_DRVNWCK_SAVE_1 Fld(5, 0) //[4:0] 412 #define MISC_IMPCAL_STATUS5_DRVPWCK_SAVE_1 Fld(5, 8) //[12:8] 413 #define MISC_IMPCAL_STATUS5_DRVNWCK_SAVE_2 Fld(5, 16) //[20:16] 414 #define MISC_IMPCAL_STATUS5_DRVPWCK_SAVE_2 Fld(5, 24) //[28:24] 415 416 #define DDRPHY_REG_MISC_IMPCAL_STATUS6 (DDRPHY_NAO_BASE_ADDRESS + 0x01E4) 417 #define MISC_IMPCAL_STATUS6_DRVNCS_SAVE_1 Fld(5, 0) //[4:0] 418 #define MISC_IMPCAL_STATUS6_DRVPCS_SAVE_1 Fld(5, 8) //[12:8] 419 420 #define DDRPHY_REG_MISC_IMPCAL_STATUS7 (DDRPHY_NAO_BASE_ADDRESS + 0x01E8) 421 #define MISC_IMPCAL_STATUS7_DRVNCMD_SAVE_1 Fld(5, 0) //[4:0] 422 #define MISC_IMPCAL_STATUS7_DRVPCMD_SAVE_1 Fld(5, 8) //[12:8] 423 #define MISC_IMPCAL_STATUS7_ODTNCMD_SAVE_1 Fld(5, 16) //[20:16] 424 425 #define DDRPHY_REG_MISC_IMPCAL_STATUS8 (DDRPHY_NAO_BASE_ADDRESS + 0x01EC) 426 #define MISC_IMPCAL_STATUS8_DRVNCMD_SAVE_2 Fld(5, 0) //[4:0] 427 #define MISC_IMPCAL_STATUS8_DRVPCMD_SAVE_2 Fld(5, 8) //[12:8] 428 #define MISC_IMPCAL_STATUS8_ODTNCMD_SAVE_2 Fld(5, 16) //[20:16] 429 430 #define DDRPHY_REG_MISC_IMPCAL_STATUS9 (DDRPHY_NAO_BASE_ADDRESS + 0x01F4) 431 #define MISC_IMPCAL_STATUS9_IMPCAL_N_ERROR Fld(1, 0) //[0:0] 432 #define MISC_IMPCAL_STATUS9_IMPCAL_P_ERROR Fld(1, 1) //[1:1] 433 #define MISC_IMPCAL_STATUS9_DRVNDQC_SAVE_1 Fld(5, 10) //[14:10] 434 #define MISC_IMPCAL_STATUS9_DRVPDQC_SAVE_1 Fld(5, 15) //[19:15] 435 #define MISC_IMPCAL_STATUS9_DRVNDQC_SAVE_2 Fld(5, 20) //[24:20] 436 #define MISC_IMPCAL_STATUS9_DRVPDQC_SAVE_2 Fld(5, 25) //[29:25] 437 438 #define DDRPHY_REG_MISC_STA_TOGLB0 (DDRPHY_NAO_BASE_ADDRESS + 0x01F8) 439 #define MISC_STA_TOGLB0_STA_TOGLB_DONE Fld(32, 0) //[31:0] 440 441 #define DDRPHY_REG_MISC_STA_TOGLB1 (DDRPHY_NAO_BASE_ADDRESS + 0x01FC) 442 #define MISC_STA_TOGLB1_STA_TOGLB_FAIL Fld(32, 0) //[31:0] 443 444 #define DDRPHY_REG_MISC_STA_EXTLB_DBG0 (DDRPHY_NAO_BASE_ADDRESS + 0x0214) 445 #define MISC_STA_EXTLB_DBG0_STA_EXTLB_DVS_LEAD_0TO1 Fld(32, 0) //[31:0] 446 447 #define DDRPHY_REG_MISC_STA_EXTLB_DBG1 (DDRPHY_NAO_BASE_ADDRESS + 0x0218) 448 #define MISC_STA_EXTLB_DBG1_STA_EXTLB_DVS_LEAD_1TO0 Fld(32, 0) //[31:0] 449 450 #define DDRPHY_REG_MISC_STA_EXTLB_DBG2 (DDRPHY_NAO_BASE_ADDRESS + 0x021C) 451 #define MISC_STA_EXTLB_DBG2_STA_EXTLB_DVS_LAG_0TO1 Fld(32, 0) //[31:0] 452 453 #define DDRPHY_REG_MISC_STA_EXTLB_DBG3 (DDRPHY_NAO_BASE_ADDRESS + 0x0220) 454 #define MISC_STA_EXTLB_DBG3_STA_EXTLB_DVS_LAG_1TO0 Fld(32, 0) //[31:0] 455 456 #define DDRPHY_REG_MISC_DUTY_TOGGLE_CNT (DDRPHY_NAO_BASE_ADDRESS + 0x0224) 457 #define MISC_DUTY_TOGGLE_CNT_TOGGLE_CNT Fld(32, 0) //[31:0] 458 459 #define DDRPHY_REG_MISC_DUTY_DQS0_ERR_CNT (DDRPHY_NAO_BASE_ADDRESS + 0x0228) 460 #define MISC_DUTY_DQS0_ERR_CNT_DQS0_ERR_CNT Fld(32, 0) //[31:0] 461 462 #define DDRPHY_REG_MISC_DUTY_DQ_ERR_CNT0 (DDRPHY_NAO_BASE_ADDRESS + 0x022C) 463 #define MISC_DUTY_DQ_ERR_CNT0_DQ_ERR_CNT0 Fld(32, 0) //[31:0] 464 465 #define DDRPHY_REG_MISC_DUTY_DQS1_ERR_CNT (DDRPHY_NAO_BASE_ADDRESS + 0x0230) 466 #define MISC_DUTY_DQS1_ERR_CNT_DQS1_ERR_CNT Fld(32, 0) //[31:0] 467 468 #define DDRPHY_REG_MISC_DUTY_DQ_ERR_CNT1 (DDRPHY_NAO_BASE_ADDRESS + 0x0234) 469 #define MISC_DUTY_DQ_ERR_CNT1_DQ_ERR_CNT1 Fld(32, 0) //[31:0] 470 471 #define DDRPHY_REG_MISC_DUTY_DQS2_ERR_CNT (DDRPHY_NAO_BASE_ADDRESS + 0x0238) 472 #define MISC_DUTY_DQS2_ERR_CNT_DQS2_ERR_CNT Fld(32, 0) //[31:0] 473 474 #define DDRPHY_REG_MISC_DUTY_DQ_ERR_CNT2 (DDRPHY_NAO_BASE_ADDRESS + 0x023C) 475 #define MISC_DUTY_DQ_ERR_CNT2_DQ_ERR_CNT2 Fld(32, 0) //[31:0] 476 477 #define DDRPHY_REG_MISC_DUTY_DQS3_ERR_CNT (DDRPHY_NAO_BASE_ADDRESS + 0x0240) 478 #define MISC_DUTY_DQS3_ERR_CNT_DQS3_ERR_CNT Fld(32, 0) //[31:0] 479 480 #define DDRPHY_REG_MISC_DUTY_DQ_ERR_CNT3 (DDRPHY_NAO_BASE_ADDRESS + 0x0244) 481 #define MISC_DUTY_DQ_ERR_CNT3_DQ_ERR_CNT3 Fld(32, 0) //[31:0] 482 483 #define DDRPHY_REG_MISC_JMETER_ST0 (DDRPHY_NAO_BASE_ADDRESS + 0x0248) 484 #define MISC_JMETER_ST0_JMTR_DONE Fld(1, 31) //[31:31] 485 486 #define DDRPHY_REG_MISC_JMETER_ST1 (DDRPHY_NAO_BASE_ADDRESS + 0x024C) 487 #define MISC_JMETER_ST1_ZEROS_CNT Fld(16, 0) //[15:0] 488 #define MISC_JMETER_ST1_ONES_CNT Fld(16, 16) //[31:16] 489 490 #define DDRPHY_REG_MISC_EMI_LPBK0 (DDRPHY_NAO_BASE_ADDRESS + 0x0250) 491 #define MISC_EMI_LPBK0_RDATA_DQ0_B0 Fld(16, 0) //[15:0] 492 #define MISC_EMI_LPBK0_RDATA_DQ1_B0 Fld(16, 16) //[31:16] 493 494 #define DDRPHY_REG_MISC_EMI_LPBK1 (DDRPHY_NAO_BASE_ADDRESS + 0x0254) 495 #define MISC_EMI_LPBK1_RDATA_DQ2_B0 Fld(16, 0) //[15:0] 496 #define MISC_EMI_LPBK1_RDATA_DQ3_B0 Fld(16, 16) //[31:16] 497 498 #define DDRPHY_REG_MISC_EMI_LPBK2 (DDRPHY_NAO_BASE_ADDRESS + 0x0258) 499 #define MISC_EMI_LPBK2_RDATA_DQ4_B0 Fld(16, 0) //[15:0] 500 #define MISC_EMI_LPBK2_RDATA_DQ5_B0 Fld(16, 16) //[31:16] 501 502 #define DDRPHY_REG_MISC_EMI_LPBK3 (DDRPHY_NAO_BASE_ADDRESS + 0x025C) 503 #define MISC_EMI_LPBK3_RDATA_DQ6_B0 Fld(16, 0) //[15:0] 504 #define MISC_EMI_LPBK3_RDATA_DQ7_B0 Fld(16, 16) //[31:16] 505 506 #define DDRPHY_REG_MISC_EMI_LPBK4 (DDRPHY_NAO_BASE_ADDRESS + 0x0260) 507 #define MISC_EMI_LPBK4_RDATA_DQ0_B1 Fld(16, 0) //[15:0] 508 #define MISC_EMI_LPBK4_RDATA_DQ1_B1 Fld(16, 16) //[31:16] 509 510 #define DDRPHY_REG_MISC_EMI_LPBK5 (DDRPHY_NAO_BASE_ADDRESS + 0x0264) 511 #define MISC_EMI_LPBK5_RDATA_DQ2_B1 Fld(16, 0) //[15:0] 512 #define MISC_EMI_LPBK5_RDATA_DQ3_B1 Fld(16, 16) //[31:16] 513 514 #define DDRPHY_REG_MISC_EMI_LPBK6 (DDRPHY_NAO_BASE_ADDRESS + 0x0268) 515 #define MISC_EMI_LPBK6_RDATA_DQ4_B1 Fld(16, 0) //[15:0] 516 #define MISC_EMI_LPBK6_RDATA_DQ5_B1 Fld(16, 16) //[31:16] 517 518 #define DDRPHY_REG_MISC_EMI_LPBK7 (DDRPHY_NAO_BASE_ADDRESS + 0x026C) 519 #define MISC_EMI_LPBK7_RDATA_DQ6_B1 Fld(16, 0) //[15:0] 520 #define MISC_EMI_LPBK7_RDATA_DQ7_B1 Fld(16, 16) //[31:16] 521 522 #define DDRPHY_REG_MISC_FT_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0270) 523 #define MISC_FT_STATUS0_AD_RX_ARDQ_DVS_R_LAG_B1 Fld(8, 0) //[7:0] 524 #define MISC_FT_STATUS0_AD_RX_ARDQ_DVS_R_LEAD_B1 Fld(8, 8) //[15:8] 525 #define MISC_FT_STATUS0_AD_RX_ARDQ_DVS_R_LAG_B0 Fld(8, 16) //[23:16] 526 #define MISC_FT_STATUS0_AD_RX_ARDQ_DVS_R_LEAD_B0 Fld(8, 24) //[31:24] 527 528 #define DDRPHY_REG_MISC_FT_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x0274) 529 #define MISC_FT_STATUS1_AD_RX_ARDQ_DVS_F_LAG_B1 Fld(8, 0) //[7:0] 530 #define MISC_FT_STATUS1_AD_RX_ARDQ_DVS_F_LEAD_B1 Fld(8, 8) //[15:8] 531 #define MISC_FT_STATUS1_AD_RX_ARDQ_DVS_F_LAG_B0 Fld(8, 16) //[23:16] 532 #define MISC_FT_STATUS1_AD_RX_ARDQ_DVS_F_LEAD_B0 Fld(8, 24) //[31:24] 533 534 #define DDRPHY_REG_MISC_FT_STATUS2 (DDRPHY_NAO_BASE_ADDRESS + 0x0278) 535 #define MISC_FT_STATUS2_AD_RRESETB_O Fld(1, 0) //[0:0] 536 537 #define DDRPHY_REG_MISC_FT_STATUS3 (DDRPHY_NAO_BASE_ADDRESS + 0x027C) 538 #define MISC_FT_STATUS3_AD_RX_ARCA0_DVS_R_LAG Fld(1, 0) //[0:0] 539 #define MISC_FT_STATUS3_AD_RX_ARCA1_DVS_R_LAG Fld(1, 1) //[1:1] 540 #define MISC_FT_STATUS3_AD_RX_ARCA2_DVS_R_LAG Fld(1, 2) //[2:2] 541 #define MISC_FT_STATUS3_AD_RX_ARCA3_DVS_R_LAG Fld(1, 3) //[3:3] 542 #define MISC_FT_STATUS3_AD_RX_ARCA4_DVS_R_LAG Fld(1, 4) //[4:4] 543 #define MISC_FT_STATUS3_AD_RX_ARCA5_DVS_R_LAG Fld(1, 5) //[5:5] 544 #define MISC_FT_STATUS3_AD_RX_ARCKE0_DVS_R_LAG Fld(1, 6) //[6:6] 545 #define MISC_FT_STATUS3_AD_RX_ARCKE1_DVS_R_LAG Fld(1, 7) //[7:7] 546 #define MISC_FT_STATUS3_AD_RX_ARCS0_DVS_R_LAG Fld(1, 8) //[8:8] 547 #define MISC_FT_STATUS3_AD_RX_ARCS1_DVS_R_LAG Fld(1, 9) //[9:9] 548 #define MISC_FT_STATUS3_AD_RX_ARCA0_DVS_R_LEAD Fld(1, 16) //[16:16] 549 #define MISC_FT_STATUS3_AD_RX_ARCA1_DVS_R_LEAD Fld(1, 17) //[17:17] 550 #define MISC_FT_STATUS3_AD_RX_ARCA2_DVS_R_LEAD Fld(1, 18) //[18:18] 551 #define MISC_FT_STATUS3_AD_RX_ARCA3_DVS_R_LEAD Fld(1, 19) //[19:19] 552 #define MISC_FT_STATUS3_AD_RX_ARCA4_DVS_R_LEAD Fld(1, 20) //[20:20] 553 #define MISC_FT_STATUS3_AD_RX_ARCA5_DVS_R_LEAD Fld(1, 21) //[21:21] 554 #define MISC_FT_STATUS3_AD_RX_ARCKE0_DVS_R_LEAD Fld(1, 22) //[22:22] 555 #define MISC_FT_STATUS3_AD_RX_ARCKE1_DVS_R_LEAD Fld(1, 23) //[23:23] 556 #define MISC_FT_STATUS3_AD_RX_ARCS0_DVS_R_LEAD Fld(1, 24) //[24:24] 557 #define MISC_FT_STATUS3_AD_RX_ARCS1_DVS_R_LEAD Fld(1, 25) //[25:25] 558 559 #define DDRPHY_REG_MISC_FT_STATUS4 (DDRPHY_NAO_BASE_ADDRESS + 0x0280) 560 #define MISC_FT_STATUS4_AD_RX_ARCA0_DVS_F_LAG Fld(1, 0) //[0:0] 561 #define MISC_FT_STATUS4_AD_RX_ARCA1_DVS_F_LAG Fld(1, 1) //[1:1] 562 #define MISC_FT_STATUS4_AD_RX_ARCA2_DVS_F_LAG Fld(1, 2) //[2:2] 563 #define MISC_FT_STATUS4_AD_RX_ARCA3_DVS_F_LAG Fld(1, 3) //[3:3] 564 #define MISC_FT_STATUS4_AD_RX_ARCA4_DVS_F_LAG Fld(1, 4) //[4:4] 565 #define MISC_FT_STATUS4_AD_RX_ARCA5_DVS_F_LAG Fld(1, 5) //[5:5] 566 #define MISC_FT_STATUS4_AD_RX_ARCKE0_DVS_F_LAG Fld(1, 6) //[6:6] 567 #define MISC_FT_STATUS4_AD_RX_ARCKE1_DVS_F_LAG Fld(1, 7) //[7:7] 568 #define MISC_FT_STATUS4_AD_RX_ARCS0_DVS_F_LAG Fld(1, 8) //[8:8] 569 #define MISC_FT_STATUS4_AD_RX_ARCS1_DVS_F_LAG Fld(1, 9) //[9:9] 570 #define MISC_FT_STATUS4_AD_RX_ARCA0_DVS_F_LEAD Fld(1, 16) //[16:16] 571 #define MISC_FT_STATUS4_AD_RX_ARCA1_DVS_F_LEAD Fld(1, 17) //[17:17] 572 #define MISC_FT_STATUS4_AD_RX_ARCA2_DVS_F_LEAD Fld(1, 18) //[18:18] 573 #define MISC_FT_STATUS4_AD_RX_ARCA3_DVS_F_LEAD Fld(1, 19) //[19:19] 574 #define MISC_FT_STATUS4_AD_RX_ARCA4_DVS_F_LEAD Fld(1, 20) //[20:20] 575 #define MISC_FT_STATUS4_AD_RX_ARCA5_DVS_F_LEAD Fld(1, 21) //[21:21] 576 #define MISC_FT_STATUS4_AD_RX_ARCKE0_DVS_F_LEAD Fld(1, 22) //[22:22] 577 #define MISC_FT_STATUS4_AD_RX_ARCKE1_DVS_F_LEAD Fld(1, 23) //[23:23] 578 #define MISC_FT_STATUS4_AD_RX_ARCS0_DVS_F_LEAD Fld(1, 24) //[24:24] 579 #define MISC_FT_STATUS4_AD_RX_ARCS1_DVS_F_LEAD Fld(1, 25) //[25:25] 580 581 #define DDRPHY_REG_MISC_STA_TOGLB2 (DDRPHY_NAO_BASE_ADDRESS + 0x0284) 582 #define MISC_STA_TOGLB2_STA_TOGLB_PUHI_TIMEOUT Fld(32, 0) //[31:0] 583 584 #define DDRPHY_REG_MISC_STA_TOGLB3 (DDRPHY_NAO_BASE_ADDRESS + 0x0288) 585 #define MISC_STA_TOGLB3_STA_TOGLB_PULO_TIMEOUT Fld(32, 0) //[31:0] 586 587 #define DDRPHY_REG_MISC_STA_EXTLB3 (DDRPHY_NAO_BASE_ADDRESS + 0x028C) 588 #define MISC_STA_EXTLB3_STA_EXTLB_RISING_FAIL Fld(32, 0) //[31:0] 589 590 #define DDRPHY_REG_MISC_STA_EXTLB4 (DDRPHY_NAO_BASE_ADDRESS + 0x0290) 591 #define MISC_STA_EXTLB4_STA_EXTLB_FALLING_FAIL Fld(32, 0) //[31:0] 592 593 #define DDRPHY_REG_MISC_STA_EXTLB5 (DDRPHY_NAO_BASE_ADDRESS + 0x0294) 594 #define MISC_STA_EXTLB5_STA_EXTLB_DBG_INFO2 Fld(32, 0) //[31:0] 595 596 #define DDRPHY_REG_DEBUG_APHY_RX_CTL (DDRPHY_NAO_BASE_ADDRESS + 0x0400) 597 #define DEBUG_APHY_RX_CTL_DEBUG_STATUS_APHY_RX_CTL Fld(32, 0) //[31:0] 598 599 #define DDRPHY_REG_GATING_ERR_INFOR (DDRPHY_NAO_BASE_ADDRESS + 0x0410) 600 #define GATING_ERR_INFOR_STB_GATING_ERR Fld(1, 0) //[0:0] 601 #define GATING_ERR_INFOR_STBUPD_STOP Fld(1, 1) //[1:1] 602 #define GATING_ERR_INFOR_R_OTHER_SHU_GP_GATING_ERR Fld(2, 4) //[5:4] 603 #define GATING_ERR_INFOR_R_MPDIV_SHU_GP_GATING_ERR Fld(3, 8) //[10:8] 604 #define GATING_ERR_INFOR_GATING_ERR_INF_STATUS Fld(4, 16) //[19:16] 605 #define GATING_ERR_INFOR_GATING_ERR_PRE_SHU_ST Fld(4, 20) //[23:20] 606 #define GATING_ERR_INFOR_GATING_ERR_CUR_SHU_ST Fld(4, 24) //[27:24] 607 608 #define DDRPHY_REG_DEBUG_DQSIEN_B0 (DDRPHY_NAO_BASE_ADDRESS + 0x0414) 609 #define DEBUG_DQSIEN_B0_DQSIEN_PICG_HEAD_ERR_FLAG_B0_RK0 Fld(1, 0) //[0:0] 610 #define DEBUG_DQSIEN_B0_STB_CNT_SHU_ST_ERR_FLAG_B0_RK0 Fld(1, 1) //[1:1] 611 #define DEBUG_DQSIEN_B0_DQSIEN_PICG_HEAD_ERR_FLAG_B0_RK1 Fld(1, 16) //[16:16] 612 #define DEBUG_DQSIEN_B0_STB_CNT_SHU_ST_ERR_FLAG_B0_RK1 Fld(1, 17) //[17:17] 613 614 #define DDRPHY_REG_DEBUG_DQSIEN_B1 (DDRPHY_NAO_BASE_ADDRESS + 0x0418) 615 #define DEBUG_DQSIEN_B1_DQSIEN_PICG_HEAD_ERR_FLAG_B1_RK0 Fld(1, 0) //[0:0] 616 #define DEBUG_DQSIEN_B1_STB_CNT_SHU_ST_ERR_FLAG_B1_RK0 Fld(1, 1) //[1:1] 617 #define DEBUG_DQSIEN_B1_DQSIEN_PICG_HEAD_ERR_FLAG_B1_RK1 Fld(1, 16) //[16:16] 618 #define DEBUG_DQSIEN_B1_STB_CNT_SHU_ST_ERR_FLAG_B1_RK1 Fld(1, 17) //[17:17] 619 620 #define DDRPHY_REG_DEBUG_DQSIEN_CA (DDRPHY_NAO_BASE_ADDRESS + 0x041C) 621 #define DEBUG_DQSIEN_CA_DQSIEN_PICG_HEAD_ERR_FLAG_CA_RK0 Fld(1, 0) //[0:0] 622 #define DEBUG_DQSIEN_CA_STB_CNT_SHU_ST_ERR_FLAG_CA_RK0 Fld(1, 1) //[1:1] 623 #define DEBUG_DQSIEN_CA_DQSIEN_PICG_HEAD_ERR_FLAG_CA_RK1 Fld(1, 16) //[16:16] 624 #define DEBUG_DQSIEN_CA_STB_CNT_SHU_ST_ERR_FLAG_CA_RK1 Fld(1, 17) //[17:17] 625 626 #define DDRPHY_REG_GATING_ERR_LATCH_DLY_B0_RK0 (DDRPHY_NAO_BASE_ADDRESS + 0x0420) 627 #define GATING_ERR_LATCH_DLY_B0_RK0_DQSIEN0_PI_DLY_RK0 Fld(7, 0) //[6:0] 628 #define GATING_ERR_LATCH_DLY_B0_RK0_DQSIEN0_UI_P0_DLY_RK0 Fld(8, 16) //[23:16] 629 #define GATING_ERR_LATCH_DLY_B0_RK0_DQSIEN0_UI_P1_DLY_RK0 Fld(8, 24) //[31:24] 630 631 #define DDRPHY_REG_GATING_ERR_LATCH_DLY_B1_RK0 (DDRPHY_NAO_BASE_ADDRESS + 0x0424) 632 #define GATING_ERR_LATCH_DLY_B1_RK0_DQSIEN1_PI_DLY_RK0 Fld(7, 0) //[6:0] 633 #define GATING_ERR_LATCH_DLY_B1_RK0_DQSIEN1_UI_P0_DLY_RK0 Fld(8, 16) //[23:16] 634 #define GATING_ERR_LATCH_DLY_B1_RK0_DQSIEN1_UI_P1_DLY_RK0 Fld(8, 24) //[31:24] 635 636 #define DDRPHY_REG_GATING_ERR_LATCH_DLY_CA_RK0 (DDRPHY_NAO_BASE_ADDRESS + 0x0428) 637 #define GATING_ERR_LATCH_DLY_CA_RK0_DQSIEN2_PI_DLY_RK0 Fld(7, 0) //[6:0] 638 #define GATING_ERR_LATCH_DLY_CA_RK0_DQSIEN2_UI_P0_DLY_RK0 Fld(8, 16) //[23:16] 639 #define GATING_ERR_LATCH_DLY_CA_RK0_DQSIEN2_UI_P1_DLY_RK0 Fld(8, 24) //[31:24] 640 641 #define DDRPHY_REG_GATING_ERR_LATCH_DLY_B0_RK1 (DDRPHY_NAO_BASE_ADDRESS + 0x0430) 642 #define GATING_ERR_LATCH_DLY_B0_RK1_DQSIEN0_PI_DLY_RK1 Fld(7, 0) //[6:0] 643 #define GATING_ERR_LATCH_DLY_B0_RK1_DQSIEN0_UI_P0_DLY_RK1 Fld(8, 16) //[23:16] 644 #define GATING_ERR_LATCH_DLY_B0_RK1_DQSIEN0_UI_P1_DLY_RK1 Fld(8, 24) //[31:24] 645 646 #define DDRPHY_REG_GATING_ERR_LATCH_DLY_B1_RK1 (DDRPHY_NAO_BASE_ADDRESS + 0x0434) 647 #define GATING_ERR_LATCH_DLY_B1_RK1_DQSIEN1_PI_DLY_RK1 Fld(7, 0) //[6:0] 648 #define GATING_ERR_LATCH_DLY_B1_RK1_DQSIEN1_UI_P0_DLY_RK1 Fld(8, 16) //[23:16] 649 #define GATING_ERR_LATCH_DLY_B1_RK1_DQSIEN1_UI_P1_DLY_RK1 Fld(8, 24) //[31:24] 650 651 #define DDRPHY_REG_GATING_ERR_LATCH_DLY_CA_RK1 (DDRPHY_NAO_BASE_ADDRESS + 0x0438) 652 #define GATING_ERR_LATCH_DLY_CA_RK1_DQSIEN2_PI_DLY_RK1 Fld(7, 0) //[6:0] 653 #define GATING_ERR_LATCH_DLY_CA_RK1_DQSIEN2_UI_P0_DLY_RK1 Fld(8, 16) //[23:16] 654 #define GATING_ERR_LATCH_DLY_CA_RK1_DQSIEN2_UI_P1_DLY_RK1 Fld(8, 24) //[31:24] 655 656 #define DDRPHY_REG_DEBUG_RODT_CTL (DDRPHY_NAO_BASE_ADDRESS + 0x0440) 657 #define DEBUG_RODT_CTL_DEBUG_STATUS_RODTCTL Fld(32, 0) //[31:0] 658 659 #define DDRPHY_REG_CAL_DQSG_CNT_B0 (DDRPHY_NAO_BASE_ADDRESS + 0x0500) 660 #define CAL_DQSG_CNT_B0_DQS_B0_F_GATING_COUNTER Fld(8, 0) //[7:0] 661 #define CAL_DQSG_CNT_B0_DQS_B0_R_GATING_COUNTER Fld(8, 8) //[15:8] 662 663 #define DDRPHY_REG_CAL_DQSG_CNT_B1 (DDRPHY_NAO_BASE_ADDRESS + 0x0504) 664 #define CAL_DQSG_CNT_B1_DQS_B1_F_GATING_COUNTER Fld(8, 0) //[7:0] 665 #define CAL_DQSG_CNT_B1_DQS_B1_R_GATING_COUNTER Fld(8, 8) //[15:8] 666 667 #define DDRPHY_REG_CAL_DQSG_CNT_CA (DDRPHY_NAO_BASE_ADDRESS + 0x0508) 668 #define CAL_DQSG_CNT_CA_DQS_CA_F_GATING_COUNTER Fld(8, 0) //[7:0] 669 #define CAL_DQSG_CNT_CA_DQS_CA_R_GATING_COUNTER Fld(8, 8) //[15:8] 670 671 #define DDRPHY_REG_DVFS_STATUS (DDRPHY_NAO_BASE_ADDRESS + 0x050C) 672 #define DVFS_STATUS_CUT_PHY_ST_SHU Fld(8, 0) //[7:0] 673 #define DVFS_STATUS_PLL_SEL Fld(1, 8) //[8:8] 674 #define DVFS_STATUS_MPDIV_SHU_GP Fld(3, 12) //[14:12] 675 #define DVFS_STATUS_OTHER_SHU_GP Fld(2, 16) //[17:16] 676 #define DVFS_STATUS_PICG_SHUFFLE Fld(1, 20) //[20:20] 677 #define DVFS_STATUS_SHUFFLE_PHY_STATE_START Fld(1, 21) //[21:21] 678 #define DVFS_STATUS_SHUFFLE_PHY_STATE_DONE Fld(1, 22) //[22:22] 679 #define DVFS_STATUS_SHUFFLE_PERIOD Fld(1, 23) //[23:23] 680 681 #define DDRPHY_REG_RX_AUTOK_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0510) 682 #define RX_AUTOK_STATUS0_RO_RX_CAL_FAIL Fld(1, 0) //[0:0] 683 #define RX_AUTOK_STATUS0_RO_RX_CAL_PASS Fld(1, 1) //[1:1] 684 #define RX_AUTOK_STATUS0_RO_RX_CAL_DONE Fld(1, 2) //[2:2] 685 #define RX_AUTOK_STATUS0_RO_RX_CAL_OUT_WIN1_LEN_ARDQX Fld(10, 4) //[13:4] 686 #define RX_AUTOK_STATUS0_RO_RX_CAL_OUT_WIN1_BEGIN_ARDQX Fld(11, 16) //[26:16] 687 688 #define DDRPHY_REG_RX_AUTOK_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x0514) 689 #define RX_AUTOK_STATUS1_RO_RX_CAL_OUT_WIN2_LEN_ARDQX Fld(10, 4) //[13:4] 690 #define RX_AUTOK_STATUS1_RO_RX_CAL_OUT_WIN2_BEGIN_ARDQX Fld(11, 16) //[26:16] 691 692 #define DDRPHY_REG_RX_AUTOK_STATUS2 (DDRPHY_NAO_BASE_ADDRESS + 0x0518) 693 #define RX_AUTOK_STATUS2_RO_RX_CAL_OUT_WIN3_LEN_ARDQX Fld(10, 4) //[13:4] 694 #define RX_AUTOK_STATUS2_RO_RX_CAL_OUT_WIN3_BEGIN_ARDQX Fld(11, 16) //[26:16] 695 696 #define DDRPHY_REG_RX_AUTOK_STATUS3 (DDRPHY_NAO_BASE_ADDRESS + 0x051C) 697 #define RX_AUTOK_STATUS3_RO_RX_CAL_OUT_WIN4_LEN_ARDQX Fld(10, 4) //[13:4] 698 #define RX_AUTOK_STATUS3_RO_RX_CAL_OUT_WIN4_BEGIN_ARDQX Fld(11, 16) //[26:16] 699 700 #define DDRPHY_REG_RX_AUTOK_STATUS4 (DDRPHY_NAO_BASE_ADDRESS + 0x0520) 701 #define RX_AUTOK_STATUS4_RO_RX_CAL_OUT_WIN5_LEN_ARDQX Fld(10, 4) //[13:4] 702 #define RX_AUTOK_STATUS4_RO_RX_CAL_OUT_WIN5_BEGIN_ARDQX Fld(11, 16) //[26:16] 703 704 #define DDRPHY_REG_RX_AUTOK_STATUS5 (DDRPHY_NAO_BASE_ADDRESS + 0x0524) 705 #define RX_AUTOK_STATUS5_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ0 Fld(10, 4) //[13:4] 706 #define RX_AUTOK_STATUS5_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ0 Fld(11, 16) //[26:16] 707 708 #define DDRPHY_REG_RX_AUTOK_STATUS6 (DDRPHY_NAO_BASE_ADDRESS + 0x0528) 709 #define RX_AUTOK_STATUS6_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ1 Fld(10, 4) //[13:4] 710 #define RX_AUTOK_STATUS6_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ1 Fld(11, 16) //[26:16] 711 712 #define DDRPHY_REG_RX_AUTOK_STATUS7 (DDRPHY_NAO_BASE_ADDRESS + 0x052C) 713 #define RX_AUTOK_STATUS7_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ2 Fld(10, 4) //[13:4] 714 #define RX_AUTOK_STATUS7_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ2 Fld(11, 16) //[26:16] 715 716 #define DDRPHY_REG_RX_AUTOK_STATUS8 (DDRPHY_NAO_BASE_ADDRESS + 0x0530) 717 #define RX_AUTOK_STATUS8_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ3 Fld(10, 4) //[13:4] 718 #define RX_AUTOK_STATUS8_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ3 Fld(11, 16) //[26:16] 719 720 #define DDRPHY_REG_RX_AUTOK_STATUS9 (DDRPHY_NAO_BASE_ADDRESS + 0x0534) 721 #define RX_AUTOK_STATUS9_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ4 Fld(10, 4) //[13:4] 722 #define RX_AUTOK_STATUS9_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ4 Fld(11, 16) //[26:16] 723 724 #define DDRPHY_REG_RX_AUTOK_STATUS10 (DDRPHY_NAO_BASE_ADDRESS + 0x0538) 725 #define RX_AUTOK_STATUS10_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ5 Fld(10, 4) //[13:4] 726 #define RX_AUTOK_STATUS10_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ5 Fld(11, 16) //[26:16] 727 728 #define DDRPHY_REG_RX_AUTOK_STATUS11 (DDRPHY_NAO_BASE_ADDRESS + 0x053C) 729 #define RX_AUTOK_STATUS11_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ6 Fld(10, 4) //[13:4] 730 #define RX_AUTOK_STATUS11_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ6 Fld(11, 16) //[26:16] 731 732 #define DDRPHY_REG_RX_AUTOK_STATUS12 (DDRPHY_NAO_BASE_ADDRESS + 0x0540) 733 #define RX_AUTOK_STATUS12_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ7 Fld(10, 4) //[13:4] 734 #define RX_AUTOK_STATUS12_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ7 Fld(11, 16) //[26:16] 735 736 #define DDRPHY_REG_RX_AUTOK_STATUS13 (DDRPHY_NAO_BASE_ADDRESS + 0x0544) 737 #define RX_AUTOK_STATUS13_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ8 Fld(10, 4) //[13:4] 738 #define RX_AUTOK_STATUS13_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ8 Fld(11, 16) //[26:16] 739 740 #define DDRPHY_REG_RX_AUTOK_STATUS14 (DDRPHY_NAO_BASE_ADDRESS + 0x0548) 741 #define RX_AUTOK_STATUS14_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ9 Fld(10, 4) //[13:4] 742 #define RX_AUTOK_STATUS14_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ9 Fld(11, 16) //[26:16] 743 744 #define DDRPHY_REG_RX_AUTOK_STATUS15 (DDRPHY_NAO_BASE_ADDRESS + 0x054C) 745 #define RX_AUTOK_STATUS15_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ10 Fld(10, 4) //[13:4] 746 #define RX_AUTOK_STATUS15_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ10 Fld(11, 16) //[26:16] 747 748 #define DDRPHY_REG_RX_AUTOK_STATUS16 (DDRPHY_NAO_BASE_ADDRESS + 0x0550) 749 #define RX_AUTOK_STATUS16_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ11 Fld(10, 4) //[13:4] 750 #define RX_AUTOK_STATUS16_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ11 Fld(11, 16) //[26:16] 751 752 #define DDRPHY_REG_RX_AUTOK_STATUS17 (DDRPHY_NAO_BASE_ADDRESS + 0x0554) 753 #define RX_AUTOK_STATUS17_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ12 Fld(10, 4) //[13:4] 754 #define RX_AUTOK_STATUS17_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ12 Fld(11, 16) //[26:16] 755 756 #define DDRPHY_REG_RX_AUTOK_STATUS18 (DDRPHY_NAO_BASE_ADDRESS + 0x0558) 757 #define RX_AUTOK_STATUS18_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ13 Fld(10, 4) //[13:4] 758 #define RX_AUTOK_STATUS18_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ13 Fld(11, 16) //[26:16] 759 760 #define DDRPHY_REG_RX_AUTOK_STATUS19 (DDRPHY_NAO_BASE_ADDRESS + 0x055C) 761 #define RX_AUTOK_STATUS19_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ14 Fld(10, 4) //[13:4] 762 #define RX_AUTOK_STATUS19_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ14 Fld(11, 16) //[26:16] 763 764 #define DDRPHY_REG_RX_AUTOK_STATUS20 (DDRPHY_NAO_BASE_ADDRESS + 0x0560) 765 #define RX_AUTOK_STATUS20_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ15 Fld(10, 4) //[13:4] 766 #define RX_AUTOK_STATUS20_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ15 Fld(11, 16) //[26:16] 767 768 #define DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0600) 769 #define DQSIEN_AUTOK_B0_RK0_STATUS0_DQSIEN_AUTOK_C__PI_B0_RK0 Fld(7, 0) //[6:0] 770 #define DQSIEN_AUTOK_B0_RK0_STATUS0_DQSIEN_AUTOK_C__UI_B0_RK0 Fld(4, 8) //[11:8] 771 #define DQSIEN_AUTOK_B0_RK0_STATUS0_DQSIEN_AUTOK_C_MCK_B0_RK0 Fld(4, 12) //[15:12] 772 #define DQSIEN_AUTOK_B0_RK0_STATUS0_AUTOK_DONE_B0_RK0 Fld(1, 16) //[16:16] 773 #define DQSIEN_AUTOK_B0_RK0_STATUS0_AUTOK_ERR_B0_RK0 Fld(1, 17) //[17:17] 774 775 #define DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x0604) 776 #define DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_R__PI_B0_RK0 Fld(7, 0) //[6:0] 777 #define DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_R__UI_B0_RK0 Fld(4, 8) //[11:8] 778 #define DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_R_MCK_B0_RK0 Fld(4, 12) //[15:12] 779 #define DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_L__PI_B0_RK0 Fld(7, 16) //[22:16] 780 #define DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_L__UI_B0_RK0 Fld(4, 24) //[27:24] 781 #define DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_L_MCK_B0_RK0 Fld(4, 28) //[31:28] 782 783 #define DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_DBG_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0608) 784 #define DQSIEN_AUTOK_B0_RK0_DBG_STATUS0_DBG_GATING_STATUS_0_B0_RK0 Fld(32, 0) //[31:0] 785 786 #define DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_DBG_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x060C) 787 #define DQSIEN_AUTOK_B0_RK0_DBG_STATUS1_DBG_GATING_STATUS_1_B0_RK0 Fld(32, 0) //[31:0] 788 789 #define DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_DBG_STATUS2 (DDRPHY_NAO_BASE_ADDRESS + 0x0610) 790 #define DQSIEN_AUTOK_B0_RK0_DBG_STATUS2_DBG_GATING_STATUS_2_B0_RK0 Fld(32, 0) //[31:0] 791 792 #define DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_DBG_STATUS3 (DDRPHY_NAO_BASE_ADDRESS + 0x0614) 793 #define DQSIEN_AUTOK_B0_RK0_DBG_STATUS3_DBG_GATING_STATUS_3_B0_RK0 Fld(32, 0) //[31:0] 794 795 #define DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_DBG_STATUS4 (DDRPHY_NAO_BASE_ADDRESS + 0x0618) 796 #define DQSIEN_AUTOK_B0_RK0_DBG_STATUS4_DBG_GATING_STATUS_4_B0_RK0 Fld(32, 0) //[31:0] 797 798 #define DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_DBG_STATUS5 (DDRPHY_NAO_BASE_ADDRESS + 0x061C) 799 #define DQSIEN_AUTOK_B0_RK0_DBG_STATUS5_DBG_GATING_STATUS_5_B0_RK0 Fld(32, 0) //[31:0] 800 801 #define DDRPHY_REG_DQSIEN_AUTOK_B0_RK1_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0620) 802 #define DQSIEN_AUTOK_B0_RK1_STATUS0_DQSIEN_AUTOK_C__PI_B0_RK1 Fld(7, 0) //[6:0] 803 #define DQSIEN_AUTOK_B0_RK1_STATUS0_DQSIEN_AUTOK_C__UI_B0_RK1 Fld(4, 8) //[11:8] 804 #define DQSIEN_AUTOK_B0_RK1_STATUS0_DQSIEN_AUTOK_C_MCK_B0_RK1 Fld(4, 12) //[15:12] 805 #define DQSIEN_AUTOK_B0_RK1_STATUS0_AUTOK_DONE_B0_RK1 Fld(1, 16) //[16:16] 806 #define DQSIEN_AUTOK_B0_RK1_STATUS0_AUTOK_ERR_B0_RK1 Fld(1, 17) //[17:17] 807 808 #define DDRPHY_REG_DQSIEN_AUTOK_B0_RK1_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x0624) 809 #define DQSIEN_AUTOK_B0_RK1_STATUS1_DQSIEN_AUTOK_R__PI_B0_RK1 Fld(7, 0) //[6:0] 810 #define DQSIEN_AUTOK_B0_RK1_STATUS1_DQSIEN_AUTOK_R__UI_B0_RK1 Fld(4, 8) //[11:8] 811 #define DQSIEN_AUTOK_B0_RK1_STATUS1_DQSIEN_AUTOK_R_MCK_B0_RK1 Fld(4, 12) //[15:12] 812 #define DQSIEN_AUTOK_B0_RK1_STATUS1_DQSIEN_AUTOK_L__PI_B0_RK1 Fld(7, 16) //[22:16] 813 #define DQSIEN_AUTOK_B0_RK1_STATUS1_DQSIEN_AUTOK_L__UI_B0_RK1 Fld(4, 24) //[27:24] 814 #define DQSIEN_AUTOK_B0_RK1_STATUS1_DQSIEN_AUTOK_L_MCK_B0_RK1 Fld(4, 28) //[31:28] 815 816 #define DDRPHY_REG_DQSIEN_AUTOK_B0_RK1_DBG_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0628) 817 #define DQSIEN_AUTOK_B0_RK1_DBG_STATUS0_DBG_GATING_STATUS_0_B0_RK1 Fld(32, 0) //[31:0] 818 819 #define DDRPHY_REG_DQSIEN_AUTOK_B0_RK1_DBG_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x062C) 820 #define DQSIEN_AUTOK_B0_RK1_DBG_STATUS1_DBG_GATING_STATUS_1_B0_RK1 Fld(32, 0) //[31:0] 821 822 #define DDRPHY_REG_DQSIEN_AUTOK_B0_RK1_DBG_STATUS2 (DDRPHY_NAO_BASE_ADDRESS + 0x0630) 823 #define DQSIEN_AUTOK_B0_RK1_DBG_STATUS2_DBG_GATING_STATUS_2_B0_RK1 Fld(32, 0) //[31:0] 824 825 #define DDRPHY_REG_DQSIEN_AUTOK_B0_RK1_DBG_STATUS3 (DDRPHY_NAO_BASE_ADDRESS + 0x0634) 826 #define DQSIEN_AUTOK_B0_RK1_DBG_STATUS3_DBG_GATING_STATUS_3_B0_RK1 Fld(32, 0) //[31:0] 827 828 #define DDRPHY_REG_DQSIEN_AUTOK_B0_RK1_DBG_STATUS4 (DDRPHY_NAO_BASE_ADDRESS + 0x0638) 829 #define DQSIEN_AUTOK_B0_RK1_DBG_STATUS4_DBG_GATING_STATUS_4_B0_RK1 Fld(32, 0) //[31:0] 830 831 #define DDRPHY_REG_DQSIEN_AUTOK_B0_RK1_DBG_STATUS5 (DDRPHY_NAO_BASE_ADDRESS + 0x063C) 832 #define DQSIEN_AUTOK_B0_RK1_DBG_STATUS5_DBG_GATING_STATUS_5_B0_RK1 Fld(32, 0) //[31:0] 833 834 #define DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0640) 835 #define DQSIEN_AUTOK_B1_RK0_STATUS0_DQSIEN_AUTOK_C__PI_B1_RK0 Fld(7, 0) //[6:0] 836 #define DQSIEN_AUTOK_B1_RK0_STATUS0_DQSIEN_AUTOK_C__UI_B1_RK0 Fld(4, 8) //[11:8] 837 #define DQSIEN_AUTOK_B1_RK0_STATUS0_DQSIEN_AUTOK_C_MCK_B1_RK0 Fld(4, 12) //[15:12] 838 #define DQSIEN_AUTOK_B1_RK0_STATUS0_AUTOK_DONE_B1_RK0 Fld(1, 16) //[16:16] 839 #define DQSIEN_AUTOK_B1_RK0_STATUS0_AUTOK_ERR_B1_RK0 Fld(1, 17) //[17:17] 840 841 #define DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x0644) 842 #define DQSIEN_AUTOK_B1_RK0_STATUS1_DQSIEN_AUTOK_R__PI_B1_RK0 Fld(7, 0) //[6:0] 843 #define DQSIEN_AUTOK_B1_RK0_STATUS1_DQSIEN_AUTOK_R__UI_B1_RK0 Fld(4, 8) //[11:8] 844 #define DQSIEN_AUTOK_B1_RK0_STATUS1_DQSIEN_AUTOK_R_MCK_B1_RK0 Fld(4, 12) //[15:12] 845 #define DQSIEN_AUTOK_B1_RK0_STATUS1_DQSIEN_AUTOK_L__PI_B1_RK0 Fld(7, 16) //[22:16] 846 #define DQSIEN_AUTOK_B1_RK0_STATUS1_DQSIEN_AUTOK_L__UI_B1_RK0 Fld(4, 24) //[27:24] 847 #define DQSIEN_AUTOK_B1_RK0_STATUS1_DQSIEN_AUTOK_L_MCK_B1_RK0 Fld(4, 28) //[31:28] 848 849 #define DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_DBG_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0648) 850 #define DQSIEN_AUTOK_B1_RK0_DBG_STATUS0_DBG_GATING_STATUS_0_B1_RK0 Fld(32, 0) //[31:0] 851 852 #define DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_DBG_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x064C) 853 #define DQSIEN_AUTOK_B1_RK0_DBG_STATUS1_DBG_GATING_STATUS_1_B1_RK0 Fld(32, 0) //[31:0] 854 855 #define DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_DBG_STATUS2 (DDRPHY_NAO_BASE_ADDRESS + 0x0650) 856 #define DQSIEN_AUTOK_B1_RK0_DBG_STATUS2_DBG_GATING_STATUS_2_B1_RK0 Fld(32, 0) //[31:0] 857 858 #define DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_DBG_STATUS3 (DDRPHY_NAO_BASE_ADDRESS + 0x0654) 859 #define DQSIEN_AUTOK_B1_RK0_DBG_STATUS3_DBG_GATING_STATUS_3_B1_RK0 Fld(32, 0) //[31:0] 860 861 #define DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_DBG_STATUS4 (DDRPHY_NAO_BASE_ADDRESS + 0x0658) 862 #define DQSIEN_AUTOK_B1_RK0_DBG_STATUS4_DBG_GATING_STATUS_4_B1_RK0 Fld(32, 0) //[31:0] 863 864 #define DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_DBG_STATUS5 (DDRPHY_NAO_BASE_ADDRESS + 0x065C) 865 #define DQSIEN_AUTOK_B1_RK0_DBG_STATUS5_DBG_GATING_STATUS_5_B1_RK0 Fld(32, 0) //[31:0] 866 867 #define DDRPHY_REG_DQSIEN_AUTOK_B1_RK1_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0660) 868 #define DQSIEN_AUTOK_B1_RK1_STATUS0_DQSIEN_AUTOK_C__PI_B1_RK1 Fld(7, 0) //[6:0] 869 #define DQSIEN_AUTOK_B1_RK1_STATUS0_DQSIEN_AUTOK_C__UI_B1_RK1 Fld(4, 8) //[11:8] 870 #define DQSIEN_AUTOK_B1_RK1_STATUS0_DQSIEN_AUTOK_C_MCK_B1_RK1 Fld(4, 12) //[15:12] 871 #define DQSIEN_AUTOK_B1_RK1_STATUS0_AUTOK_DONE_B1_RK1 Fld(1, 16) //[16:16] 872 #define DQSIEN_AUTOK_B1_RK1_STATUS0_AUTOK_ERR_B1_RK1 Fld(1, 17) //[17:17] 873 874 #define DDRPHY_REG_DQSIEN_AUTOK_B1_RK1_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x0664) 875 #define DQSIEN_AUTOK_B1_RK1_STATUS1_DQSIEN_AUTOK_R__PI_B1_RK1 Fld(7, 0) //[6:0] 876 #define DQSIEN_AUTOK_B1_RK1_STATUS1_DQSIEN_AUTOK_R__UI_B1_RK1 Fld(4, 8) //[11:8] 877 #define DQSIEN_AUTOK_B1_RK1_STATUS1_DQSIEN_AUTOK_R_MCK_B1_RK1 Fld(4, 12) //[15:12] 878 #define DQSIEN_AUTOK_B1_RK1_STATUS1_DQSIEN_AUTOK_L__PI_B1_RK1 Fld(7, 16) //[22:16] 879 #define DQSIEN_AUTOK_B1_RK1_STATUS1_DQSIEN_AUTOK_L__UI_B1_RK1 Fld(4, 24) //[27:24] 880 #define DQSIEN_AUTOK_B1_RK1_STATUS1_DQSIEN_AUTOK_L_MCK_B1_RK1 Fld(4, 28) //[31:28] 881 882 #define DDRPHY_REG_DQSIEN_AUTOK_B1_RK1_DBG_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0668) 883 #define DQSIEN_AUTOK_B1_RK1_DBG_STATUS0_DBG_GATING_STATUS_0_B1_RK1 Fld(32, 0) //[31:0] 884 885 #define DDRPHY_REG_DQSIEN_AUTOK_B1_RK1_DBG_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x066C) 886 #define DQSIEN_AUTOK_B1_RK1_DBG_STATUS1_DBG_GATING_STATUS_1_B1_RK1 Fld(32, 0) //[31:0] 887 888 #define DDRPHY_REG_DQSIEN_AUTOK_B1_RK1_DBG_STATUS2 (DDRPHY_NAO_BASE_ADDRESS + 0x0670) 889 #define DQSIEN_AUTOK_B1_RK1_DBG_STATUS2_DBG_GATING_STATUS_2_B1_RK1 Fld(32, 0) //[31:0] 890 891 #define DDRPHY_REG_DQSIEN_AUTOK_B1_RK1_DBG_STATUS3 (DDRPHY_NAO_BASE_ADDRESS + 0x0674) 892 #define DQSIEN_AUTOK_B1_RK1_DBG_STATUS3_DBG_GATING_STATUS_3_B1_RK1 Fld(32, 0) //[31:0] 893 894 #define DDRPHY_REG_DQSIEN_AUTOK_B1_RK1_DBG_STATUS4 (DDRPHY_NAO_BASE_ADDRESS + 0x0678) 895 #define DQSIEN_AUTOK_B1_RK1_DBG_STATUS4_DBG_GATING_STATUS_4_B1_RK1 Fld(32, 0) //[31:0] 896 897 #define DDRPHY_REG_DQSIEN_AUTOK_B1_RK1_DBG_STATUS5 (DDRPHY_NAO_BASE_ADDRESS + 0x067C) 898 #define DQSIEN_AUTOK_B1_RK1_DBG_STATUS5_DBG_GATING_STATUS_5_B1_RK1 Fld(32, 0) //[31:0] 899 900 #define DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0680) 901 #define DQSIEN_AUTOK_CA_RK0_STATUS0_DQSIEN_AUTOK_C__PI_CA_RK0 Fld(7, 0) //[6:0] 902 #define DQSIEN_AUTOK_CA_RK0_STATUS0_DQSIEN_AUTOK_C__UI_CA_RK0 Fld(4, 8) //[11:8] 903 #define DQSIEN_AUTOK_CA_RK0_STATUS0_DQSIEN_AUTOK_C_MCK_CA_RK0 Fld(4, 12) //[15:12] 904 #define DQSIEN_AUTOK_CA_RK0_STATUS0_AUTOK_DONE_CA_RK0 Fld(1, 16) //[16:16] 905 #define DQSIEN_AUTOK_CA_RK0_STATUS0_AUTOK_ERR_CA_RK0 Fld(1, 17) //[17:17] 906 907 #define DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x0684) 908 #define DQSIEN_AUTOK_CA_RK0_STATUS1_DQSIEN_AUTOK_R__PI_CA_RK0 Fld(7, 0) //[6:0] 909 #define DQSIEN_AUTOK_CA_RK0_STATUS1_DQSIEN_AUTOK_R__UI_CA_RK0 Fld(4, 8) //[11:8] 910 #define DQSIEN_AUTOK_CA_RK0_STATUS1_DQSIEN_AUTOK_R_MCK_CA_RK0 Fld(4, 12) //[15:12] 911 #define DQSIEN_AUTOK_CA_RK0_STATUS1_DQSIEN_AUTOK_L__PI_CA_RK0 Fld(7, 16) //[22:16] 912 #define DQSIEN_AUTOK_CA_RK0_STATUS1_DQSIEN_AUTOK_L__UI_CA_RK0 Fld(4, 24) //[27:24] 913 #define DQSIEN_AUTOK_CA_RK0_STATUS1_DQSIEN_AUTOK_L_MCK_CA_RK0 Fld(4, 28) //[31:28] 914 915 #define DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_DBG_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0688) 916 #define DQSIEN_AUTOK_CA_RK0_DBG_STATUS0_DBG_GATING_STATUS_0_CA_RK0 Fld(32, 0) //[31:0] 917 918 #define DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_DBG_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x068C) 919 #define DQSIEN_AUTOK_CA_RK0_DBG_STATUS1_DBG_GATING_STATUS_1_CA_RK0 Fld(32, 0) //[31:0] 920 921 #define DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_DBG_STATUS2 (DDRPHY_NAO_BASE_ADDRESS + 0x0690) 922 #define DQSIEN_AUTOK_CA_RK0_DBG_STATUS2_DBG_GATING_STATUS_2_CA_RK0 Fld(32, 0) //[31:0] 923 924 #define DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_DBG_STATUS3 (DDRPHY_NAO_BASE_ADDRESS + 0x0694) 925 #define DQSIEN_AUTOK_CA_RK0_DBG_STATUS3_DBG_GATING_STATUS_3_CA_RK0 Fld(32, 0) //[31:0] 926 927 #define DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_DBG_STATUS4 (DDRPHY_NAO_BASE_ADDRESS + 0x0698) 928 #define DQSIEN_AUTOK_CA_RK0_DBG_STATUS4_DBG_GATING_STATUS_4_CA_RK0 Fld(32, 0) //[31:0] 929 930 #define DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_DBG_STATUS5 (DDRPHY_NAO_BASE_ADDRESS + 0x069C) 931 #define DQSIEN_AUTOK_CA_RK0_DBG_STATUS5_DBG_GATING_STATUS_5_CA_RK0 Fld(32, 0) //[31:0] 932 933 #define DDRPHY_REG_DQSIEN_AUTOK_CA_RK1_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0700) 934 #define DQSIEN_AUTOK_CA_RK1_STATUS0_DQSIEN_AUTOK_C__PI_CA_RK1 Fld(7, 0) //[6:0] 935 #define DQSIEN_AUTOK_CA_RK1_STATUS0_DQSIEN_AUTOK_C__UI_CA_RK1 Fld(4, 8) //[11:8] 936 #define DQSIEN_AUTOK_CA_RK1_STATUS0_DQSIEN_AUTOK_C_MCK_CA_RK1 Fld(4, 12) //[15:12] 937 #define DQSIEN_AUTOK_CA_RK1_STATUS0_AUTOK_DONE_CA_RK1 Fld(1, 16) //[16:16] 938 #define DQSIEN_AUTOK_CA_RK1_STATUS0_AUTOK_ERR_CA_RK1 Fld(1, 17) //[17:17] 939 940 #define DDRPHY_REG_DQSIEN_AUTOK_CA_RK1_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x0704) 941 #define DQSIEN_AUTOK_CA_RK1_STATUS1_DQSIEN_AUTOK_R__PI_CA_RK1 Fld(7, 0) //[6:0] 942 #define DQSIEN_AUTOK_CA_RK1_STATUS1_DQSIEN_AUTOK_R__UI_CA_RK1 Fld(4, 8) //[11:8] 943 #define DQSIEN_AUTOK_CA_RK1_STATUS1_DQSIEN_AUTOK_R_MCK_CA_RK1 Fld(4, 12) //[15:12] 944 #define DQSIEN_AUTOK_CA_RK1_STATUS1_DQSIEN_AUTOK_L__PI_CA_RK1 Fld(7, 16) //[22:16] 945 #define DQSIEN_AUTOK_CA_RK1_STATUS1_DQSIEN_AUTOK_L__UI_CA_RK1 Fld(4, 24) //[27:24] 946 #define DQSIEN_AUTOK_CA_RK1_STATUS1_DQSIEN_AUTOK_L_MCK_CA_RK1 Fld(4, 28) //[31:28] 947 948 #define DDRPHY_REG_DQSIEN_AUTOK_CA_RK1_DBG_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0708) 949 #define DQSIEN_AUTOK_CA_RK1_DBG_STATUS0_DBG_GATING_STATUS_0_CA_RK1 Fld(32, 0) //[31:0] 950 951 #define DDRPHY_REG_DQSIEN_AUTOK_CA_RK1_DBG_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x070C) 952 #define DQSIEN_AUTOK_CA_RK1_DBG_STATUS1_DBG_GATING_STATUS_1_CA_RK1 Fld(32, 0) //[31:0] 953 954 #define DDRPHY_REG_DQSIEN_AUTOK_CA_RK1_DBG_STATUS2 (DDRPHY_NAO_BASE_ADDRESS + 0x0710) 955 #define DQSIEN_AUTOK_CA_RK1_DBG_STATUS2_DBG_GATING_STATUS_2_CA_RK1 Fld(32, 0) //[31:0] 956 957 #define DDRPHY_REG_DQSIEN_AUTOK_CA_RK1_DBG_STATUS3 (DDRPHY_NAO_BASE_ADDRESS + 0x0714) 958 #define DQSIEN_AUTOK_CA_RK1_DBG_STATUS3_DBG_GATING_STATUS_3_CA_RK1 Fld(32, 0) //[31:0] 959 960 #define DDRPHY_REG_DQSIEN_AUTOK_CA_RK1_DBG_STATUS4 (DDRPHY_NAO_BASE_ADDRESS + 0x0718) 961 #define DQSIEN_AUTOK_CA_RK1_DBG_STATUS4_DBG_GATING_STATUS_4_CA_RK1 Fld(32, 0) //[31:0] 962 963 #define DDRPHY_REG_DQSIEN_AUTOK_CA_RK1_DBG_STATUS5 (DDRPHY_NAO_BASE_ADDRESS + 0x071C) 964 #define DQSIEN_AUTOK_CA_RK1_DBG_STATUS5_DBG_GATING_STATUS_5_CA_RK1 Fld(32, 0) //[31:0] 965 966 #define DDRPHY_REG_DQSIEN_AUTOK_CTRL_STATUS (DDRPHY_NAO_BASE_ADDRESS + 0x0720) 967 #define DQSIEN_AUTOK_CTRL_STATUS_DQSIEN_AUTOK_DONE_RK0 Fld(1, 0) //[0:0] 968 #define DQSIEN_AUTOK_CTRL_STATUS_DQSIEN_AUTOK_DONE_RK1 Fld(1, 1) //[1:1] 969 #define DQSIEN_AUTOK_CTRL_STATUS_DQSIEN_AUTOK_DLE_TIMEOUT_ERROR Fld(1, 2) //[2:2] 970 #define DQSIEN_AUTOK_CTRL_STATUS_DQSIEN_AUTOK_FSM_ST Fld(3, 4) //[6:4] 971 #define DQSIEN_AUTOK_CTRL_STATUS_DQSIEN_AUTOK_FSM_CUR_EDGE Fld(1, 8) //[8:8] 972 973 #define DDRPHY_REG_AD_DLINE_MON (DDRPHY_NAO_BASE_ADDRESS + 0x0724) 974 #define AD_DLINE_MON_AD_RPLLGP_DLINE_MON Fld(24, 0) //[23:0] 975 976 #define DDRPHY_REG_DLINE_MON_TRACK_DBG (DDRPHY_NAO_BASE_ADDRESS + 0x0728) 977 #define DLINE_MON_TRACK_DBG_DLINE_MON_TRACK_DBG Fld(32, 0) //[31:0] 978 979 #define DDRPHY_REG_MISC_DUTYCAL_STATUS (DDRPHY_NAO_BASE_ADDRESS + 0x072C) 980 #define MISC_DUTYCAL_STATUS_RGS_RX_ARDQ_DUTY_VCAL_CMP_OUT_B0 Fld(1, 0) //[0:0] 981 #define MISC_DUTYCAL_STATUS_RGS_RX_ARDQ_DUTY_VCAL_CMP_OUT_B1 Fld(1, 1) //[1:1] 982 #define MISC_DUTYCAL_STATUS_RGS_RX_ARCA_DUTY_VCAL_CMP_OUT_C0 Fld(1, 2) //[2:2] 983 984 #define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE0 (DDRPHY_NAO_BASE_ADDRESS + 0x0730) 985 #define MISC_DBG_DB_IMP_MESSAGE0_DBG_DB_DQS0_DRVP_MAX Fld(5, 0) //[4:0] 986 #define MISC_DBG_DB_IMP_MESSAGE0_DBG_DB_DQS0_DRVP_MAX_ERR Fld(1, 7) //[7:7] 987 #define MISC_DBG_DB_IMP_MESSAGE0_DBG_DB_DQS0_DRVN_MAX Fld(5, 8) //[12:8] 988 #define MISC_DBG_DB_IMP_MESSAGE0_DBG_DB_DQS0_DRVN_MAX_ERR Fld(1, 15) //[15:15] 989 #define MISC_DBG_DB_IMP_MESSAGE0_DBG_DB_DQS0_ODTN_MAX Fld(5, 16) //[20:16] 990 #define MISC_DBG_DB_IMP_MESSAGE0_DBG_DB_DQS0_ODTN_MAX_ERR Fld(1, 23) //[23:23] 991 #define MISC_DBG_DB_IMP_MESSAGE0_DBG_DB_WCK0_DRVP_MAX Fld(5, 24) //[28:24] 992 #define MISC_DBG_DB_IMP_MESSAGE0_DBG_DB_WCK0_DRVP_MAX_ERR Fld(1, 31) //[31:31] 993 994 #define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE1 (DDRPHY_NAO_BASE_ADDRESS + 0x0734) 995 #define MISC_DBG_DB_IMP_MESSAGE1_DBG_DB_DQS1_DRVP_MAX Fld(5, 0) //[4:0] 996 #define MISC_DBG_DB_IMP_MESSAGE1_DBG_DB_DQS1_DRVP_MAX_ERR Fld(1, 7) //[7:7] 997 #define MISC_DBG_DB_IMP_MESSAGE1_DBG_DB_DQS1_DRVN_MAX Fld(5, 8) //[12:8] 998 #define MISC_DBG_DB_IMP_MESSAGE1_DBG_DB_DQS1_DRVN_MAX_ERR Fld(1, 15) //[15:15] 999 #define MISC_DBG_DB_IMP_MESSAGE1_DBG_DB_DQS1_ODTN_MAX Fld(5, 16) //[20:16] 1000 #define MISC_DBG_DB_IMP_MESSAGE1_DBG_DB_DQS1_ODTN_MAX_ERR Fld(1, 23) //[23:23] 1001 #define MISC_DBG_DB_IMP_MESSAGE1_DBG_DB_WCK0_DRVN_MAX Fld(5, 24) //[28:24] 1002 #define MISC_DBG_DB_IMP_MESSAGE1_DBG_DB_WCK0_DRVN_MAX_ERR Fld(1, 31) //[31:31] 1003 1004 #define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE2 (DDRPHY_NAO_BASE_ADDRESS + 0x0738) 1005 #define MISC_DBG_DB_IMP_MESSAGE2_DBG_DB_DQ0_DRVP_MAX Fld(5, 0) //[4:0] 1006 #define MISC_DBG_DB_IMP_MESSAGE2_DBG_DB_DQ0_DRVP_MAX_ERR Fld(1, 7) //[7:7] 1007 #define MISC_DBG_DB_IMP_MESSAGE2_DBG_DB_DQ0_DRVN_MAX Fld(5, 8) //[12:8] 1008 #define MISC_DBG_DB_IMP_MESSAGE2_DBG_DB_DQ0_DRVN_MAX_ERR Fld(1, 15) //[15:15] 1009 #define MISC_DBG_DB_IMP_MESSAGE2_DBG_DB_DQ0_ODTN_MAX Fld(5, 16) //[20:16] 1010 #define MISC_DBG_DB_IMP_MESSAGE2_DBG_DB_DQ0_ODTN_MAX_ERR Fld(1, 23) //[23:23] 1011 #define MISC_DBG_DB_IMP_MESSAGE2_DBG_DB_WCK1_DRVP_MAX Fld(5, 24) //[28:24] 1012 #define MISC_DBG_DB_IMP_MESSAGE2_DBG_DB_WCK1_DRVP_MAX_ERR Fld(1, 31) //[31:31] 1013 1014 #define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE3 (DDRPHY_NAO_BASE_ADDRESS + 0x073C) 1015 #define MISC_DBG_DB_IMP_MESSAGE3_DBG_DB_DQ1_DRVP_MAX Fld(5, 0) //[4:0] 1016 #define MISC_DBG_DB_IMP_MESSAGE3_DBG_DB_DQ1_DRVP_MAX_ERR Fld(1, 7) //[7:7] 1017 #define MISC_DBG_DB_IMP_MESSAGE3_DBG_DB_DQ1_DRVN_MAX Fld(5, 8) //[12:8] 1018 #define MISC_DBG_DB_IMP_MESSAGE3_DBG_DB_DQ1_DRVN_MAX_ERR Fld(1, 15) //[15:15] 1019 #define MISC_DBG_DB_IMP_MESSAGE3_DBG_DB_DQ1_ODTN_MAX Fld(5, 16) //[20:16] 1020 #define MISC_DBG_DB_IMP_MESSAGE3_DBG_DB_DQ1_ODTN_MAX_ERR Fld(1, 23) //[23:23] 1021 #define MISC_DBG_DB_IMP_MESSAGE3_DBG_DB_WCK1_DRVN_MAX Fld(5, 24) //[28:24] 1022 #define MISC_DBG_DB_IMP_MESSAGE3_DBG_DB_WCK1_DRVN_MAX_ERR Fld(1, 31) //[31:31] 1023 1024 #define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE4 (DDRPHY_NAO_BASE_ADDRESS + 0x0740) 1025 #define MISC_DBG_DB_IMP_MESSAGE4_DBG_DB_CMD_DRVP_MAX Fld(5, 0) //[4:0] 1026 #define MISC_DBG_DB_IMP_MESSAGE4_DBG_DB_CMD_DRVP_MAX_ERR Fld(1, 7) //[7:7] 1027 #define MISC_DBG_DB_IMP_MESSAGE4_DBG_DB_CMD_DRVN_MAX Fld(5, 8) //[12:8] 1028 #define MISC_DBG_DB_IMP_MESSAGE4_DBG_DB_CMD_DRVN_MAX_ERR Fld(1, 15) //[15:15] 1029 #define MISC_DBG_DB_IMP_MESSAGE4_DBG_DB_CMD_ODTN_MAX Fld(5, 16) //[20:16] 1030 #define MISC_DBG_DB_IMP_MESSAGE4_DBG_DB_CMD_ODTN_MAX_ERR Fld(1, 23) //[23:23] 1031 #define MISC_DBG_DB_IMP_MESSAGE4_DBG_DB_CS_DRVP_MAX Fld(5, 24) //[28:24] 1032 #define MISC_DBG_DB_IMP_MESSAGE4_DBG_DB_CS_DRVP_MAX_ERR Fld(1, 31) //[31:31] 1033 1034 #define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE5 (DDRPHY_NAO_BASE_ADDRESS + 0x0744) 1035 #define MISC_DBG_DB_IMP_MESSAGE5_DBG_DB_CLK_DRVP_MAX Fld(5, 0) //[4:0] 1036 #define MISC_DBG_DB_IMP_MESSAGE5_DBG_DB_CLK_DRVP_MAX_ERR Fld(1, 7) //[7:7] 1037 #define MISC_DBG_DB_IMP_MESSAGE5_DBG_DB_CLK_DRVN_MAX Fld(5, 8) //[12:8] 1038 #define MISC_DBG_DB_IMP_MESSAGE5_DBG_DB_CLK_DRVN_MAX_ERR Fld(1, 15) //[15:15] 1039 #define MISC_DBG_DB_IMP_MESSAGE5_DBG_DB_CLK_ODTN_MAX Fld(5, 16) //[20:16] 1040 #define MISC_DBG_DB_IMP_MESSAGE5_DBG_DB_CLK_ODTN_MAX_ERR Fld(1, 23) //[23:23] 1041 #define MISC_DBG_DB_IMP_MESSAGE5_DBG_DB_CS_DRVN_MAX Fld(5, 24) //[28:24] 1042 #define MISC_DBG_DB_IMP_MESSAGE5_DBG_DB_CS_DRVN_MAX_ERR Fld(1, 31) //[31:31] 1043 1044 #define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE6 (DDRPHY_NAO_BASE_ADDRESS + 0x0748) 1045 #define MISC_DBG_DB_IMP_MESSAGE6_DBG_DB_DQS0_DRVP_MIN Fld(5, 0) //[4:0] 1046 #define MISC_DBG_DB_IMP_MESSAGE6_DBG_DB_DQS0_DRVP_MIN_ERR Fld(1, 7) //[7:7] 1047 #define MISC_DBG_DB_IMP_MESSAGE6_DBG_DB_DQS0_DRVN_MIN Fld(5, 8) //[12:8] 1048 #define MISC_DBG_DB_IMP_MESSAGE6_DBG_DB_DQS0_DRVN_MIN_ERR Fld(1, 15) //[15:15] 1049 #define MISC_DBG_DB_IMP_MESSAGE6_DBG_DB_DQS0_ODTN_MIN Fld(5, 16) //[20:16] 1050 #define MISC_DBG_DB_IMP_MESSAGE6_DBG_DB_DQS0_ODTN_MIN_ERR Fld(1, 23) //[23:23] 1051 #define MISC_DBG_DB_IMP_MESSAGE6_DBG_DB_WCK0_DRVP_MIN Fld(5, 24) //[28:24] 1052 #define MISC_DBG_DB_IMP_MESSAGE6_DBG_DB_WCK0_DRVP_MIN_ERR Fld(1, 31) //[31:31] 1053 1054 #define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE7 (DDRPHY_NAO_BASE_ADDRESS + 0x074C) 1055 #define MISC_DBG_DB_IMP_MESSAGE7_DBG_DB_DQS1_DRVP_MIN Fld(5, 0) //[4:0] 1056 #define MISC_DBG_DB_IMP_MESSAGE7_DBG_DB_DQS1_DRVP_MIN_ERR Fld(1, 7) //[7:7] 1057 #define MISC_DBG_DB_IMP_MESSAGE7_DBG_DB_DQS1_DRVN_MIN Fld(5, 8) //[12:8] 1058 #define MISC_DBG_DB_IMP_MESSAGE7_DBG_DB_DQS1_DRVN_MIN_ERR Fld(1, 15) //[15:15] 1059 #define MISC_DBG_DB_IMP_MESSAGE7_DBG_DB_DQS1_ODTN_MIN Fld(5, 16) //[20:16] 1060 #define MISC_DBG_DB_IMP_MESSAGE7_DBG_DB_DQS1_ODTN_MIN_ERR Fld(1, 23) //[23:23] 1061 #define MISC_DBG_DB_IMP_MESSAGE7_DBG_DB_WCK0_DRVN_MIN Fld(5, 24) //[28:24] 1062 #define MISC_DBG_DB_IMP_MESSAGE7_DBG_DB_WCK0_DRVN_MIN_ERR Fld(1, 31) //[31:31] 1063 1064 #define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE8 (DDRPHY_NAO_BASE_ADDRESS + 0x0750) 1065 #define MISC_DBG_DB_IMP_MESSAGE8_DBG_DB_DQ0_DRVP_MIN Fld(5, 0) //[4:0] 1066 #define MISC_DBG_DB_IMP_MESSAGE8_DBG_DB_DQ0_DRVP_MIN_ERR Fld(1, 7) //[7:7] 1067 #define MISC_DBG_DB_IMP_MESSAGE8_DBG_DB_DQ0_DRVN_MIN Fld(5, 8) //[12:8] 1068 #define MISC_DBG_DB_IMP_MESSAGE8_DBG_DB_DQ0_DRVN_MIN_ERR Fld(1, 15) //[15:15] 1069 #define MISC_DBG_DB_IMP_MESSAGE8_DBG_DB_DQ0_ODTN_MIN Fld(5, 16) //[20:16] 1070 #define MISC_DBG_DB_IMP_MESSAGE8_DBG_DB_DQ0_ODTN_MIN_ERR Fld(1, 23) //[23:23] 1071 #define MISC_DBG_DB_IMP_MESSAGE8_DBG_DB_WCK1_DRVP_MIN Fld(5, 24) //[28:24] 1072 #define MISC_DBG_DB_IMP_MESSAGE8_DBG_DB_WCK1_DRVP_MIN_ERR Fld(1, 31) //[31:31] 1073 1074 #define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE9 (DDRPHY_NAO_BASE_ADDRESS + 0x0754) 1075 #define MISC_DBG_DB_IMP_MESSAGE9_DBG_DB_DQ1_DRVP_MIN Fld(5, 0) //[4:0] 1076 #define MISC_DBG_DB_IMP_MESSAGE9_DBG_DB_DQ1_DRVP_MIN_ERR Fld(1, 7) //[7:7] 1077 #define MISC_DBG_DB_IMP_MESSAGE9_DBG_DB_DQ1_DRVN_MIN Fld(5, 8) //[12:8] 1078 #define MISC_DBG_DB_IMP_MESSAGE9_DBG_DB_DQ1_DRVN_MIN_ERR Fld(1, 15) //[15:15] 1079 #define MISC_DBG_DB_IMP_MESSAGE9_DBG_DB_DQ1_ODTN_MIN Fld(5, 16) //[20:16] 1080 #define MISC_DBG_DB_IMP_MESSAGE9_DBG_DB_DQ1_ODTN_MIN_ERR Fld(1, 23) //[23:23] 1081 #define MISC_DBG_DB_IMP_MESSAGE9_DBG_DB_WCK1_DRVN_MIN Fld(5, 24) //[28:24] 1082 #define MISC_DBG_DB_IMP_MESSAGE9_DBG_DB_WCK1_DRVN_MIN_ERR Fld(1, 31) //[31:31] 1083 1084 #define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE10 (DDRPHY_NAO_BASE_ADDRESS + 0x0758) 1085 #define MISC_DBG_DB_IMP_MESSAGE10_DBG_DB_CMD_DRVP_MIN Fld(5, 0) //[4:0] 1086 #define MISC_DBG_DB_IMP_MESSAGE10_DBG_DB_CMD_DRVP_MIN_ERR Fld(1, 7) //[7:7] 1087 #define MISC_DBG_DB_IMP_MESSAGE10_DBG_DB_CMD_DRVN_MIN Fld(5, 8) //[12:8] 1088 #define MISC_DBG_DB_IMP_MESSAGE10_DBG_DB_CMD_DRVN_MIN_ERR Fld(1, 15) //[15:15] 1089 #define MISC_DBG_DB_IMP_MESSAGE10_DBG_DB_CMD_ODTN_MIN Fld(5, 16) //[20:16] 1090 #define MISC_DBG_DB_IMP_MESSAGE10_DBG_DB_CMD_ODTN_MIN_ERR Fld(1, 23) //[23:23] 1091 #define MISC_DBG_DB_IMP_MESSAGE10_DBG_DB_CS_DRVP_MIN Fld(5, 24) //[28:24] 1092 #define MISC_DBG_DB_IMP_MESSAGE10_DBG_DB_CS_DRVP_MIN_ERR Fld(1, 31) //[31:31] 1093 1094 #define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE11 (DDRPHY_NAO_BASE_ADDRESS + 0x075C) 1095 #define MISC_DBG_DB_IMP_MESSAGE11_DBG_DB_CLK_DRVP_MIN Fld(5, 0) //[4:0] 1096 #define MISC_DBG_DB_IMP_MESSAGE11_DBG_DB_CLK_DRVP_MIN_ERR Fld(1, 7) //[7:7] 1097 #define MISC_DBG_DB_IMP_MESSAGE11_DBG_DB_CLK_DRVN_MIN Fld(5, 8) //[12:8] 1098 #define MISC_DBG_DB_IMP_MESSAGE11_DBG_DB_CLK_DRVN_MIN_ERR Fld(1, 15) //[15:15] 1099 #define MISC_DBG_DB_IMP_MESSAGE11_DBG_DB_CLK_ODTN_MIN Fld(5, 16) //[20:16] 1100 #define MISC_DBG_DB_IMP_MESSAGE11_DBG_DB_CLK_ODTN_MIN_ERR Fld(1, 23) //[23:23] 1101 #define MISC_DBG_DB_IMP_MESSAGE11_DBG_DB_CS_DRVN_MIN Fld(5, 24) //[28:24] 1102 #define MISC_DBG_DB_IMP_MESSAGE11_DBG_DB_CS_DRVN_MIN_ERR Fld(1, 31) //[31:31] 1103 1104 #define DDRPHY_REG_MISC_DMA_SRAM_MBIST (DDRPHY_NAO_BASE_ADDRESS + 0x0800) 1105 #define MISC_DMA_SRAM_MBIST_DRAMC_MBIST_MBIST_PRE_FUSE Fld(8, 0) //[7:0] 1106 1107 #define DDRPHY_REG_MISC_APHY_OBS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0820) 1108 #define MISC_APHY_OBS0_AD_RX_ARDQ1_RCNT_B0 Fld(9, 0) //[8:0] 1109 #define MISC_APHY_OBS0_AD_RX_ARDQ2_RCNT_B0 Fld(9, 9) //[17:9] 1110 #define MISC_APHY_OBS0_AD_RX_ARDQ3_RCNT_B0 Fld(9, 18) //[26:18] 1111 1112 #define DDRPHY_REG_MISC_APHY_OBS1 (DDRPHY_NAO_BASE_ADDRESS + 0x0824) 1113 #define MISC_APHY_OBS1_AD_RX_ARDQ5_RCNT_B0 Fld(9, 0) //[8:0] 1114 #define MISC_APHY_OBS1_AD_RX_ARDQ6_RCNT_B0 Fld(9, 9) //[17:9] 1115 #define MISC_APHY_OBS1_AD_RX_ARDQ7_RCNT_B0 Fld(9, 18) //[26:18] 1116 1117 #define DDRPHY_REG_MISC_APHY_OBS2 (DDRPHY_NAO_BASE_ADDRESS + 0x0828) 1118 #define MISC_APHY_OBS2_AD_RX_ARDQ1_RCNT_B1 Fld(9, 0) //[8:0] 1119 #define MISC_APHY_OBS2_AD_RX_ARDQ2_RCNT_B1 Fld(9, 9) //[17:9] 1120 #define MISC_APHY_OBS2_AD_RX_ARDQ3_RCNT_B1 Fld(9, 18) //[26:18] 1121 1122 #define DDRPHY_REG_MISC_APHY_OBS3 (DDRPHY_NAO_BASE_ADDRESS + 0x082C) 1123 #define MISC_APHY_OBS3_AD_RX_ARDQ5_RCNT_B1 Fld(9, 0) //[8:0] 1124 #define MISC_APHY_OBS3_AD_RX_ARDQ6_RCNT_B1 Fld(9, 9) //[17:9] 1125 #define MISC_APHY_OBS3_AD_RX_ARDQ7_RCNT_B1 Fld(9, 18) //[26:18] 1126 1127 #define DDRPHY_REG_MISC_APHY_OBS4 (DDRPHY_NAO_BASE_ADDRESS + 0x0830) 1128 #define MISC_APHY_OBS4_AD_RX_ARDQM_RCNT_B0 Fld(9, 0) //[8:0] 1129 #define MISC_APHY_OBS4_AD_RX_ARDQM_RCNT_B1 Fld(9, 9) //[17:9] 1130 1131 #define DDRPHY_REG_MISC_APHY_OBS5 (DDRPHY_NAO_BASE_ADDRESS + 0x0834) 1132 #define MISC_APHY_OBS5_AD_RX_ARCA1_RCNT_C0 Fld(9, 0) //[8:0] 1133 #define MISC_APHY_OBS5_AD_RX_ARCA2_RCNT_C0 Fld(9, 9) //[17:9] 1134 #define MISC_APHY_OBS5_AD_RX_ARCA3_RCNT_C0 Fld(9, 18) //[26:18] 1135 1136 #define DDRPHY_REG_MISC_APHY_OBS6 (DDRPHY_NAO_BASE_ADDRESS + 0x0838) 1137 #define MISC_APHY_OBS6_AD_RX_ARCA5_RCNT_C0 Fld(9, 0) //[8:0] 1138 #define MISC_APHY_OBS6_AD_RX_ARCS0_RCNT_C0 Fld(9, 9) //[17:9] 1139 #define MISC_APHY_OBS6_AD_RX_ARCS1_RCNT_C0 Fld(9, 18) //[26:18] 1140 1141 #define DDRPHY_REG_MISC_APHY_OBS7 (DDRPHY_NAO_BASE_ADDRESS + 0x083C) 1142 #define MISC_APHY_OBS7_AD_RX_ARCKE0_RCNT_C0 Fld(9, 0) //[8:0] 1143 #define MISC_APHY_OBS7_AD_RX_ARCKE1_RCNT_C0 Fld(9, 9) //[17:9] 1144 1145 #define DDRPHY_REG_MISC_APHY_OBS8 (DDRPHY_NAO_BASE_ADDRESS + 0x0840) 1146 #define MISC_APHY_OBS8_RGS_ARDLL_ULCK_B0 Fld(2, 0) //[1:0] 1147 #define MISC_APHY_OBS8_RGS_ARDLL_ULCK_B1 Fld(2, 2) //[3:2] 1148 #define MISC_APHY_OBS8_RGS_ARDLL_ULCK_C0 Fld(2, 4) //[5:4] 1149 #define MISC_APHY_OBS8_RGS_RPHYPLL_DET_RSTB Fld(1, 6) //[6:6] 1150 #define MISC_APHY_OBS8_RGS_RCLRPLL_DET_RSTB Fld(1, 7) //[7:7] 1151 1152 #define DDRPHY_REG_MISC_EMI_LPBK8 (DDRPHY_NAO_BASE_ADDRESS + 0x0844) 1153 #define MISC_EMI_LPBK8_RDATA_CA0 Fld(8, 0) //[7:0] 1154 #define MISC_EMI_LPBK8_RDATA_CA1 Fld(8, 8) //[15:8] 1155 #define MISC_EMI_LPBK8_RDATA_CA2 Fld(8, 16) //[23:16] 1156 #define MISC_EMI_LPBK8_RDATA_CA3 Fld(8, 24) //[31:24] 1157 1158 #define DDRPHY_REG_MISC_EMI_LPBK9 (DDRPHY_NAO_BASE_ADDRESS + 0x0848) 1159 #define MISC_EMI_LPBK9_RDATA_CA4 Fld(8, 0) //[7:0] 1160 #define MISC_EMI_LPBK9_RDATA_CA5 Fld(8, 8) //[15:8] 1161 #define MISC_EMI_LPBK9_RDATA_CA6 Fld(8, 16) //[23:16] 1162 #define MISC_EMI_LPBK9_RDATA_CA7 Fld(8, 24) //[31:24] 1163 1164 #define DDRPHY_REG_MISC_EMI_LPBK10 (DDRPHY_NAO_BASE_ADDRESS + 0x084C) 1165 #define MISC_EMI_LPBK10_RDATA_CKE0 Fld(8, 0) //[7:0] 1166 #define MISC_EMI_LPBK10_RDATA_CKE1 Fld(8, 8) //[15:8] 1167 #define MISC_EMI_LPBK10_RDATA_CKE2 Fld(8, 16) //[23:16] 1168 1169 #define DDRPHY_REG_MISC_EMI_LPBK11 (DDRPHY_NAO_BASE_ADDRESS + 0x0850) 1170 #define MISC_EMI_LPBK11_RDATA_CS0 Fld(8, 0) //[7:0] 1171 #define MISC_EMI_LPBK11_RDATA_CS1 Fld(8, 8) //[15:8] 1172 #define MISC_EMI_LPBK11_RDATA_CS2 Fld(8, 16) //[23:16] 1173 1174 #define DDRPHY_REG_MISC_FT_STATUS5 (DDRPHY_NAO_BASE_ADDRESS + 0x0854) 1175 #define MISC_FT_STATUS5_AD_RX_ARDQ6_DVS_R_LEAD_C0 Fld(1, 0) //[0:0] 1176 #define MISC_FT_STATUS5_AD_RX_ARDQ6_DVS_R_LAG_C0 Fld(1, 1) //[1:1] 1177 #define MISC_FT_STATUS5_AD_RX_ARDQ6_DVS_F_LEAD_C0 Fld(1, 2) //[2:2] 1178 #define MISC_FT_STATUS5_AD_RX_ARDQ6_DVS_F_LAG_C0 Fld(1, 3) //[3:3] 1179 #define MISC_FT_STATUS5_AD_RX_ARDQ7_DVS_R_LEAD_C0 Fld(1, 4) //[4:4] 1180 #define MISC_FT_STATUS5_AD_RX_ARDQ7_DVS_R_LAG_C0 Fld(1, 5) //[5:5] 1181 #define MISC_FT_STATUS5_AD_RX_ARDQ7_DVS_F_LEAD_C0 Fld(1, 6) //[6:6] 1182 #define MISC_FT_STATUS5_AD_RX_ARDQ7_DVS_F_LAG_C0 Fld(1, 7) //[7:7] 1183 #define MISC_FT_STATUS5_AD_RX_ARCS1_DVS_R_LEAD_B1 Fld(1, 8) //[8:8] 1184 #define MISC_FT_STATUS5_AD_RX_ARCS1_DVS_R_LAG_B1 Fld(1, 9) //[9:9] 1185 #define MISC_FT_STATUS5_AD_RX_ARCS1_DVS_F_LEAD_B1 Fld(1, 10) //[10:10] 1186 #define MISC_FT_STATUS5_AD_RX_ARCS1_DVS_F_LAG_B1 Fld(1, 11) //[11:11] 1187 #define MISC_FT_STATUS5_AD_RX_ARCKE0_DVS_R_LEAD_B1 Fld(1, 12) //[12:12] 1188 #define MISC_FT_STATUS5_AD_RX_ARCKE0_DVS_R_LAG_B1 Fld(1, 13) //[13:13] 1189 #define MISC_FT_STATUS5_AD_RX_ARCKE0_DVS_F_LEAD_B1 Fld(1, 14) //[14:14] 1190 #define MISC_FT_STATUS5_AD_RX_ARCKE0_DVS_F_LAG_B1 Fld(1, 15) //[15:15] 1191 #define MISC_FT_STATUS5_AD_RX_ARCKE1_DVS_R_LEAD_B1 Fld(1, 16) //[16:16] 1192 #define MISC_FT_STATUS5_AD_RX_ARCKE1_DVS_R_LAG_B1 Fld(1, 17) //[17:17] 1193 #define MISC_FT_STATUS5_AD_RX_ARCKE1_DVS_F_LEAD_B1 Fld(1, 18) //[18:18] 1194 #define MISC_FT_STATUS5_AD_RX_ARCKE1_DVS_F_LAG_B1 Fld(1, 19) //[19:19] 1195 1196 #define DDRPHY_REG_MISC_STA_EXTLB6 (DDRPHY_NAO_BASE_ADDRESS + 0x0858) 1197 #define MISC_STA_EXTLB6_STA_EXTLB_DONE_EXTEND Fld(32, 0) //[31:0] 1198 1199 #define DDRPHY_REG_MISC_STA_EXTLB7 (DDRPHY_NAO_BASE_ADDRESS + 0x085C) 1200 #define MISC_STA_EXTLB7_STA_EXTLB_FAIL_EXTEND Fld(32, 0) //[31:0] 1201 1202 #define DDRPHY_REG_MISC_STA_EXTLB8 (DDRPHY_NAO_BASE_ADDRESS + 0x0860) 1203 #define MISC_STA_EXTLB8_STA_EXTLB_RISING_FAIL_EXTEND Fld(32, 0) //[31:0] 1204 1205 #define DDRPHY_REG_MISC_STA_EXTLB9 (DDRPHY_NAO_BASE_ADDRESS + 0x0864) 1206 #define MISC_STA_EXTLB9_STA_EXTLB_FALLING_FAIL_EXTEND Fld(32, 0) //[31:0] 1207 1208 #endif // __DDRPHY_NAO_REGS_H__ 1209