1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_MEDIATEK_DRAMC_SOC_COMMON_H__ 4 #define __SOC_MEDIATEK_DRAMC_SOC_COMMON_H__ 5 6 /* 7 * Internal CBT mode enum 8 * 1. Calibration flow uses vGet_Dram_CBT_Mode to 9 * differentiate between mixed vs non-mixed LP4 10 * 2. Declared as dram_cbt_mode[RANK_MAX] internally to 11 * store each rank's CBT mode type 12 */ 13 typedef enum { 14 CBT_NORMAL_MODE = 0, 15 CBT_BYTE_MODE1, 16 } DRAM_CBT_MODE_T; 17 18 #define DQS_NUMBER_LP4 2 19 #define DQS_BIT_NUMBER 8 20 #define DQ_DATA_WIDTH_LP4 16 21 22 #endif /* __SOC_MEDIATEK_DRAMC_SOC_COMMON_H__ */ 23