1 /* SPDX-License-Identifier: BSD-3-Clause */
2
3 //-----------------------------------------------------------------------------
4 // Include files
5 //-----------------------------------------------------------------------------
6 //#include "..\Common\pd_common.h"
7 //#include "Register.h"
8 #include "dramc_common.h"
9 #include "dramc_dv_init.h"
10 #include "dramc_int_global.h"
11 #include "x_hal_io.h"
12 #include "dramc_actiming.h"
13 #if (FOR_DV_SIMULATION_USED==0)
14 #include "dramc_top.h"
15 #include "pll.h"
16 //extern EMI_SETTINGS g_default_emi_setting;
17 #endif
18
19 //#include "DramC_reg.h"
20 //#include "System_reg.h"
21 //#include "string.h"
22
23 //-----------------------------------------------------------------------------
24 // Global variables
25 //-----------------------------------------------------------------------------
26 U8 u1PrintModeRegWrite = 0;
27
28 #if ENABLE_RODT_TRACKING_SAVE_MCK
29
30 U8 u1ODT_ON;
31 U8 u1WDQS_ON = 0;
32 U8 u1RODT_TRACK = 0;
33 U8 u1ROEN, u1ModeSel;
34 #endif
35
36
37 const U8 uiLPDDR4_MRR_DRAM_Pinmux[PINMUX_MAX][CHANNEL_NUM][16] =
38 {
39 {
40
41 {
42 0, 1, 2, 3, 5, 7, 6, 4,
43 9, 8, 13, 15, 10, 14, 11, 12
44 },
45 #if (CHANNEL_NUM>1)
46
47 {
48 0, 1, 5, 4, 3, 7, 6, 2,
49 9, 8, 13, 14, 10, 15, 11, 12
50 },
51 #endif
52 #if (CHANNEL_NUM>2)
53
54 {
55 0, 1, 2, 3, 5, 7, 6, 4,
56 9, 8, 13, 15, 10, 14, 11, 12
57 },
58
59 {
60 0, 1, 5, 4, 3, 7, 6, 2,
61 9, 8, 13, 14, 10, 15, 11, 12
62 },
63 #endif
64 },
65 {
66
67 {
68 0, 1, 4, 3, 2, 5, 7, 6,
69 9, 8, 10, 11, 14, 13, 15, 12
70 },
71 #if (CHANNEL_NUM>1)
72
73 {
74 0, 1, 2, 4, 5, 3, 7, 6,
75 8, 9, 10, 11, 15, 14, 13, 12
76 },
77 #endif
78 #if (CHANNEL_NUM>2)
79
80 {
81 0, 1, 2, 3, 4, 5, 6, 7,
82 8, 9, 10, 11, 12, 13, 14, 15
83 },
84
85 {
86 0, 1, 2, 3, 4, 5, 6, 7,
87 8, 9, 10, 11, 12, 13, 14, 15
88 },
89 #endif
90 },
91 {
92
93 {
94 0, 1, 3, 6, 4, 7, 2, 5,
95 8, 9, 10, 13, 11, 12, 15, 14
96 },
97 #if (CHANNEL_NUM>1)
98
99 {
100 0, 1, 4, 7, 3, 5, 6, 2,
101 9, 8, 10, 12, 11, 14, 13, 15
102 },
103 #endif
104 #if (CHANNEL_NUM>2)
105
106 {
107 1, 0, 3, 2, 4, 7, 6, 5,
108 8, 9, 10, 14, 11, 15, 13, 12
109 },
110
111 {
112 0, 1, 4, 7, 3, 5, 6, 2,
113 9, 8, 10, 12, 11, 14, 13, 15
114 },
115 #endif
116 },
117 {
118
119 {
120 9, 8, 11, 10, 14, 15, 13, 12,
121 0, 1, 7, 6, 4, 5, 2, 3
122 },
123 #if (CHANNEL_NUM>1)
124
125 {
126 8, 9, 11, 10, 12, 14, 13, 15,
127 1, 0, 5, 6, 3, 2, 7, 4
128 },
129 #endif
130 #if (CHANNEL_NUM>2)
131
132 {
133 0, 1, 7, 6, 4, 5, 2, 3,
134 9, 8, 11, 10, 14, 15, 13, 12
135 },
136
137 {
138 1, 0, 5, 6, 3, 2, 7, 4,
139 8, 9, 11, 10, 12, 14, 13, 15
140 },
141 #endif
142 },
143 };
144
145
146
147 U8 uiLPDDR4_MRR_Mapping_POP[CHANNEL_NUM][16] =
148 {
149
150 {
151 0, 1, 2, 3, 7, 4, 6, 5,
152 9, 8, 12, 14, 15, 10, 13, 11
153 },
154 #if (CHANNEL_NUM>1)
155
156 {
157 0, 1, 7, 4, 3, 2, 6, 5,
158 9, 8, 12, 14, 15, 10, 11, 13
159 },
160 #endif
161 #if (CHANNEL_NUM>2)
162
163 {
164 0, 1, 2, 3, 7, 4, 6, 5,
165 9, 8, 12, 14, 15, 10, 13, 11
166 },
167
168 {
169 0, 1, 7, 4, 3, 2, 6, 5,
170 9, 8, 12, 14, 15, 10, 11, 13
171 },
172 #endif
173 };
174
175 #if (fcFOR_CHIP_ID == fc8195)
Set_DRAM_Pinmux_Sel(DRAMC_CTX_T * p)176 static void Set_DRAM_Pinmux_Sel(DRAMC_CTX_T *p)
177 {
178
179 #if !FOR_DV_SIMULATION_USED
180 if (is_discrete_lpddr4())
181 p->DRAMPinmux = PINMUX_DSC;
182 else
183 #endif
184 p->DRAMPinmux = PINMUX_EMCP;
185
186 mcSHOW_DBG_MSG2(("[Set_DRAM_Pinmux_Sel] DRAMPinmux = %d\n", p->DRAMPinmux));
187
188 vIO32WriteFldAlign(DRAMC_REG_SA_RESERVE, p->DRAMPinmux, SA_RESERVE_DRM_DSC_DRAM);
189 memcpy(&uiLPDDR4_MRR_Mapping_POP, uiLPDDR4_MRR_DRAM_Pinmux[p->DRAMPinmux], sizeof(uiLPDDR4_MRR_Mapping_POP));
190 memcpy(&uiLPDDR4_O1_Mapping_POP, uiLPDDR4_O1_DRAM_Pinmux[p->DRAMPinmux], sizeof(uiLPDDR4_O1_Mapping_POP));
191 memcpy(&uiLPDDR4_CA_Mapping_POP, uiLPDDR4_CA_DRAM_Pinmux[p->DRAMPinmux], sizeof(uiLPDDR4_CA_Mapping_POP));
192 }
193 #endif
194
Set_MRR_Pinmux_Mapping(DRAMC_CTX_T * p)195 static void Set_MRR_Pinmux_Mapping(DRAMC_CTX_T *p)
196 {
197 U8 *uiLPDDR_MRR_Mapping = NULL;
198 U8 backup_channel;
199 U32 backup_broadcast;
200 DRAM_CHANNEL_T chIdx = CHANNEL_A;
201
202
203 backup_channel = vGetPHY2ChannelMapping(p);
204 backup_broadcast = GetDramcBroadcast();
205
206 DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
207
208
209 for (chIdx = CHANNEL_A; chIdx < (int)p->support_channel_num; chIdx++)
210 {
211 vSetPHY2ChannelMapping(p, chIdx);
212
213 uiLPDDR_MRR_Mapping = (U8 *)uiLPDDR4_MRR_Mapping_POP[chIdx];
214
215
216 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX1), P_Fld(uiLPDDR_MRR_Mapping[0], MRR_BIT_MUX1_MRR_BIT0_SEL) | P_Fld(uiLPDDR_MRR_Mapping[1], MRR_BIT_MUX1_MRR_BIT1_SEL) |
217 P_Fld(uiLPDDR_MRR_Mapping[2], MRR_BIT_MUX1_MRR_BIT2_SEL) | P_Fld(uiLPDDR_MRR_Mapping[3], MRR_BIT_MUX1_MRR_BIT3_SEL));
218 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX2), P_Fld(uiLPDDR_MRR_Mapping[4], MRR_BIT_MUX2_MRR_BIT4_SEL) | P_Fld(uiLPDDR_MRR_Mapping[5], MRR_BIT_MUX2_MRR_BIT5_SEL) |
219 P_Fld(uiLPDDR_MRR_Mapping[6], MRR_BIT_MUX2_MRR_BIT6_SEL) | P_Fld(uiLPDDR_MRR_Mapping[7], MRR_BIT_MUX2_MRR_BIT7_SEL));
220 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX3), P_Fld(uiLPDDR_MRR_Mapping[8], MRR_BIT_MUX3_MRR_BIT8_SEL) | P_Fld(uiLPDDR_MRR_Mapping[9], MRR_BIT_MUX3_MRR_BIT9_SEL) |
221 P_Fld(uiLPDDR_MRR_Mapping[10], MRR_BIT_MUX3_MRR_BIT10_SEL) | P_Fld(uiLPDDR_MRR_Mapping[11], MRR_BIT_MUX3_MRR_BIT11_SEL));
222 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX4), P_Fld(uiLPDDR_MRR_Mapping[12], MRR_BIT_MUX4_MRR_BIT12_SEL) | P_Fld(uiLPDDR_MRR_Mapping[13], MRR_BIT_MUX4_MRR_BIT13_SEL) |
223 P_Fld(uiLPDDR_MRR_Mapping[14], MRR_BIT_MUX4_MRR_BIT14_SEL) | P_Fld(uiLPDDR_MRR_Mapping[15], MRR_BIT_MUX4_MRR_BIT15_SEL));
224 }
225
226
227 vSetPHY2ChannelMapping(p, backup_channel);
228 DramcBroadcastOnOff(backup_broadcast);
229 }
230
231
Set_DQO1_Pinmux_Mapping(DRAMC_CTX_T * p)232 static void Set_DQO1_Pinmux_Mapping(DRAMC_CTX_T *p)
233 {
234 U8 *uiLPDDR_DQO1_Mapping = NULL;
235 U8 backup_channel;
236 U32 backup_broadcast;
237 DRAM_CHANNEL_T chIdx = CHANNEL_A;
238
239
240 backup_channel = vGetPHY2ChannelMapping(p);
241 backup_broadcast = GetDramcBroadcast();
242
243 DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
244
245
246 for (chIdx = CHANNEL_A; chIdx < (int)p->support_channel_num; chIdx++)
247 {
248 vSetPHY2ChannelMapping(p, chIdx);
249
250 uiLPDDR_DQO1_Mapping = (U8 *)uiLPDDR4_O1_Mapping_POP[chIdx];
251
252
253 vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQ_SE_PINMUX_CTRL0), P_Fld(uiLPDDR_DQO1_Mapping[0], MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ0)
254 | P_Fld(uiLPDDR_DQO1_Mapping[1], MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ1)
255 | P_Fld(uiLPDDR_DQO1_Mapping[2], MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ2)
256 | P_Fld(uiLPDDR_DQO1_Mapping[3], MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ3)
257 | P_Fld(uiLPDDR_DQO1_Mapping[4], MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ4)
258 | P_Fld(uiLPDDR_DQO1_Mapping[5], MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ5)
259 | P_Fld(uiLPDDR_DQO1_Mapping[6], MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ6)
260 | P_Fld(uiLPDDR_DQO1_Mapping[7], MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ7));
261 vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQ_SE_PINMUX_CTRL1), P_Fld(uiLPDDR_DQO1_Mapping[8], MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ8)
262 | P_Fld(uiLPDDR_DQO1_Mapping[9], MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ9)
263 | P_Fld(uiLPDDR_DQO1_Mapping[10], MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ10)
264 | P_Fld(uiLPDDR_DQO1_Mapping[11], MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ11)
265 | P_Fld(uiLPDDR_DQO1_Mapping[12], MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ12)
266 | P_Fld(uiLPDDR_DQO1_Mapping[13], MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ13)
267 | P_Fld(uiLPDDR_DQO1_Mapping[14], MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ14)
268 | P_Fld(uiLPDDR_DQO1_Mapping[15], MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ15));
269 }
270
271
272 vSetPHY2ChannelMapping(p, backup_channel);
273 DramcBroadcastOnOff(backup_broadcast);
274 }
275
276
SetRankInfoToConf(DRAMC_CTX_T * p)277 static void SetRankInfoToConf(DRAMC_CTX_T *p)
278 {
279 #if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
280 EMI_SETTINGS *emi_set;
281 U32 u4value = 0;
282
283 emi_set = &g_default_emi_setting;
284
285 u4value = ((emi_set->EMI_CONA_VAL >> 17) & 0x1)? 0: 1;
286
287 vIO32WriteFldAlign(DRAMC_REG_SA_RESERVE, u4value, SA_RESERVE_SINGLE_RANK);
288
289 mcSHOW_JV_LOG_MSG(("Rank info: %d, CONA[0x%x]\n", u4value, emi_set->EMI_CONA_VAL));
290 #endif
291 return;
292 }
293
SetDramInfoToConf(DRAMC_CTX_T * p)294 static void SetDramInfoToConf(DRAMC_CTX_T *p)
295 {
296 vIO32WriteFldMulti_All(DRAMC_REG_SA_RESERVE,
297 P_Fld(p->dram_cbt_mode[RANK_0], SA_RESERVE_MODE_RK0) |
298 P_Fld(p->dram_cbt_mode[RANK_1], SA_RESERVE_MODE_RK1));
299
300 if(u2DFSGetHighestFreq(p) >= 2133)
301 {
302 vIO32WriteFldAlign_All(DRAMC_REG_SA_RESERVE, 1, SA_RESERVE_SUPPORT_4266);
303 }
304 }
305 #if 0
306 static void UpdateHighestFreqInDFSTbl(DRAMC_CTX_T *p, DRAM_PLL_FREQ_SEL_T new_freq_sel)
307 {
308 #if(FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0)
309 U16 u2HighestFreq = u2DFSGetHighestFreq(p);
310 DRAM_PLL_FREQ_SEL_T cur_freq_sel = 0;
311 U8 u1ShuffleIdx = 0;
312
313
314 cur_freq_sel = GetSelByFreq(p, u2HighestFreq);
315 if (cur_freq_sel == new_freq_sel)
316 return;
317
318 for (u1ShuffleIdx = 0; u1ShuffleIdx < DRAM_DFS_SRAM_MAX; u1ShuffleIdx++)
319 if (gFreqTbl[u1ShuffleIdx].freq_sel == cur_freq_sel)
320 break;
321
322 gFreqTbl[u1ShuffleIdx].freq_sel = new_freq_sel;
323
324 gUpdateHighestFreq = TRUE;
325 u2HighestFreq = u2DFSGetHighestFreq(p);
326
327 #if __ETT__
328 UpdateEttDFVSTblHighest(p, cur_freq_sel, new_freq_sel);
329 #endif
330 mcSHOW_DBG_MSG2(("[UpdateHighestFreqInDFSTbl] Get Highest Freq is %d\n", u2HighestFreq));
331 #endif
332 }
333
334 static void UpdateHighestFreqToDDR3733(DRAMC_CTX_T *p)
335 {
336 #if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
337 EMI_SETTINGS *emi_set;
338
339 emi_set = &g_default_emi_setting;
340
341 if (emi_set->highest_freq == 3733) {
342 UpdateHighestFreqInDFSTbl(p, LP4_DDR3733);
343 }
344 #endif
345 }
346 #endif
347 #ifdef SCRAMBLE_EN
348 #endif
349 #if 0
350 static void TzCfgScramble(DRAMC_CTX_T *p, U32 u4RandmKey, U32 u4EncryptType)
351 {
352 U32 u4ScrambleCFGAddr = DRAMC_REG_SCRAMBLE_CFG0;
353 U32 u4ScrambleCFGRGIdx = 0;
354
355 for(u4ScrambleCFGRGIdx = 0; u4ScrambleCFGRGIdx < 8; u4ScrambleCFGRGIdx++)
356 {
357 u4ScrambleCFGAddr += 4;
358 vIO32Write4B(DRAMC_REG_ADDR(u4ScrambleCFGAddr), u4RandmKey);
359 }
360
361 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SCRAMBLE_CFG8), P_Fld(1, SCRAMBLE_CFG8_SC_CMP_EN0) \
362 | P_Fld(0, SCRAMBLE_CFG8_SC_CMP_TYPE0));
363 vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SCRAMBLE_CFG9), 0xFFFF0000);
364 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SCRAMBLE_CFG8), P_Fld(u4EncryptType, SCRAMBLE_CFG8_SC_RETRUN_HUSKY) \
365 | P_Fld(1, SCRAMBLE_CFG8_SC_DDR_TYPE)
366 | P_Fld(1, SCRAMBLE_CFG8_SC_EN));
367 }
368 #endif
369
370
371 #if defined(DEVIATION) && !__ETT__
372 #include "deviation.h"
373 #define KEY_DEVIATION 0x4073
vInitDeviationVariable(void)374 static void vInitDeviationVariable(void)
375 {
376 DEVIATION_INFO_T* deviation_info_ptr;
377
378 deviation_info_ptr = (DEVIATION_INFO_T *) get_dbg_info_base(KEY_DEVIATION);
379
380 if (deviation_info_ptr->magic == DEVIATION_MAGIC_PATTERN)
381 {
382 if (deviation_info_ptr->ca_enable == ENABLE)
383 {
384 gSetSpecificedVref_Enable[0] = ENABLE;
385
386
387 if (deviation_info_ptr->ca_channel_bank == 4)
388 {
389 gSetSpecificedVref_All_ChRk[0] = ENABLE;
390 }
391 else
392 {
393 gSetSpecificedVref_Channel[0] = (deviation_info_ptr->ca_channel_bank >> 1) & 1;
394 gSetSpecificedVref_Rank[0] = deviation_info_ptr->ca_channel_bank & 1;
395 }
396 gSetSpecificedVref_Vref_Offset[0] = deviation_info_ptr->ca_offset;
397 }
398
399 if (deviation_info_ptr->rx_enable == ENABLE)
400 {
401 gSetSpecificedVref_Enable[1] = ENABLE;
402
403 if (deviation_info_ptr->rx_channel_bank == 4)
404 {
405 gSetSpecificedVref_All_ChRk[1] = ENABLE;
406 }
407 else
408 {
409 gSetSpecificedVref_Channel[1] = (deviation_info_ptr->rx_channel_bank >> 1) & 1;
410 gSetSpecificedVref_Rank[1] = deviation_info_ptr->rx_channel_bank & 1;
411 }
412 gSetSpecificedVref_Vref_Offset[1] = deviation_info_ptr->rx_offset;
413 }
414
415 if (deviation_info_ptr->tx_enable == ENABLE)
416 {
417 gSetSpecificedVref_Enable[2] = ENABLE;
418
419 if (deviation_info_ptr->tx_channel_bank == 4)
420 {
421 gSetSpecificedVref_All_ChRk[2] = ENABLE;
422 }
423 else
424 {
425 gSetSpecificedVref_Channel[2] = (deviation_info_ptr->tx_channel_bank >> 1) & 1;
426 gSetSpecificedVref_Rank[2] = deviation_info_ptr->tx_channel_bank & 1;
427 }
428 gSetSpecificedVref_Vref_Offset[2] = deviation_info_ptr->tx_offset;
429 }
430 }
431 }
432
vSetDeviationVariable(void)433 void vSetDeviationVariable(void)
434 {
435 DEVIATION_INFO_T* deviation_info_ptr;
436 U8 u1ChannelIdx, u1RankIdx, u1ByteIdx;
437
438 deviation_info_ptr = (DEVIATION_INFO_T *) get_dbg_info_base(KEY_DEVIATION);
439
440 for(u1ChannelIdx=0; u1ChannelIdx<2; u1ChannelIdx++)
441 {
442 for(u1RankIdx=0; u1RankIdx<2; u1RankIdx++)
443 {
444 deviation_info_ptr->dram_k_ca_vref_range[u1ChannelIdx][u1RankIdx] = (u1MR12Value[u1ChannelIdx][u1RankIdx][FSP_1]>>6) & 1;
445 deviation_info_ptr->dram_k_ca_vref_value[u1ChannelIdx][u1RankIdx] = u1MR12Value[u1ChannelIdx][u1RankIdx][FSP_1] & 0x3f;
446
447 deviation_info_ptr->dram_k_tx_vref_range[u1ChannelIdx][u1RankIdx] = (u1MR14Value[u1ChannelIdx][u1RankIdx][FSP_1]>>6)&1;
448 deviation_info_ptr->dram_k_tx_vref_value[u1ChannelIdx][u1RankIdx] = u1MR14Value[u1ChannelIdx][u1RankIdx][FSP_1] & 0x3f;
449
450 for(u1ByteIdx=0; u1ByteIdx<2; u1ByteIdx++)
451 {
452 deviation_info_ptr->dram_k_rx_vref_value[u1ChannelIdx][u1RankIdx][u1ByteIdx] = gFinalRXVrefDQ[u1ChannelIdx][u1RankIdx][u1ByteIdx];
453 }
454 }
455 }
456 }
457 #endif
458
Global_Option_Init(DRAMC_CTX_T * p)459 void Global_Option_Init(DRAMC_CTX_T *p)
460 {
461 //SaveCurrDramCtx(p);
462 vSetChannelNumber(p);
463 SetRankInfoToConf(p);
464 vSetRankNumber(p);
465 vSetFSPNumber(p);
466 #if (fcFOR_CHIP_ID == fc8195)
467 Set_DRAM_Pinmux_Sel(p);
468 #endif
469 Set_MRR_Pinmux_Mapping(p);
470 Set_DQO1_Pinmux_Mapping(p);
471
472 vInitGlobalVariablesByCondition(p);
473
474 #if ENABLE_TX_TRACKING
475 DramcDQSOSCInit();
476 #endif
477
478 #ifdef FOR_HQA_TEST_USED
479 HQA_measure_message_reset_all_data(p);
480 #endif
481
482 #if defined(DEVIATION) && !__ETT__
483 vInitDeviationVariable();
484 #endif
485 }
486
487
488 #if 0
489 static void RxDQSIsiPulseCG(DRAMC_CTX_T *p, U8 u1OnOff)
490 {
491 #if __A60868_TO_BE_PORTING__
492
493 mcSHOW_DBG_MSG4(("CH%u RX DQS ISI pulse CG: %u (0:disable, 1:enable)\n", u1OnOff));
494
495
496 #if (fcFOR_CHIP_ID == fcA60868)
497 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), u1OnOff, B0_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B0);
498 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6), u1OnOff, B1_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B1);
499 #else
500 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ10), u1OnOff, SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B0);
501 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ10), u1OnOff, SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B1);
502 #endif
503
504 return;
505 #endif
506 }
507 #endif
508 #if 0
509 static void OpenLoopModeSetting(DRAMC_CTX_T * p, DDR800_MODE_T eDDR800Mode)
510 {
511 #if __A60868_TO_BE_PORTING__
512
513
514 if (eDDR800Mode == DDR800_OPEN_LOOP)
515 {
516 vIO32WriteFldMulti_All(DDRPHY_MISC_CG_CTRL6, P_Fld(0x1, MISC_CG_CTRL6_RG_M_CK_OPENLOOP_MODE_EN)
517 | P_Fld(0x1, MISC_CG_CTRL6_RG_MCK4X_I_OPENLOOP_MODE_EN)
518 | P_Fld(0x1, MISC_CG_CTRL6_RG_CG_DDR400_MCK4X_I_OFF)
519 | P_Fld(0x0, MISC_CG_CTRL6_RG_DDR400_MCK4X_I_FORCE_ON)
520 | P_Fld(0x1, MISC_CG_CTRL6_RG_MCK4X_I_FB_CK_CG_OFF)
521 | P_Fld(0x1, MISC_CG_CTRL6_RG_MCK4X_Q_OPENLOOP_MODE_EN)
522 | P_Fld(0x1, MISC_CG_CTRL6_RG_CG_DDR400_MCK4X_Q_OFF)
523 | P_Fld(0x0, MISC_CG_CTRL6_RG_DDR400_MCK4X_Q_FORCE_ON)
524 | P_Fld(0x1, MISC_CG_CTRL6_RG_MCK4X_Q_FB_CK_CG_OFF)
525 | P_Fld(0x1, MISC_CG_CTRL6_RG_MCK4X_O_OPENLOOP_MODE_EN)
526 | P_Fld(0x1, MISC_CG_CTRL6_RG_CG_DDR400_MCK4X_O_OFF)
527 | P_Fld(0x0, MISC_CG_CTRL6_RG_DDR400_MCK4X_O_FORCE_ON)
528 | P_Fld(0x1, MISC_CG_CTRL6_RG_MCK4X_O_FB_CK_CG_OFF));
529
530 vIO32WriteFldAlign_All(DDRPHY_SHU_MISC2, 1, SHU_MISC2_M_CK_OPENLOOP_MODE_SEL);
531 }
532 #endif
533 }
534 #endif
535 #if __A60868_TO_BE_PORTING__
536 #endif
537 #if 0
538 static void APhyModeSetting(DRAMC_CTX_T * p, DDR800_MODE_T eMode, U8 *uDLL1, U8 *uMode, U8 *uDLL0)
539 {
540 #if __A60868_TO_BE_PORTING__
541
542 DDR800Mode_T DDR800Mode;
543
544 OpenLoopModeSetting(p, eMode);
545
546 if ((eMode == DDR800_CLOSE_LOOP) || (eMode == NORMAL_CLOSE_LOOP))
547 {
548 DDR800Mode.phypll_ddr400_en = 0;
549 DDR800Mode.ddr400_en_b0 = 0;
550 DDR800Mode.ddr400_en_b1 = 0;
551 DDR800Mode.ddr400_en_ca = 0;
552 DDR800Mode.dll_phdet_en_b0 = 1;
553 DDR800Mode.dll_phdet_en_b1 = 1;
554 DDR800Mode.dll_phdet_en_ca_cha = 1;
555 DDR800Mode.dll_phdet_en_ca_chb = 1;
556 DDR800Mode.phypll_ada_mck8x_en = 1;
557 DDR800Mode.ddr400_dqs_ps_b0 = 0;
558 DDR800Mode.ddr400_dqs_ps_b1 = 0;
559 DDR800Mode.ddr400_dq_ps_b0 = 0;
560 DDR800Mode.ddr400_dq_ps_b1 = 0;
561 DDR800Mode.ddr400_dqs_ps_ca = 0;
562 DDR800Mode.ddr400_dq_ps_ca = 0;
563 DDR800Mode.ddr400_semi_en_b0 = 0;
564 DDR800Mode.ddr400_semi_en_b1 = 0;
565 DDR800Mode.ddr400_semi_en_ca = 0;
566 DDR800Mode.ddr400_semi_open_en = 0;
567 DDR800Mode.pll0_ada_mck8x_chb_en = 1;
568 DDR800Mode.pll0_ada_mck8x_cha_en = 1;
569
570 if (p->frequency <= 400)
571 {
572 *uDLL1 = 1;
573 *uMode = 0;
574 *uDLL0 = 2;
575 }
576 else if (p->frequency <= 800)
577 {
578 if (vGet_Div_Mode(p) == DIV8_MODE)
579 {
580 *uDLL1 = 0;
581 *uMode = 0;
582 *uDLL0 = 2;
583 }
584 else
585 {
586 *uDLL1 = 0;
587 *uMode = 1;
588 *uDLL0 = 0;
589 }
590 }
591 else
592 {
593 *uDLL1 = 0;
594 *uMode = 0;
595 *uDLL0 = 2;
596 }
597 }
598 else if (eMode == DDR800_OPEN_LOOP)
599 {
600 DDR800Mode.phypll_ddr400_en = 1;
601 DDR800Mode.ddr400_en_b0 = 1;
602 DDR800Mode.ddr400_en_b1 = 1;
603 DDR800Mode.ddr400_en_ca = 1;
604 DDR800Mode.dll_phdet_en_b0 = 0;
605 DDR800Mode.dll_phdet_en_b1 = 0;
606 DDR800Mode.dll_phdet_en_ca_cha = 0;
607 DDR800Mode.dll_phdet_en_ca_chb = 0;
608 DDR800Mode.phypll_ada_mck8x_en = 0;
609 #if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
610 DDR800Mode.ddr400_dqs_ps_b0 = 0;
611 DDR800Mode.ddr400_dqs_ps_b1 = 0;
612 DDR800Mode.ddr400_dq_ps_b0 = 0;
613 DDR800Mode.ddr400_dq_ps_b1 = 0;
614 DDR800Mode.ddr400_dqs_ps_ca = 0;
615 DDR800Mode.ddr400_dq_ps_ca = 0;
616 #else
617 DDR800Mode.ddr400_dqs_ps_b0 = 1;
618 DDR800Mode.ddr400_dqs_ps_b1 = 1;
619 DDR800Mode.ddr400_dq_ps_b0 = 0;
620 DDR800Mode.ddr400_dq_ps_b1 = 0;
621 DDR800Mode.ddr400_dqs_ps_ca = 1;
622 DDR800Mode.ddr400_dq_ps_ca = 2;
623 #endif
624 DDR800Mode.ddr400_semi_en_b0 = 0;
625 DDR800Mode.ddr400_semi_en_b1 = 0;
626 DDR800Mode.ddr400_semi_en_ca = 0;
627 DDR800Mode.ddr400_semi_open_en = 0;
628 DDR800Mode.pll0_ada_mck8x_chb_en = 0;
629 DDR800Mode.pll0_ada_mck8x_cha_en = 0;
630 *uDLL1 = 0;
631 *uMode = 1;
632 *uDLL0 = 0;
633 }
634 else if (eMode == DDR800_SEMI_LOOP)
635 {
636 DDR800Mode.phypll_ddr400_en = 1;
637 DDR800Mode.ddr400_en_b0 = 1;
638 DDR800Mode.ddr400_en_b1 = 1;
639 DDR800Mode.ddr400_en_ca = 1;
640 DDR800Mode.dll_phdet_en_b0 = 0;
641 DDR800Mode.dll_phdet_en_b1 = 0;
642 DDR800Mode.dll_phdet_en_ca_cha = 1;
643 DDR800Mode.dll_phdet_en_ca_chb = 0;
644 DDR800Mode.phypll_ada_mck8x_en = 1;
645 #if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
646 DDR800Mode.ddr400_dqs_ps_b0 = 0;
647 DDR800Mode.ddr400_dqs_ps_b1 = 0;
648 DDR800Mode.ddr400_dq_ps_b0 = 0;
649 DDR800Mode.ddr400_dq_ps_b1 = 0;
650 DDR800Mode.ddr400_dqs_ps_ca = 0;
651 DDR800Mode.ddr400_dq_ps_ca = 0;
652 #else
653 DDR800Mode.ddr400_dqs_ps_b0 = 1;
654 DDR800Mode.ddr400_dqs_ps_b1 = 1;
655 DDR800Mode.ddr400_dq_ps_b0 = 0;
656 DDR800Mode.ddr400_dq_ps_b1 = 0;
657 DDR800Mode.ddr400_dqs_ps_ca = 1;
658 DDR800Mode.ddr400_dq_ps_ca = 2;
659 #endif
660 DDR800Mode.ddr400_semi_en_b0 = 1;
661 DDR800Mode.ddr400_semi_en_b1 = 1;
662 DDR800Mode.ddr400_semi_en_ca = 1;
663 DDR800Mode.ddr400_semi_open_en = 1;
664 DDR800Mode.pll0_ada_mck8x_chb_en = 0;
665 DDR800Mode.pll0_ada_mck8x_cha_en = 1;
666 *uDLL1 = 0;
667 *uMode = 1;
668 *uDLL0 = 2;
669 }
670 else
671 {
672 mcSHOW_ERR_MSG(("[FAIL] APhy mode incorrect !!!\n"));
673 #if __ETT__
674 while (1);
675 #endif
676 }
677
678
679 vIO32WriteFldAlign(DDRPHY_SHU_PLL1, DDR800Mode.phypll_ddr400_en, SHU_PLL1_RG_RPHYPLL_DDR400_EN);
680 //vIO32WriteFldAlign_All(DDRPHY_PLL4, DDR800Mode.phypll_ada_mck8x_en, PLL4_RG_RPHYPLL_ADA_MCK8X_EN);
681 vIO32WriteFldAlign_All(DDRPHY_SHU_B0_DQ6, DDR800Mode.ddr400_en_b0, SHU_B0_DQ6_RG_ARPI_DDR400_EN_B0);
682 vIO32WriteFldAlign_All(DDRPHY_SHU_B1_DQ6, DDR800Mode.ddr400_en_b1, SHU_B1_DQ6_RG_ARPI_DDR400_EN_B1);
683 vIO32WriteFldAlign_All(DDRPHY_SHU_CA_CMD6, DDR800Mode.ddr400_en_ca, SHU_CA_CMD6_RG_ARPI_DDR400_EN_CA);
684
685
686 vIO32WriteFldAlign_All(DDRPHY_SHU_B0_DLL0, DDR800Mode.dll_phdet_en_b0, SHU_B0_DLL0_RG_ARDLL_PHDET_EN_B0_SHU);
687 vIO32WriteFldAlign_All(DDRPHY_SHU_B1_DLL0, DDR800Mode.dll_phdet_en_b1, SHU_B1_DLL0_RG_ARDLL_PHDET_EN_B1_SHU);
688 vIO32WriteFldAlign(DDRPHY_SHU_CA_DLL0, DDR800Mode.dll_phdet_en_ca_cha, SHU_CA_DLL0_RG_ARDLL_PHDET_EN_CA_SHU);
689 vIO32WriteFldAlign(DDRPHY_SHU_CA_DLL0 + SHIFT_TO_CHB_ADDR, DDR800Mode.dll_phdet_en_ca_chb, SHU_CA_DLL0_RG_ARDLL_PHDET_EN_CA_SHU);
690 vIO32WriteFldAlign(DDRPHY_SHU_PLL22, DDR800Mode.phypll_ada_mck8x_en, SHU_PLL22_RG_RPHYPLL_ADA_MCK8X_EN_SHU);
691 vIO32WriteFldAlign_All(DDRPHY_SHU_PLL0, DDR800Mode.pll0_ada_mck8x_chb_en, SHU_PLL0_ADA_MCK8X_CHB_EN);
692 vIO32WriteFldAlign_All(DDRPHY_SHU_PLL0, DDR800Mode.pll0_ada_mck8x_cha_en, SHU_PLL0_ADA_MCK8X_CHA_EN);
693
694
695 vIO32WriteFldAlign_All(DDRPHY_SHU_B0_DQ9, DDR800Mode.ddr400_dqs_ps_b0, SHU_B0_DQ9_RG_DDR400_DQS_PS_B0);
696 vIO32WriteFldAlign_All(DDRPHY_SHU_B1_DQ9, DDR800Mode.ddr400_dqs_ps_b1, SHU_B1_DQ9_RG_DDR400_DQS_PS_B1);
697 vIO32WriteFldAlign_All(DDRPHY_SHU_B0_DQ9, DDR800Mode.ddr400_dq_ps_b0, SHU_B0_DQ9_RG_DDR400_DQ_PS_B0);
698 vIO32WriteFldAlign_All(DDRPHY_SHU_B1_DQ9, DDR800Mode.ddr400_dq_ps_b1, SHU_B1_DQ9_RG_DDR400_DQ_PS_B1);
699 vIO32WriteFldAlign_All(DDRPHY_SHU_CA_CMD9, DDR800Mode.ddr400_dqs_ps_ca, SHU_CA_CMD9_RG_DDR400_DQS_PS_CA);
700 vIO32WriteFldAlign_All(DDRPHY_SHU_CA_CMD9, DDR800Mode.ddr400_dq_ps_ca, SHU_CA_CMD9_RG_DDR400_DQ_PS_CA);
701
702
703 vIO32WriteFldAlign_All(DDRPHY_SHU_B0_DQ9, DDR800Mode.ddr400_semi_en_b0, SHU_B0_DQ9_RG_DDR400_SEMI_EN_B0);
704 vIO32WriteFldAlign_All(DDRPHY_SHU_B1_DQ9, DDR800Mode.ddr400_semi_en_b1, SHU_B1_DQ9_RG_DDR400_SEMI_EN_B1);
705 vIO32WriteFldAlign_All(DDRPHY_SHU_CA_CMD9, DDR800Mode.ddr400_semi_en_ca, SHU_CA_CMD9_RG_DDR400_SEMI_EN_CA);
706 vIO32WriteFldAlign_All(DDRPHY_SHU_PLL0, DDR800Mode.ddr400_semi_open_en, SHU_PLL0_RG_DDR400_SEMI_OPEN_EN);
707 #endif
708 }
709
710 static void DDRDllModeSetting(DRAMC_CTX_T * p)
711 {
712 #if __A60868_TO_BE_PORTING__
713 U8 uDLL1 = 0, uMode = 0, uDLL0 = 2;
714
715 APhyModeSetting(p, vGet_DDR800_Mode(p), &uDLL1, &uMode, &uDLL0);
716
717 vIO32WriteFldAlign_All(DDRPHY_SHU_B0_DLL1, uDLL1, SHU_B0_DLL1_FRATE_EN_B0);
718 vIO32WriteFldAlign_All(DDRPHY_SHU_B1_DLL1, uDLL1, SHU_B1_DLL1_FRATE_EN_B1);
719 vIO32WriteFldAlign_All(DDRPHY_SHU_CA_DLL2, uDLL1, SHU_CA_DLL2_FRATE_EN);
720
721 vIO32WriteFldAlign_All(DDRPHY_SHU_B0_DQ6, uMode, SHU_B0_DQ6_RG_TX_ARDQ_SER_MODE_B0);
722 vIO32WriteFldAlign_All(DDRPHY_SHU_B1_DQ6, uMode, SHU_B1_DQ6_RG_TX_ARDQ_SER_MODE_B1);
723 vIO32WriteFldAlign_All(DDRPHY_SHU_CA_CMD6, uMode, SHU_CA_CMD6_RG_TX_ARCMD_SER_MODE);
724 vIO32WriteFldAlign_All(DDRPHY_SHU_B0_DQ6, uMode, SHU_B0_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B0);
725 vIO32WriteFldAlign_All(DDRPHY_SHU_B1_DQ6, uMode, SHU_B1_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B1);
726 vIO32WriteFldAlign_All(DDRPHY_SHU_CA_CMD6, uMode, SHU_CA_CMD6_RG_RX_ARCMD_RANK_SEL_SER_MODE);
727
728 vIO32WriteFldAlign_All(DDRPHY_SHU_B0_DLL0, uDLL0, SHU_B0_DLL0_RG_ARDLL_DIV_MCTL_B0);
729 vIO32WriteFldAlign_All(DDRPHY_SHU_B1_DLL0, uDLL0, SHU_B1_DLL0_RG_ARDLL_DIV_MCTL_B1);
730 vIO32WriteFldAlign_All(DDRPHY_SHU_CA_DLL0, uDLL0, SHU_CA_DLL0_RG_ARDLL_DIV_MCTL_CA);
731 #endif
732 }
733
734 static void DDRPhyPLLSetting(DRAMC_CTX_T *p)
735 {
736 #if __A60868_TO_BE_PORTING__
737
738 U8 u1CAP_SEL;
739 U8 u1MIDPICAP_SEL;
740 U8 u1VTH_SEL;
741 U16 u2SDM_PCW = 0;
742 U8 u1CA_DLL_Mode[2];
743 U8 iChannel = CHANNEL_A;
744 U8 u1BRPI_MCTL_EN_CA = 0;
745 U8 u1PCW_CHG = 0;
746 #if ENABLE_TMRRI_NEW_MODE
747 U8 u1RankIdx;
748 #endif
749 U8 u1Gain_Ca_ChA = 0, u1Gain_Ca_ChB = 0;
750 U8 u1CurrShuLevel = 0;
751
752 u1VTH_SEL = 0x2;
753
754 #if (fcFOR_CHIP_ID == fcLafite)
755 if (p->frequency <= 400)
756 {
757 u1CAP_SEL = 0xb;
758 }
759 else if (p->frequency <= 600)
760 {
761 u1CAP_SEL = 0xf;
762 }
763 else if (p->frequency <= 800)
764 {
765 u1CAP_SEL = 0xb;
766 }
767 else if (p->frequency <= 1200)
768 {
769 u1CAP_SEL = 0x8;
770 }
771 else if (p->frequency <= 1333)
772 {
773 u1CAP_SEL = 0x8;
774 }
775 else if (p->frequency <= 1600)
776 {
777 u1CAP_SEL = 0x4;
778 }
779 else if (p->frequency <= 1866)
780 {
781 u1CAP_SEL = 0x2;
782 }
783 else
784 {
785 u1CAP_SEL = 0x1;
786 }
787
788 if (p->frequency <= 933)
789 {
790 u1MIDPICAP_SEL = 0x2;
791 }
792 else if (p->frequency <= 1200)
793 {
794 u1MIDPICAP_SEL = 0x3;
795 }
796 else if (p->frequency <= 1333)
797 {
798 u1MIDPICAP_SEL = 0x3;
799 }
800 else if (p->frequency <= 1600)
801 {
802 u1MIDPICAP_SEL = 0x2;
803 }
804 else if (p->frequency <= 1866)
805 {
806 u1MIDPICAP_SEL = 0x1;
807 }
808 else
809 {
810 u1MIDPICAP_SEL = 0x0;
811 }
812 #if EMI_LPBK_USE_DDR_800
813 if (p->frequency == 800)
814 {
815 u1CAP_SEL = 0xf;
816 }
817 #endif
818 #endif
819
820 vIO32WriteFldAlign_All(DDRPHY_SHU_PLL4, 0x0, SHU_PLL4_RG_RPHYPLL_RESERVED);
821 vIO32WriteFldAlign_All(DDRPHY_SHU_PLL6, 0x0, SHU_PLL6_RG_RCLRPLL_RESERVED);
822
823 #if (fcFOR_CHIP_ID == fcLafite)
824 #if DLL_ASYNC_MODE
825 u1BRPI_MCTL_EN_CA = 1;
826 u1CA_DLL_Mode[CHANNEL_A] = u1CA_DLL_Mode[CHANNEL_B] = DLL_MASTER;
827 vIO32WriteFldAlign(DDRPHY_MISC_SHU_OPT + ((U32)CHANNEL_A << POS_BANK_NUM), 1, MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN);
828 vIO32WriteFldAlign(DDRPHY_MISC_SHU_OPT + SHIFT_TO_CHB_ADDR, 1, MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN);
829 vIO32WriteFldMulti(DDRPHY_CKMUX_SEL + ((U32)CHANNEL_A << POS_BANK_NUM), P_Fld(0, CKMUX_SEL_FMEM_CK_MUX) | P_Fld(0, CKMUX_SEL_FB_CK_MUX));
830 vIO32WriteFldMulti(DDRPHY_CKMUX_SEL + SHIFT_TO_CHB_ADDR, P_Fld(2, CKMUX_SEL_FMEM_CK_MUX) | P_Fld(2, CKMUX_SEL_FB_CK_MUX));
831 #else
832 u1CA_DLL_Mode[CHANNEL_A] = DLL_MASTER;
833 u1CA_DLL_Mode[CHANNEL_B] = DLL_SLAVE;
834 vIO32WriteFldAlign(DDRPHY_MISC_SHU_OPT + ((U32)CHANNEL_A << POS_BANK_NUM), 1, MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN);
835 vIO32WriteFldAlign(DDRPHY_MISC_SHU_OPT + SHIFT_TO_CHB_ADDR, 2, MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN);
836 vIO32WriteFldMulti(DDRPHY_CKMUX_SEL + ((U32)CHANNEL_A << POS_BANK_NUM), P_Fld(1, CKMUX_SEL_FMEM_CK_MUX) | P_Fld(1, CKMUX_SEL_FB_CK_MUX));
837 vIO32WriteFldMulti(DDRPHY_CKMUX_SEL + SHIFT_TO_CHB_ADDR, P_Fld(1, CKMUX_SEL_FMEM_CK_MUX) | P_Fld(1, CKMUX_SEL_FB_CK_MUX));
838 #endif
839
840 #if ENABLE_DLL_ALL_SLAVE_MODE
841 if ((p->frequency <= 933) && (vGet_DDR800_Mode(p) != DDR800_SEMI_LOOP))
842 {
843 u1CA_DLL_Mode[CHANNEL_A] = u1CA_DLL_Mode[CHANNEL_B] = DLL_SLAVE;
844 }
845 #endif
846
847 if (u1CA_DLL_Mode[CHANNEL_A] == DLL_SLAVE)
848 {
849 vIO32WriteFldAlign_All(DRAMC_REG_SHU_DVFSCTL, 1, SHU_DVFSCTL_R_BYPASS_1ST_DLL);
850 }
851 else
852 {
853 vIO32WriteFldAlign_All(DRAMC_REG_SHU_DVFSCTL, 0, SHU_DVFSCTL_R_BYPASS_1ST_DLL);
854 }
855
856 for (iChannel = CHANNEL_A; iChannel <= CHANNEL_B; iChannel++)
857 {
858 if (u1CA_DLL_Mode[iChannel] == DLL_MASTER)
859 {
860 vIO32WriteFldMulti(DDRPHY_SHU_CA_DLL0 + ((U32)iChannel << POS_BANK_NUM), P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_PHDET_OUT_SEL_CA)
861 | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_PHDET_IN_SWAP_CA)
862 | P_Fld(0x6, SHU_CA_DLL0_RG_ARDLL_GAIN_CA)
863 | P_Fld(0x9, SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA)
864 | P_Fld(0x8, SHU_CA_DLL0_RG_ARDLL_P_GAIN_CA)
865 | P_Fld(0x1, SHU_CA_DLL0_RG_ARDLL_PHJUMP_EN_CA)
866 | P_Fld(0x1, SHU_CA_DLL0_RG_ARDLL_PHDIV_CA)
867 | P_Fld(0x1, SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA));
868 vIO32WriteFldMulti(DDRPHY_SHU_CA_DLL1 + ((U32)iChannel << POS_BANK_NUM), P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA) | P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_FASTPJ_CK_SEL_CA));
869 vIO32WriteFldAlign(DDRPHY_SHU_CA_CMD9 + ((U32)iChannel << POS_BANK_NUM), 1, SHU_CA_CMD9_RG_DLL_FAST_PSJP_CA);
870 }
871 else
872 {
873 vIO32WriteFldMulti(DDRPHY_SHU_CA_DLL0 + ((U32)iChannel << POS_BANK_NUM), P_Fld(0x1, SHU_CA_DLL0_RG_ARDLL_PHDET_OUT_SEL_CA)
874 | P_Fld(0x1, SHU_CA_DLL0_RG_ARDLL_PHDET_IN_SWAP_CA)
875 | P_Fld(0x7, SHU_CA_DLL0_RG_ARDLL_GAIN_CA)
876 | P_Fld(0x7, SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA)
877 | P_Fld(0x8, SHU_CA_DLL0_RG_ARDLL_P_GAIN_CA)
878 | P_Fld(0x1, SHU_CA_DLL0_RG_ARDLL_PHJUMP_EN_CA)
879 | P_Fld(0x1, SHU_CA_DLL0_RG_ARDLL_PHDIV_CA)
880 | P_Fld(0x0, SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA));
881 vIO32WriteFldMulti(DDRPHY_SHU_CA_DLL1 + ((U32)iChannel << POS_BANK_NUM), P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA) | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_FASTPJ_CK_SEL_CA));
882 vIO32WriteFldAlign(DDRPHY_SHU_CA_CMD9 + ((U32)iChannel << POS_BANK_NUM), 0, SHU_CA_CMD9_RG_DLL_FAST_PSJP_CA);
883 }
884 }
885 #endif
886
887 #if (fcFOR_CHIP_ID == fcLafite)
888 u1CurrShuLevel = vGet_Current_SRAMIdx(p);
889 if ((u1CurrShuLevel == SRAM_SHU4) || (u1CurrShuLevel == SRAM_SHU6))
890 {
891 vIO32WriteFldAlign_All(DDRPHY_SHU_B0_DLL0, 0x8, SHU_B0_DLL0_RG_ARDLL_GAIN_B0);
892 vIO32WriteFldAlign_All(DDRPHY_SHU_B1_DLL0, 0x8, SHU_B1_DLL0_RG_ARDLL_GAIN_B1);
893 u1Gain_Ca_ChA = u4IO32ReadFldAlign(DDRPHY_SHU_CA_DLL0, SHU_CA_DLL0_RG_ARDLL_GAIN_CA);
894 u1Gain_Ca_ChB = u4IO32ReadFldAlign(DDRPHY_SHU_CA_DLL0 + SHIFT_TO_CHB_ADDR, SHU_CA_DLL0_RG_ARDLL_GAIN_CA);
895 u1Gain_Ca_ChA += 1;
896 u1Gain_Ca_ChB += 1;
897 vIO32WriteFldAlign(DDRPHY_SHU_CA_DLL0, u1Gain_Ca_ChA, SHU_CA_DLL0_RG_ARDLL_GAIN_CA);
898 vIO32WriteFldAlign(DDRPHY_SHU_CA_DLL0 + SHIFT_TO_CHB_ADDR, u1Gain_Ca_ChB, SHU_CA_DLL0_RG_ARDLL_GAIN_CA);
899 }
900 #endif
901
902 U32 u4RegBackupAddress[] =
903 {
904 (DDRPHY_B0_DQ7),
905 (DDRPHY_B1_DQ7),
906 (DDRPHY_CA_CMD7),
907 (DDRPHY_B0_DQ7 + SHIFT_TO_CHB_ADDR),
908 (DDRPHY_B1_DQ7 + SHIFT_TO_CHB_ADDR),
909 (DDRPHY_CA_CMD7 + SHIFT_TO_CHB_ADDR),
910 };
911
912 //if(p->vendor_id==VENDOR_SAMSUNG && p->dram_type==TYPE_LPDDR3)
913 {
914 #if 0
915 mcSHOW_DBG_MSG(("DDRPhyPLLSetting-DMSUS\n"));
916 vIO32WriteFldAlign_All(DDRPHY_MISC_SPM_CTRL0, 0x0, MISC_SPM_CTRL0_PHY_SPM_CTL0);
917 vIO32WriteFldAlign_All(DDRPHY_MISC_SPM_CTRL2, 0x0, MISC_SPM_CTRL2_PHY_SPM_CTL2);
918 vIO32WriteFldMulti_All(DDRPHY_MISC_SPM_CTRL1, P_Fld(0x1, MISC_SPM_CTRL1_RG_ARDMSUS_10) | P_Fld(0x1, MISC_SPM_CTRL1_RG_ARDMSUS_10_B0)
919 | P_Fld(0x1, MISC_SPM_CTRL1_RG_ARDMSUS_10_B1) | P_Fld(0x1, MISC_SPM_CTRL1_RG_ARDMSUS_10_CA));
920 #else
921 DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32));
922 vIO32WriteFldMulti_All(DDRPHY_B0_DQ7, P_Fld(0x1, B0_DQ7_RG_TX_ARDQ_PULL_DN_B0) | P_Fld(0x1, B0_DQ7_RG_TX_ARDQM0_PULL_DN_B0)
923 | P_Fld(0x1, B0_DQ7_RG_TX_ARDQS0_PULL_DN_B0) | P_Fld(0x1, B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0));
924 vIO32WriteFldMulti_All(DDRPHY_B1_DQ7, P_Fld(0x1, B1_DQ7_RG_TX_ARDQ_PULL_DN_B1) | P_Fld(0x1, B1_DQ7_RG_TX_ARDQM0_PULL_DN_B1)
925 | P_Fld(0x1, B1_DQ7_RG_TX_ARDQS0_PULL_DN_B1) | P_Fld(0x1, B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1));
926 vIO32WriteFldMulti_All(DDRPHY_CA_CMD7, P_Fld(0x1, CA_CMD7_RG_TX_ARCMD_PULL_DN) | P_Fld(0x1, CA_CMD7_RG_TX_ARCS_PULL_DN)
927 | P_Fld(0x1, CA_CMD7_RG_TX_ARCLK_PULL_DN) | P_Fld(0x1, CA_CMD7_RG_TX_ARCLKB_PULL_DN));
928
929
930 vIO32WriteFldAlign_All(DDRPHY_CA_CMD2, 1, CA_CMD2_RG_TX_ARCMD_OE_DIS);
931 #endif
932 }
933
934
935 vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL0, 0x0, MISC_CG_CTRL0_CLK_MEM_SEL);
936
937 #ifdef USE_CLK26M
938 vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL0, 0x1, MISC_CG_CTRL0_RG_DA_RREF_CK_SEL);
939 #endif
940
941
942 vIO32WriteFldAlign_All(DDRPHY_CA_DLL_ARPI2, 0x0, CA_DLL_ARPI2_RG_ARDLL_PHDET_EN_CA);
943 vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI2, 0x0, B0_DLL_ARPI2_RG_ARDLL_PHDET_EN_B0);
944 vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI2, 0x0, B1_DLL_ARPI2_RG_ARDLL_PHDET_EN_B1);
945
946
947 vIO32WriteFldMulti_All(DDRPHY_B0_DLL_ARPI2, P_Fld(0x1, B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0)
948 | P_Fld(0x1, B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0)
949 | P_Fld(0x1, B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0)
950 | P_Fld(0x1, B0_DLL_ARPI2_RG_ARPI_CG_FB_B0)
951 | P_Fld(0x1, B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0)
952 | P_Fld(0x1, B0_DLL_ARPI2_RG_ARPI_CG_DQM_B0)
953 | P_Fld(0x1, B0_DLL_ARPI2_RG_ARPI_CG_DQ_B0)
954 | P_Fld(0x1, B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0)
955 | P_Fld(0x1, B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0));
956 vIO32WriteFldMulti_All(DDRPHY_B1_DLL_ARPI2, P_Fld(0x1, B1_DLL_ARPI2_RG_ARPI_CG_MCK_B1)
957 | P_Fld(0x1, B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1)
958 | P_Fld(0x1, B1_DLL_ARPI2_RG_ARPI_CG_MCTL_B1)
959 | P_Fld(0x1, B1_DLL_ARPI2_RG_ARPI_CG_FB_B1)
960 | P_Fld(0x1, B1_DLL_ARPI2_RG_ARPI_CG_DQS_B1)
961 | P_Fld(0x1, B1_DLL_ARPI2_RG_ARPI_CG_DQM_B1)
962 | P_Fld(0x1, B1_DLL_ARPI2_RG_ARPI_CG_DQ_B1)
963 | P_Fld(0x1, B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1)
964 | P_Fld(0x1, B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1));
965 vIO32WriteFldMulti_All(DDRPHY_CA_DLL_ARPI2, P_Fld(0x1, CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA)
966 | P_Fld(0x1, CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA)
967 | P_Fld(0x1, CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA)
968 | P_Fld(0x1, CA_DLL_ARPI2_RG_ARPI_CG_FB_CA)
969 | P_Fld(0x1, CA_DLL_ARPI2_RG_ARPI_CG_CS)
970 | P_Fld(0x1, CA_DLL_ARPI2_RG_ARPI_CG_CLK)
971 | P_Fld(0x1, CA_DLL_ARPI2_RG_ARPI_CG_CMD)
972 | P_Fld(0x1, CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN)
973 | P_Fld(0x1, CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA));
974
975
976 vIO32WriteFldMulti_All(DDRPHY_SHU_B0_DQ6, P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_MIDPI_EN_B0)
977 | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B0));
978 vIO32WriteFldMulti_All(DDRPHY_SHU_B1_DQ6, P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_MIDPI_EN_B1)
979 | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B1));
980 vIO32WriteFldMulti_All(DDRPHY_SHU_CA_CMD6, P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_MIDPI_EN_CA)
981 | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_MIDPI_CKDIV4_EN_CA));
982
983
984 vIO32WriteFldAlign_All(DDRPHY_CA_DLL_ARPI0, 0x0, CA_DLL_ARPI0_RG_ARPI_RESETB_CA);
985 vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI0, 0x0, B0_DLL_ARPI0_RG_ARPI_RESETB_B0);
986 vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI0, 0x0, B1_DLL_ARPI0_RG_ARPI_RESETB_B1);
987 mcDELAY_US(1);
988
989
990 vIO32WriteFldMulti_All(DDRPHY_PLL4, P_Fld(0x0, PLL4_RG_RPHYPLL_ADA_MCK8X_EN)
991 | P_Fld(0x0, PLL4_RG_RPHYPLL_RESETB));
992
993
994 vIO32WriteFldAlign_All(DDRPHY_PLL1, 0x0, PLL1_RG_RPHYPLL_EN);
995 vIO32WriteFldAlign_All(DDRPHY_PLL2, 0x0, PLL2_RG_RCLRPLL_EN);
996
997
998 #ifdef USE_CLK26M
999 vIO32WriteFldMulti_All(DDRPHY_SHU_PLL8, P_Fld(0x0, SHU_PLL8_RG_RPHYPLL_POSDIV) | P_Fld(0x0, SHU_PLL8_RG_RPHYPLL_PREDIV));
1000 vIO32WriteFldMulti_All(DDRPHY_SHU_PLL10, P_Fld(0x0, SHU_PLL10_RG_RCLRPLL_POSDIV) | P_Fld(0x0, SHU_PLL10_RG_RCLRPLL_PREDIV));
1001 #else
1002 vIO32WriteFldMulti_All(DDRPHY_SHU_PLL8, P_Fld(0x0, SHU_PLL8_RG_RPHYPLL_POSDIV) | P_Fld(0x1, SHU_PLL8_RG_RPHYPLL_PREDIV));
1003 vIO32WriteFldMulti_All(DDRPHY_SHU_PLL10, P_Fld(0x0, SHU_PLL10_RG_RCLRPLL_POSDIV) | P_Fld(0x1, SHU_PLL10_RG_RCLRPLL_PREDIV));
1004 #endif
1005
1006 if (p->frequency == 2133)
1007 {
1008 u2SDM_PCW = 0xa400;
1009 }
1010 else if (p->frequency == 1866)
1011 {
1012 #if ENABLE_FIX_SHORT_PLUSE
1013 u2SDM_PCW = 0x7b00;
1014 #else
1015 u2SDM_PCW = 0x8f00;
1016 #endif
1017 }
1018 else if (p->frequency == 1600 || p->frequency == 800 || p->frequency == 400)
1019 {
1020 #if ENABLE_FIX_SHORT_PLUSE
1021 if (p->frequency == 1600)
1022 u2SDM_PCW = 0x6c00;
1023 #else
1024 if (p->frequency == 1600)
1025 u2SDM_PCW = 0x7700;
1026 else if (p->frequency == 800)
1027 u2SDM_PCW = 0x7600;
1028 #endif
1029 else if ((p->frequency == 400) && (vGet_DDR800_Mode(p) == DDR800_OPEN_LOOP))
1030 u2SDM_PCW = 0x3c00;
1031 else if (p->frequency == 400)
1032 u2SDM_PCW = 0x7e00;
1033 else
1034 u2SDM_PCW = 0x7b00;
1035
1036 #if EMI_LPBK_USE_DDR_800
1037 if (p->frequency == 800)
1038 {
1039 vIO32WriteFldAlign_All(DDRPHY_SHU_PLL8, 0x1, SHU_PLL8_RG_RPHYPLL_POSDIV);
1040 vIO32WriteFldAlign_All(DDRPHY_SHU_PLL10, 0x1, SHU_PLL10_RG_RCLRPLL_POSDIV);
1041 }
1042 #endif
1043 }
1044 else if (p->frequency == 1333 || p->frequency == 667)
1045 {
1046 u2SDM_PCW = 0x6600;
1047 }
1048 else if (p->frequency == 1200)
1049 {
1050 #if ENABLE_FIX_SHORT_PLUSE
1051 u2SDM_PCW = 0x5100;
1052 #else
1053 u2SDM_PCW = 0x5c00;
1054 #endif
1055 }
1056 else if (p->frequency == 1140)
1057 {
1058 u2SDM_PCW = 0x5700;
1059 }
1060
1061 else if (p->frequency == 933)
1062 {
1063 u2SDM_PCW = 0x8f00;
1064 }
1065 else if (p->frequency == 600)
1066 {
1067 u2SDM_PCW = 0x5c00;
1068 }
1069 else if (p->frequency == 467)
1070 {
1071 u2SDM_PCW = 0x4700;
1072 }
1073
1074
1075 vIO32WriteFldMulti_All(DDRPHY_SHU_PLL5, P_Fld(u2SDM_PCW, SHU_PLL5_RG_RPHYPLL_SDM_PCW)
1076 | P_Fld(0x0, SHU_PLL5_RG_RPHYPLL_SDM_FRA_EN));
1077 vIO32WriteFldMulti_All(DDRPHY_SHU_PLL7, P_Fld(u2SDM_PCW, SHU_PLL7_RG_RCLRPLL_SDM_PCW)
1078 | P_Fld(0x0, SHU_PLL7_RG_RCLRPLL_SDM_FRA_EN));
1079
1080 #if (fcFOR_CHIP_ID == fcLafite)
1081 DDRDllModeSetting(p);
1082 #endif
1083
1084 vIO32WriteFldAlign_All(DDRPHY_CA_DLL_ARPI0, 0, CA_DLL_ARPI0_RG_ARMCTLPLL_CK_SEL_CA);
1085 vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI0, 0, B0_DLL_ARPI0_RG_ARMCTLPLL_CK_SEL_B0);
1086 vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI0, 0, B1_DLL_ARPI0_RG_ARMCTLPLL_CK_SEL_B1);
1087 vIO32WriteFldAlign_All(DDRPHY_CA_DLL_ARPI1, 0, CA_DLL_ARPI1_RG_ARPI_CLKIEN_JUMP_EN);
1088 vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI1, 0, B0_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B0);
1089 vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI1, 0, B1_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B1);
1090
1091
1092 vIO32WriteFldMulti_All(DDRPHY_SHU_B0_DQ6, P_Fld(u1VTH_SEL, SHU_B0_DQ6_RG_ARPI_MIDPI_VTH_SEL_B0)
1093 | P_Fld(u1CAP_SEL, SHU_B0_DQ6_RG_ARPI_CAP_SEL_B0)
1094 | P_Fld(u1MIDPICAP_SEL, SHU_B0_DQ6_RG_ARPI_MIDPI_CAP_SEL_B0));
1095 vIO32WriteFldMulti_All(DDRPHY_SHU_B1_DQ6, P_Fld(u1VTH_SEL, SHU_B1_DQ6_RG_ARPI_MIDPI_VTH_SEL_B1)
1096 | P_Fld(u1CAP_SEL, SHU_B1_DQ6_RG_ARPI_CAP_SEL_B1)
1097 | P_Fld(u1MIDPICAP_SEL, SHU_B1_DQ6_RG_ARPI_MIDPI_CAP_SEL_B1));
1098 vIO32WriteFldMulti_All(DDRPHY_SHU_CA_CMD6, P_Fld(u1VTH_SEL, SHU_CA_CMD6_RG_ARPI_MIDPI_VTH_SEL_CA)
1099 | P_Fld(u1CAP_SEL, SHU_CA_CMD6_RG_ARPI_CAP_SEL_CA)
1100 | P_Fld(u1MIDPICAP_SEL, SHU_CA_CMD6_RG_ARPI_MIDPI_CAP_SEL_CA));
1101
1102
1103 vIO32WriteFldAlign_All(DDRPHY_PLL1, 0x1, PLL1_RG_RPHYPLL_EN);
1104 vIO32WriteFldAlign_All(DDRPHY_PLL2, 0x1, PLL2_RG_RCLRPLL_EN);
1105 mcDELAY_US(100);
1106
1107
1108 if (p->frequency > 933)
1109 {
1110 vIO32WriteFldMulti_All(DDRPHY_SHU_B0_DQ6, P_Fld(0x1, SHU_B0_DQ6_RG_ARPI_MIDPI_EN_B0)
1111 | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B0));
1112 vIO32WriteFldMulti_All(DDRPHY_SHU_B1_DQ6, P_Fld(0x1, SHU_B1_DQ6_RG_ARPI_MIDPI_EN_B1)
1113 | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B1));
1114 vIO32WriteFldMulti_All(DDRPHY_SHU_CA_CMD6, P_Fld(0x1, SHU_CA_CMD6_RG_ARPI_MIDPI_EN_CA)
1115 | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_MIDPI_CKDIV4_EN_CA));
1116 }
1117 else
1118 {
1119 if ((p->frequency == 400) && (vGet_DDR800_Mode(p) != DDR800_CLOSE_LOOP))
1120 {
1121 vIO32WriteFldMulti_All(DDRPHY_SHU_B0_DQ6, P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_MIDPI_EN_B0)
1122 | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B0));
1123 vIO32WriteFldMulti_All(DDRPHY_SHU_B1_DQ6, P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_MIDPI_EN_B1)
1124 | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B1));
1125 if (vGet_DDR800_Mode(p) == DDR800_SEMI_LOOP)
1126 {
1127
1128 vIO32WriteFldAlign_All(DDRPHY_SHU_CA_CMD6, 0x0, SHU_CA_CMD6_RG_ARPI_MIDPI_EN_CA);
1129 vIO32WriteFldAlign(DDRPHY_SHU_CA_CMD6, 0x1, SHU_CA_CMD6_RG_ARPI_MIDPI_CKDIV4_EN_CA);
1130 vIO32WriteFldAlign(DDRPHY_SHU_CA_CMD6 + SHIFT_TO_CHB_ADDR, 0x0, SHU_CA_CMD6_RG_ARPI_MIDPI_CKDIV4_EN_CA);
1131 }
1132 else
1133 {
1134 vIO32WriteFldMulti_All(DDRPHY_SHU_CA_CMD6, P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_MIDPI_EN_CA)
1135 | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_MIDPI_CKDIV4_EN_CA));
1136 }
1137 }
1138 else
1139 {
1140
1141 vIO32WriteFldMulti_All(DDRPHY_SHU_B0_DQ6, P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_MIDPI_EN_B0)
1142 | P_Fld(0x1, SHU_B0_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B0));
1143 vIO32WriteFldMulti_All(DDRPHY_SHU_B1_DQ6, P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_MIDPI_EN_B1)
1144 | P_Fld(0x1, SHU_B1_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B1));
1145 vIO32WriteFldMulti_All(DDRPHY_SHU_CA_CMD6, P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_MIDPI_EN_CA)
1146 | P_Fld(0x1, SHU_CA_CMD6_RG_ARPI_MIDPI_CKDIV4_EN_CA));
1147 }
1148 }
1149 mcDELAY_US(1);
1150
1151
1152 vIO32WriteFldAlign_All(DDRPHY_CA_DLL_ARPI0, 0x1, CA_DLL_ARPI0_RG_ARPI_RESETB_CA);
1153 vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI0, 0x1, B0_DLL_ARPI0_RG_ARPI_RESETB_B0);
1154 vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI0, 0x1, B1_DLL_ARPI0_RG_ARPI_RESETB_B1);
1155 mcDELAY_US(1);
1156
1157
1158 vIO32WriteFldMulti_All(DDRPHY_PLL4, P_Fld(0x1, PLL4_RG_RPHYPLL_ADA_MCK8X_EN)
1159 | P_Fld(0x1, PLL4_RG_RPHYPLL_RESETB));
1160 mcDELAY_US(1);
1161
1162 #if (fcFOR_CHIP_ID == fcLafite)
1163 vIO32WriteFldMulti(DDRPHY_CA_DLL_ARPI3, P_Fld(0x1, CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA)
1164 | P_Fld(0x1, CA_DLL_ARPI3_RG_ARPI_FB_EN_CA)
1165 | P_Fld(0x1, CA_DLL_ARPI3_RG_ARPI_CS_EN)
1166 | P_Fld(0x1, CA_DLL_ARPI3_RG_ARPI_CLK_EN)
1167 | P_Fld(0x1, CA_DLL_ARPI3_RG_ARPI_CMD_EN));
1168 vIO32WriteFldMulti(DDRPHY_CA_DLL_ARPI3 + SHIFT_TO_CHB_ADDR, P_Fld(u1BRPI_MCTL_EN_CA, CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA)
1169 | P_Fld(0x1, CA_DLL_ARPI3_RG_ARPI_FB_EN_CA)
1170 | P_Fld(0x1, CA_DLL_ARPI3_RG_ARPI_CS_EN)
1171 | P_Fld(0x1, CA_DLL_ARPI3_RG_ARPI_CLK_EN)
1172 | P_Fld(0x1, CA_DLL_ARPI3_RG_ARPI_CMD_EN));
1173 #endif
1174 vIO32WriteFldMulti_All(DDRPHY_B0_DLL_ARPI3, P_Fld(0x1, B0_DLL_ARPI3_RG_ARPI_FB_EN_B0)
1175 | P_Fld(0x1, B0_DLL_ARPI3_RG_ARPI_DQS_EN_B0)
1176 | P_Fld(0x1, B0_DLL_ARPI3_RG_ARPI_DQM_EN_B0)
1177 | P_Fld(0x1, B0_DLL_ARPI3_RG_ARPI_DQ_EN_B0)
1178 | P_Fld(0x1, B0_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B0));
1179 vIO32WriteFldMulti_All(DDRPHY_B1_DLL_ARPI3, P_Fld(0x1, B1_DLL_ARPI3_RG_ARPI_FB_EN_B1)
1180 | P_Fld(0x1, B1_DLL_ARPI3_RG_ARPI_DQS_EN_B1)
1181 | P_Fld(0x1, B1_DLL_ARPI3_RG_ARPI_DQM_EN_B1)
1182 | P_Fld(0x1, B1_DLL_ARPI3_RG_ARPI_DQ_EN_B1)
1183 | P_Fld(0x1, B1_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B1));
1184
1185 vIO32WriteFldMulti_All(DDRPHY_CA_DLL_ARPI2, P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA)
1186 | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA)
1187 | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA)
1188 | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_FB_CA)
1189 | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_CS)
1190 | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_CLK)
1191 | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_CG_CMD)
1192 | P_Fld(0x0, CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA));
1193 vIO32WriteFldMulti_All(DDRPHY_B0_DLL_ARPI2, P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0)
1194 | P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0)
1195 | P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0)
1196 | P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_CG_FB_B0)
1197 | P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0)
1198 | P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_CG_DQM_B0)
1199 | P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_CG_DQ_B0)
1200 | P_Fld(0x0, B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0));
1201 vIO32WriteFldMulti_All(DDRPHY_B1_DLL_ARPI2, P_Fld(0x0, B1_DLL_ARPI2_RG_ARPI_CG_MCK_B1)
1202 | P_Fld(0x0, B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1)
1203 | P_Fld(0x0, B1_DLL_ARPI2_RG_ARPI_CG_MCTL_B1)
1204 | P_Fld(0x0, B1_DLL_ARPI2_RG_ARPI_CG_FB_B1)
1205 | P_Fld(0x0, B1_DLL_ARPI2_RG_ARPI_CG_DQS_B1)
1206 | P_Fld(0x0, B1_DLL_ARPI2_RG_ARPI_CG_DQM_B1)
1207 | P_Fld(0x0, B1_DLL_ARPI2_RG_ARPI_CG_DQ_B1)
1208 | P_Fld(0x0, B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1));
1209 #if (fcFOR_CHIP_ID == fcLafite)
1210 vIO32WriteFldAlign_All(DDRPHY_CA_DLL_ARPI2, 1, CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN);
1211 vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI2, 0, B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0);
1212 vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI2, 0, B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1);
1213 #endif
1214
1215 mcDELAY_US(2);
1216
1217 vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL0, 0x1, MISC_CG_CTRL0_CLK_MEM_SEL);
1218 mcDELAY_US(1);
1219
1220 #if ENABLE_APHY_DLL_IDLE_MODE_OPTION
1221 vIO32WriteFldAlign(DDRPHY_CA_DLL_ARPI5, 0x0, CA_DLL_ARPI5_RG_ARDLL_IDLE_EN_CA);
1222 vIO32WriteFldAlign(DDRPHY_CA_DLL_ARPI5 + SHIFT_TO_CHB_ADDR, 0x1, CA_DLL_ARPI5_RG_ARDLL_IDLE_EN_CA);
1223 vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI5, 0x1, B0_DLL_ARPI5_RG_ARDLL_IDLE_EN_B0);
1224 vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI5, 0x1, B1_DLL_ARPI5_RG_ARDLL_IDLE_EN_B1);
1225
1226 vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI5, 0x3, B0_DLL_ARPI5_RG_ARDLL_PD_ZONE_B0);
1227 vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI5, 0x3, B1_DLL_ARPI5_RG_ARDLL_PD_ZONE_B1);
1228 vIO32WriteFldAlign_All(DDRPHY_CA_DLL_ARPI5, 0x3, CA_DLL_ARPI5_RG_ARDLL_PD_ZONE_CA);
1229
1230 vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI5, 0xC, B0_DLL_ARPI5_RG_ARDLL_MON_SEL_B0);
1231 vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI5, 0xC, B1_DLL_ARPI5_RG_ARDLL_MON_SEL_B1);
1232 vIO32WriteFldAlign_All(DDRPHY_CA_DLL_ARPI5, 0xC, CA_DLL_ARPI5_RG_ARDLL_MON_SEL_CA);
1233 #endif
1234
1235
1236 vIO32WriteFldAlign(DDRPHY_CA_DLL_ARPI2, 0x1, CA_DLL_ARPI2_RG_ARDLL_PHDET_EN_CA);
1237 mcDELAY_US(1);
1238 vIO32WriteFldAlign_All(DDRPHY_CA_DLL_ARPI2, 0x1, CA_DLL_ARPI2_RG_ARDLL_PHDET_EN_CA);
1239 mcDELAY_US(1);
1240 vIO32WriteFldAlign_All(DDRPHY_B0_DLL_ARPI2, 0x1, B0_DLL_ARPI2_RG_ARDLL_PHDET_EN_B0);
1241 mcDELAY_US(1);
1242 vIO32WriteFldAlign_All(DDRPHY_B1_DLL_ARPI2, 0x1, B1_DLL_ARPI2_RG_ARDLL_PHDET_EN_B1);
1243 mcDELAY_US(1);
1244
1245 //if(p->vendor_id==VENDOR_SAMSUNG && p->dram_type==TYPE_LPDDR3)
1246 {
1247 #if 0
1248 mcSHOW_DBG_MSG(("DDRPhyPLLSetting-DMSUS\n\n"));
1249 vIO32WriteFldMulti_All(DDRPHY_MISC_SPM_CTRL1, P_Fld(0x0, MISC_SPM_CTRL1_RG_ARDMSUS_10) | P_Fld(0x0, MISC_SPM_CTRL1_RG_ARDMSUS_10_B0)
1250 | P_Fld(0x0, MISC_SPM_CTRL1_RG_ARDMSUS_10_B1) | P_Fld(0x0, MISC_SPM_CTRL1_RG_ARDMSUS_10_CA));
1251 vIO32WriteFldAlign_All(DDRPHY_MISC_SPM_CTRL0, 0xffffffff, MISC_SPM_CTRL0_PHY_SPM_CTL0);
1252 vIO32WriteFldAlign_All(DDRPHY_MISC_SPM_CTRL2, 0xffffffff, MISC_SPM_CTRL2_PHY_SPM_CTL2);
1253 #else
1254
1255 vIO32WriteFldAlign_All(DDRPHY_CA_CMD2, 0, CA_CMD2_RG_TX_ARCMD_OE_DIS);
1256 DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32));
1257 #endif
1258
1259 mcSHOW_DBG_MSG2(("DDRPhyPLLSetting-CKEON\n\n"));
1260
1261 CKEFixOnOff(p, TO_ALL_RANK, CKE_DYNAMIC, TO_ALL_CHANNEL);
1262 }
1263
1264 #if ENABLE_DFS_SSC_WA
1265 DDRSSCSetting(p);
1266 #endif
1267
1268 DDRPhyFreqMeter(p);
1269 #endif
1270 }
1271 #endif
1272 #if CBT_MOVE_CA_INSTEAD_OF_CLK
DramcCmdUIDelaySetting(DRAMC_CTX_T * p,U8 value)1273 void DramcCmdUIDelaySetting(DRAMC_CTX_T *p, U8 value)
1274 {
1275 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA7), P_Fld(value, SHU_SELPH_CA7_DLY_RA0) |
1276 P_Fld(value, SHU_SELPH_CA7_DLY_RA1) |
1277 P_Fld(value, SHU_SELPH_CA7_DLY_RA2) |
1278 P_Fld(value, SHU_SELPH_CA7_DLY_RA3) |
1279 P_Fld(value, SHU_SELPH_CA7_DLY_RA4) |
1280 P_Fld(value, SHU_SELPH_CA7_DLY_RA5) |
1281 P_Fld(value, SHU_SELPH_CA7_DLY_RA6));
1282
1283
1284 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA5), value, SHU_SELPH_CA5_DLY_CKE);
1285 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA6), value, SHU_SELPH_CA6_DLY_CKE1);
1286
1287
1288 // vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA5), P_Fld(0x1, SHU_SELPH_CA5_DLY_CS) | P_Fld(0x1, SHU_SELPH_CA5_DLY_CS1));
1289 }
1290 #endif
1291
cbt_dfs_mr13_global(DRAMC_CTX_T * p,U8 freq)1292 void cbt_dfs_mr13_global(DRAMC_CTX_T *p, U8 freq)
1293 {
1294 U8 u1RankIdx;
1295 U8 backup_rank;
1296
1297 backup_rank = u1GetRank(p);
1298
1299 for(u1RankIdx =0; u1RankIdx < p->support_rank_num; u1RankIdx++)
1300 {
1301 vSetRank(p, u1RankIdx);
1302
1303 if (freq == CBT_LOW_FREQ)
1304 {
1305 DramcMRWriteFldAlign(p, 13, 0, MR13_FSP_OP, JUST_TO_GLOBAL_VALUE);
1306 DramcMRWriteFldAlign(p, 13, 0, MR13_FSP_WR, JUST_TO_GLOBAL_VALUE);
1307 }
1308 else
1309 {
1310 DramcMRWriteFldAlign(p, 13, 1, MR13_FSP_OP, JUST_TO_GLOBAL_VALUE);
1311 DramcMRWriteFldAlign(p, 13, 1, MR13_FSP_WR, JUST_TO_GLOBAL_VALUE);
1312 }
1313 }
1314
1315 vSetRank(p, backup_rank);
1316 }
1317
cbt_switch_freq(DRAMC_CTX_T * p,U8 freq)1318 void cbt_switch_freq(DRAMC_CTX_T *p, U8 freq)
1319 {
1320 #if (FOR_DV_SIMULATION_USED == TRUE)
1321 return;
1322 #endif
1323
1324 U8 u1backup_TCKFIXON[CHANNEL_NUM], ch, ch_bak;
1325
1326 #if MR_CBT_SWITCH_FREQ
1327 #if (fcFOR_CHIP_ID == fc8195)
1328 static U8 _CurFreq = CBT_UNKNOWN_FREQ;
1329 if (_CurFreq == freq)
1330 {
1331 return;
1332 }
1333 _CurFreq = freq;
1334
1335
1336 ch_bak = p->channel;
1337 for (ch = CHANNEL_A; ch < p->support_channel_num; ch++) {
1338 vSetPHY2ChannelMapping(p, ch);
1339 u1backup_TCKFIXON[ch] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL),
1340 DRAMC_PD_CTRL_TCKFIXON);
1341 }
1342 vSetPHY2ChannelMapping(p, ch_bak);
1343 vIO32WriteFldAlign_All(DRAMC_REG_DRAMC_PD_CTRL, 0x0, DRAMC_PD_CTRL_TCKFIXON);
1344
1345 EnableDFSHwModeClk(p);
1346
1347 if (freq == CBT_LOW_FREQ)
1348 {
1349 #if REPLACE_DFS_RG_MODE
1350 DramcDFSDirectJump_SPMMode_forK(p, DRAM_DFS_REG_SHU1);
1351 //DramcDFSDirectJump_SPMMode(p, SRAM_SHU3);
1352
1353 #else
1354 DramcDFSDirectJump_RGMode(p, DRAM_DFS_REG_SHU1);
1355 #endif
1356 }
1357 else
1358 {
1359 #if REPLACE_DFS_RG_MODE
1360 DramcDFSDirectJump_SPMMode_forK(p, DRAM_DFS_REG_SHU0);
1361 //DramcDFSDirectJump_SPMMode(p, vGet_Current_SRAMIdx(p));
1362 #else
1363 DramcDFSDirectJump_RGMode(p, DRAM_DFS_REG_SHU0);
1364 #endif
1365 }
1366
1367 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CLK_CTRL, P_Fld(0, MISC_CLK_CTRL_DVFS_CLK_MEM_SEL)
1368 | P_Fld(0, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN));
1369
1370 for (ch = CHANNEL_A; ch < p->support_channel_num; ch++) {
1371 vSetPHY2ChannelMapping(p, ch);
1372 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), u1backup_TCKFIXON[ch],
1373 DRAMC_PD_CTRL_TCKFIXON);
1374 }
1375 vSetPHY2ChannelMapping(p, ch_bak);
1376
1377 DDRPhyFreqMeter(p);
1378 #else
1379 #error Need check of the DRAM_DFS_SHUFFLE_X for your chip !!!
1380 #endif
1381 #endif
1382 }
1383
1384
DramcPowerOnSequence(DRAMC_CTX_T * p)1385 void DramcPowerOnSequence(DRAMC_CTX_T *p)
1386 {
1387 #if ENABLE_TMRRI_NEW_MODE
1388 //U8 u1RankIdx;
1389 #endif
1390
1391 #ifdef DUMP_INIT_RG_LOG_TO_DE
1392
1393 CKEFixOnOff(p, TO_ALL_RANK, CKE_FIXON, TO_ALL_CHANNEL);
1394 return;
1395 #endif
1396
1397 #if APPLY_LP4_POWER_INIT_SEQUENCE
1398 //static U8 u1PowerOn=0;
1399 //if(u1PowerOn ==0)
1400 {
1401
1402 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 0x0, MISC_CTRL1_R_DMDA_RRESETB_I);
1403
1404 //vIO32WriteFldAlign(DRAMC_REG_RKCFG, 0, RKCFG_CKE2RANK_OPT2);
1405
1406
1407 CKEFixOnOff(p, TO_ALL_RANK, CKE_FIXOFF, TO_ALL_CHANNEL);
1408
1409
1410 mcDELAY_US(200);
1411
1412
1413 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 0x1, MISC_CTRL1_R_DMDA_RRESETB_I);
1414
1415
1416 DramCLKAlwaysOnOff(p, ON, TO_ALL_CHANNEL);
1417
1418
1419 mcDELAY_MS(2);
1420
1421
1422 CKEFixOnOff(p, TO_ALL_RANK, CKE_FIXON, TO_ALL_CHANNEL);
1423
1424
1425 mcDELAY_US(2);
1426 //u1PowerOn=1;
1427
1428
1429 DramCLKAlwaysOnOff(p, OFF, TO_ALL_CHANNEL);
1430 mcSHOW_DBG_MSG5(("APPLY_LP4_POWER_INIT_SEQUENCE\n"));
1431 }
1432 #endif
1433 }
1434
DramcModeRegInit_CATerm(DRAMC_CTX_T * p,U8 bWorkAround)1435 DRAM_STATUS_T DramcModeRegInit_CATerm(DRAMC_CTX_T *p, U8 bWorkAround)
1436 {
1437 static U8 CATermWA[CHANNEL_NUM] = {0};
1438 U8 u1ChannelIdx, u1RankIdx, u1RankIdxBak;
1439 U32 backup_broadcast;
1440 //U8 operating_fsp = p->dram_fsp;
1441 U8 u1MR11_Value;
1442 U8 u1MR22_Value;
1443
1444 u1ChannelIdx = vGetPHY2ChannelMapping(p);
1445
1446 if (CATermWA[u1ChannelIdx] == bWorkAround)
1447 return DRAM_OK;
1448
1449 CATermWA[u1ChannelIdx] = bWorkAround;
1450
1451 backup_broadcast = GetDramcBroadcast();
1452
1453 DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
1454
1455 u1RankIdxBak = u1GetRank(p);
1456
1457 for (u1RankIdx = 0; u1RankIdx < (U32)(p->support_rank_num); u1RankIdx++)
1458 {
1459 vSetRank(p, u1RankIdx);
1460
1461 mcSHOW_DBG_MSG2(("[DramcModeRegInit_CATerm] CH%u RK%u bWorkAround=%d\n", u1ChannelIdx, u1RankIdx, bWorkAround));
1462
1463 #if MRW_CHECK_ONLY
1464 mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__));
1465 #endif
1466 DramcMRWriteFldAlign(p, 13, 0, MR13_FSP_OP, TO_MR);
1467 DramcMRWriteFldAlign(p, 13, 1, MR13_FSP_WR, TO_MR);
1468
1469
1470
1471 if (p->dram_type == TYPE_LPDDR4P)
1472 {
1473 u1MR11_Value = 0x0;
1474 }
1475 else
1476 {
1477 #if ENABLE_SAMSUNG_NT_ODT
1478 if ((p->vendor_id == VENDOR_SAMSUNG) && (p->revision_id == 0x7))
1479 {
1480 u1MR11_Value = 0x2;
1481 u1MR11_Value |= (0x1 << 3);
1482 }
1483 else
1484 #endif
1485 u1MR11_Value = 0x3;
1486
1487 #if FSP1_CLKCA_TERM
1488 if (p->dram_cbt_mode[u1RankIdx] == CBT_NORMAL_MODE)
1489 {
1490 u1MR11_Value |= 0x40;
1491 }
1492 else
1493 {
1494 u1MR11_Value |= 0x20;
1495 }
1496 #endif
1497 }
1498 #if APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST
1499 if (gDramcDqOdtRZQAdjust >= 0)
1500 u1MR11_Value = gDramcDqOdtRZQAdjust;
1501 #endif
1502 u1MR11Value[p->dram_fsp] = u1MR11_Value;
1503 DramcModeRegWriteByRank(p, u1RankIdx, 11, u1MR11Value[p->dram_fsp]);
1504
1505 if (p->dram_type == TYPE_LPDDR4)
1506 {
1507 u1MR22_Value = 0x24;
1508 }
1509 else
1510 {
1511 u1MR22_Value = 0x3c;
1512 #if FSP1_CLKCA_TERM
1513 if (bWorkAround)
1514 {
1515 u1MR22_Value = 0x4;
1516 }
1517 else
1518 {
1519 if (u1RankIdx == RANK_0)
1520 {
1521 u1MR22_Value = 0x4;
1522 }
1523 else
1524 {
1525 u1MR22_Value = 0x2c;
1526 }
1527 }
1528 #endif
1529 }
1530 #if APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST
1531 if (gDramcMR22SoCODTAdjust[u1MRFsp] >= 0)
1532 {
1533 u1MR22_Value = (u1MR22_Value & ~(0x7)) | gDramcMR22SoCODTAdjust[u1MRFsp];
1534 }
1535 #endif
1536 u1MR22Value[p->dram_fsp] = u1MR22_Value;
1537 DramcModeRegWriteByRank(p, u1RankIdx, 22, u1MR22_Value);
1538 }
1539
1540 vSetRank(p, u1RankIdxBak);
1541 // vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MRS), RANK_0, MRS_MRSRK);
1542
1543 DramcBroadcastOnOff(backup_broadcast);
1544
1545 return DRAM_OK;
1546 }
1547
DramcModeRegInit_LP4(DRAMC_CTX_T * p)1548 DRAM_STATUS_T DramcModeRegInit_LP4(DRAMC_CTX_T *p)
1549 {
1550 U32 u4RankIdx;//, u4CKE0Bak, u4CKE1Bak, u4MIOCKBak, u4AutoRefreshBak;
1551 U8 u1MR2_RLWL;
1552 //U16 u2MR3Value;
1553 U8 u1MRFsp= FSP_0;
1554 U8 u1ChannelIdx; //support_channel_num
1555 U8 backup_channel, backup_rank;
1556 U8 operating_fsp = p->dram_fsp;
1557 U32 backup_broadcast;
1558 U8 u1MR11_Value;
1559 U8 u1MR22_Value;
1560 U8 u1nWR=0;
1561 U16 u2FreqMax = u2DFSGetHighestFreq(p);
1562 U8 u1set_mrsrk=0;
1563
1564 backup_broadcast = GetDramcBroadcast();
1565
1566 DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
1567
1568
1569 DramcPowerOnSequence(p);
1570
1571 backup_channel = p->channel;
1572 backup_rank = p->rank;
1573
1574
1575 #if VENDER_JV_LOG
1576 vPrintCalibrationBasicInfo_ForJV(p);
1577 #endif
1578
1579
1580 {
1581
1582 u1MR01Value[FSP_0] &= 0x8F;
1583 u1MR01Value[FSP_1] &= 0x8F;
1584 if (u2FreqMax == 2133)
1585 {
1586
1587 u1MR01Value[FSP_0] |= (0x7 << 4);
1588 u1MR01Value[FSP_1] |= (0x7 << 4);
1589 u1nWR = 40;
1590 }
1591 else if (u2FreqMax == 1866)
1592 {
1593
1594 u1MR01Value[FSP_0] |= (0x6 << 4);
1595 u1MR01Value[FSP_1] |= (0x6 << 4);
1596 u1nWR = 34;
1597 }
1598 else
1599 {
1600
1601 u1MR01Value[FSP_0] |= (0x5 << 4);
1602 u1MR01Value[FSP_1] |= (0x5 << 4);
1603 u1nWR = 30;
1604 }
1605
1606 mcSHOW_DBG_MSG2(("nWR fixed to %d\n", u1nWR));
1607 //mcDUMP_REG_MSG(("nWR fixed to %d\n", u1nWR));
1608 }
1609
1610 #ifndef DUMP_INIT_RG_LOG_TO_DE
1611 if(p->dram_fsp == FSP_1)
1612 {
1613
1614 CmdOEOnOff(p, DISABLE, CMDOE_DIS_TO_ALL_CHANNEL);
1615 cbt_switch_freq(p, CBT_LOW_FREQ);
1616 CmdOEOnOff(p, ENABLE, CMDOE_DIS_TO_ALL_CHANNEL);
1617 }
1618 #endif
1619
1620 for(u1ChannelIdx=0; u1ChannelIdx<(p->support_channel_num); u1ChannelIdx++)
1621 {
1622 vSetPHY2ChannelMapping(p, u1ChannelIdx);
1623
1624 for(u4RankIdx =0; u4RankIdx < (U32)(p->support_rank_num); u4RankIdx++)
1625 {
1626 vSetRank(p, u4RankIdx);
1627
1628 mcSHOW_DBG_MSG2(("[ModeRegInit_LP4] CH%u RK%u\n", u1ChannelIdx, u4RankIdx));
1629 //mcDUMP_REG_MSG(("[ModeRegInit_LP4] CH%u RK%u\n", u1ChannelIdx, u4RankIdx));
1630 #if VENDER_JV_LOG
1631 mcSHOW_JV_LOG_MSG(("\n[ModeRegInit_LP4] CH%u RK%d\n", u1ChannelIdx, u4RankIdx));
1632 #endif
1633 #if MRW_CHECK_ONLY
1634 mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__));
1635 #endif
1636
1637 //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MRS), u4RankIdx, MRS_MRSRK);
1638
1639
1640 if(p->dram_type == TYPE_LPDDR4P)
1641 {
1642
1643 #ifndef MT6779_FPGA
1644 #if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0)
1645 #if __Petrus_TO_BE_PORTING__
1646 dramc_set_vddq_voltage(p->dram_type, 600000);
1647 #endif
1648 #endif
1649 #endif
1650
1651 DramcModeRegWriteByRank(p, u4RankIdx, 37, 0x1);
1652
1653
1654 #ifndef MT6779_FPGA
1655 #if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0)
1656 #if __Petrus_TO_BE_PORTING__
1657 dramc_set_vddq_voltage(p->dram_type, 400000);
1658 #endif
1659 #endif
1660 #endif
1661 }
1662
1663
1664 // if(p->frequency<=1200)
1665 {
1666
1667 u1MRFsp = FSP_0;
1668 mcSHOW_DBG_MSG2(("\tFsp%d\n", u1MRFsp));
1669 #if VENDER_JV_LOG
1670 mcSHOW_JV_LOG_MSG(("\tFsp%d\n", u1MRFsp));
1671 #endif
1672
1673 u1MR13Value[u4RankIdx] = 0;
1674 MRWriteFldMulti(p, 13, P_Fld(1, MR13_PRO) |
1675 P_Fld(1, MR13_VRCG),
1676 TO_MR);
1677
1678
1679 DramcModeRegWriteByRank(p, u4RankIdx, 12, u1MR12Value[u1ChannelIdx][u4RankIdx][u1MRFsp]);
1680 DramcModeRegWriteByRank(p, u4RankIdx, 1, u1MR01Value[u1MRFsp]);
1681
1682
1683 u1MR2_RLWL = LP4_DRAM_INIT_RLWL_MRfield_config(p->frequency << 1);
1684 u1MR02Value[p->dram_fsp] = u1MR2_RLWL | (u1MR2_RLWL << 3);
1685
1686 #if 0
1687 if (p->freqGroup <= 400)
1688 {
1689 u1MR02Value[u1MRFsp] = 0x12;
1690 }
1691 else if ((p->freqGroup == 800) || (p->freqGroup == 600))
1692 {
1693 u1MR02Value[u1MRFsp] = 0x12;
1694 }
1695 else if (p->freqGroup == 933)
1696 {
1697 u1MR02Value[u1MRFsp] = 0x1b;
1698 }
1699 else if (p->freqGroup == 1200)
1700 {
1701 u1MR02Value[u1MRFsp] = 0x24;
1702 }
1703 #endif
1704 DramcModeRegWriteByRank(p, u4RankIdx, 2, u1MR02Value[u1MRFsp]);
1705
1706 u1MR11Value[u1MRFsp] = 0x0;
1707 DramcModeRegWriteByRank(p, u4RankIdx, 11, u1MR11Value[u1MRFsp]);
1708
1709 #if ENABLE_LP4Y_DFS
1710
1711 if (p->freqGroup <= 800)
1712 {
1713 u1MR21Value[u1MRFsp] |= (0x1 << 5);
1714 #if LP4Y_BACKUP_SOLUTION
1715 u1MR51Value[u1MRFsp] |= (0x3 << 1);
1716 #endif
1717 }
1718 else if ((p->freqGroup == 1200) || (p->freqGroup == 933))
1719 #endif
1720 {
1721 u1MR21Value[u1MRFsp] = 0;
1722 u1MR51Value[u1MRFsp] = 0;
1723 }
1724 DramcModeRegWriteByRank(p, u4RankIdx, 21, u1MR21Value[u1MRFsp]);
1725 DramcModeRegWriteByRank(p, u4RankIdx, 51, u1MR51Value[u1MRFsp]);
1726
1727 if(p->dram_type == TYPE_LPDDR4)
1728 {
1729 u1MR22_Value = 0x20;
1730 }
1731 else
1732 {
1733 u1MR22_Value = 0x38;
1734 }
1735 #if APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST
1736 if (gDramcMR22SoCODTAdjust[u1MRFsp]>=0)
1737 {
1738 u1MR22_Value = (u1MR22_Value&~(0x7))|gDramcMR22SoCODTAdjust[u1MRFsp];
1739 }
1740 #endif
1741 u1MR22Value[u1MRFsp] = u1MR22_Value;
1742 DramcModeRegWriteByRank(p, u4RankIdx, 22, u1MR22Value[u1MRFsp]);
1743
1744
1745 DramcModeRegWriteByRank(p, u4RankIdx, 14, u1MR14Value[u1ChannelIdx][u4RankIdx][u1MRFsp]);
1746
1747 #if CALIBRATION_SPEED_UP_DEBUG
1748 mcSHOW_DBG_MSG2(("CBT Vref Init: CH%d Rank%d FSP%d, Range %d Vref %d\n\n",p->channel, p->rank, u1MRFsp, u1MR12Value[u1ChannelIdx][u4RankIdx][u1MRFsp]>>6, (u1MR12Value[u1ChannelIdx][u4RankIdx][u1MRFsp] & 0x3f)));
1749 mcSHOW_DBG_MSG2(("TX Vref Init: CH%d Rank%d FSP%d, TX Range %d Vref %d\n\n",p->channel, p->rank, u1MRFsp,u1MR14Value[u1ChannelIdx][u4RankIdx][u1MRFsp]>>6, (u1MR14Value[u1ChannelIdx][u4RankIdx][u1MRFsp] & 0x3f)));
1750 #endif
1751
1752
1753 u1MR03Value[u1MRFsp] = (u1MR03Value[u1MRFsp]&0x3F);
1754
1755 if(p->dram_type == TYPE_LPDDR4X || p->dram_type == TYPE_LPDDR4P)
1756 {
1757 u1MR03Value[u1MRFsp] &= 0xfe;
1758 }
1759 #if APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST
1760 if (gDramcMR03PDDSAdjust[u1MRFsp]>=0)
1761 {
1762 u1MR03Value[u1MRFsp] = (u1MR03Value[u1MRFsp]&~(0x7<<3))|(gDramcMR03PDDSAdjust[u1MRFsp]<<3);
1763 }
1764 #endif
1765
1766 DramcModeRegWriteByRank(p, u4RankIdx, 3, u1MR03Value[u1MRFsp]);
1767 DramcModeRegWriteByRank(p, u4RankIdx, 4, u1MR04Value[u4RankIdx]);
1768 DramcModeRegWriteByRank(p, u4RankIdx, 3, u1MR03Value[u1MRFsp]);
1769 }
1770 //else
1771 {
1772
1773 u1MRFsp = FSP_1;
1774 mcSHOW_DBG_MSG2(("\tFsp%d\n", u1MRFsp));
1775 #if VENDER_JV_LOG
1776 mcSHOW_JV_LOG_MSG(("\tFsp%d\n", u1MRFsp));
1777 #endif
1778
1779 DramcMRWriteFldAlign(p, 13, 1, MR13_FSP_WR, TO_MR);
1780
1781
1782 #if CBT_FSP1_MATCH_FSP0_UNTERM_WA
1783 if (p->dram_fsp == FSP_0)
1784 DramcModeRegWriteByRank(p, u4RankIdx, 12, u1MR12Value[u1ChannelIdx][u4RankIdx][FSP_0]);
1785 else
1786 #endif
1787 DramcModeRegWriteByRank(p, u4RankIdx, 12, u1MR12Value[u1ChannelIdx][u4RankIdx][u1MRFsp]);
1788 DramcModeRegWriteByRank(p, u4RankIdx, 1, u1MR01Value[u1MRFsp]);
1789 #if 0
1790
1791 if (p->freqGroup == 2133)
1792 {
1793 u1MR02Value[u1MRFsp] = 0x3f;
1794 }
1795 else if (p->freqGroup == 1866)
1796 {
1797 u1MR02Value[u1MRFsp] = 0x36;
1798 }
1799 else if (p->freqGroup == 1600)
1800 {
1801 u1MR02Value[u1MRFsp] = 0x2d;
1802 }
1803 else if (p->freqGroup == 1333)
1804 {
1805 u1MR02Value[u1MRFsp] = 0x24;
1806 }
1807 #endif
1808 DramcModeRegWriteByRank(p, u4RankIdx, 2, u1MR02Value[u1MRFsp]);
1809
1810 if(p->dram_type == TYPE_LPDDR4P)
1811 u1MR11_Value = 0x0;
1812 else
1813 {
1814 #if ENABLE_SAMSUNG_NT_ODT
1815 if ((p->vendor_id == VENDOR_SAMSUNG) && (p->revision_id == 0x7))
1816 {
1817 u1MR11_Value = 0x2;
1818 u1MR11_Value |= (0x1 << 3);
1819 }
1820 else
1821 #endif
1822 u1MR11_Value = 0x3;
1823
1824 #if FSP1_CLKCA_TERM
1825 #if CBT_FSP1_MATCH_FSP0_UNTERM_WA
1826 if (p->dram_fsp == FSP_1)
1827 #endif
1828 {
1829 if(p->dram_cbt_mode[u4RankIdx]==CBT_NORMAL_MODE)
1830 {
1831 u1MR11_Value |= 0x40;
1832 }
1833 else
1834 {
1835 u1MR11_Value |= 0x20;
1836 }
1837 }
1838 #endif
1839 }
1840 #if APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST
1841 if (gDramcDqOdtRZQAdjust>=0)
1842 {
1843 u1MR11_Value &= ~(0x7);
1844 u1MR11_Value = gDramcDqOdtRZQAdjust;
1845 }
1846 #endif
1847 u1MR11Value[u1MRFsp] = u1MR11_Value;
1848 DramcModeRegWriteByRank(p, u4RankIdx, 11, u1MR11Value[u1MRFsp]);
1849
1850 u1MR21Value[u1MRFsp] = 0;
1851 u1MR51Value[u1MRFsp] = 0;
1852 DramcModeRegWriteByRank(p, u4RankIdx, 21, u1MR21Value[u1MRFsp]);
1853 DramcModeRegWriteByRank(p, u4RankIdx, 51, u1MR51Value[u1MRFsp]);
1854
1855 if(p->dram_type == TYPE_LPDDR4)
1856 {
1857 u1MR22_Value = 0x24;
1858 }
1859 else
1860 {
1861 u1MR22_Value = 0x3c;
1862 #if FSP1_CLKCA_TERM
1863 #if CBT_FSP1_MATCH_FSP0_UNTERM_WA
1864 if (p->dram_fsp == FSP_1)
1865 #endif
1866 {
1867 if(u4RankIdx==RANK_0)
1868 {
1869 u1MR22_Value = 0x4;
1870 }
1871 else
1872 {
1873 u1MR22_Value = 0x2c;
1874 }
1875 }
1876 #endif
1877 }
1878 #if APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST
1879 if (gDramcMR22SoCODTAdjust[u1MRFsp]>=0)
1880 {
1881 u1MR22_Value = (u1MR22_Value&~(0x7))|gDramcMR22SoCODTAdjust[u1MRFsp];
1882 }
1883 #endif
1884 u1MR22Value[u1MRFsp] = u1MR22_Value;
1885 DramcModeRegWriteByRank(p, u4RankIdx, 22, u1MR22Value[u1MRFsp]);
1886
1887
1888 DramcModeRegWriteByRank(p, u4RankIdx, 14, u1MR14Value[u1ChannelIdx][u4RankIdx][u1MRFsp]);
1889
1890 #if CALIBRATION_SPEED_UP_DEBUG
1891 mcSHOW_DBG_MSG2(("CBT Vref Init: CH%d Rank%d FSP%d, Range %d Vref %d\n\n",p->channel, p->rank, u1MRFsp, u1MR12Value[u1ChannelIdx][u4RankIdx][u1MRFsp]>>6, (u1MR12Value[u1ChannelIdx][u4RankIdx][u1MRFsp] & 0x3f)));
1892 mcSHOW_DBG_MSG2(("TX Vref Init: CH%d Rank%d FSP%d, TX Range %d Vref %d\n\n",p->channel, p->rank, u1MRFsp, u1MR14Value[u1ChannelIdx][u4RankIdx][u1MRFsp]>>6, (u1MR14Value[u1ChannelIdx][u4RankIdx][u1MRFsp] & 0x3f)));
1893 #endif
1894
1895
1896 u1MR03Value[u1MRFsp] = (u1MR03Value[u1MRFsp]&0x3F);
1897
1898 if(p->dram_type == TYPE_LPDDR4X || p->dram_type == TYPE_LPDDR4P)
1899 {
1900 u1MR03Value[u1MRFsp] &= 0xfe;
1901 }
1902 #if APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST
1903 if (gDramcMR03PDDSAdjust[u1MRFsp]>=0)
1904 {
1905 u1MR03Value[u1MRFsp] = (u1MR03Value[u1MRFsp]&~(0x7<<3))|(gDramcMR03PDDSAdjust[u1MRFsp]<<3);
1906 }
1907 #endif
1908
1909 DramcModeRegWriteByRank(p, u4RankIdx, 3, u1MR03Value[u1MRFsp]);
1910 DramcModeRegWriteByRank(p, u4RankIdx, 4, u1MR04Value[u4RankIdx]);
1911 DramcModeRegWriteByRank(p, u4RankIdx, 3, u1MR03Value[u1MRFsp]);
1912 }
1913
1914 #if ENABLE_LP4_ZQ_CAL
1915 DramcZQCalibration(p, u4RankIdx);
1916 #endif
1917
1918
1919 //if (p->frequency < MRFSP_TERM_FREQ)
1920 if(operating_fsp == FSP_0)
1921 {
1922 DramcMRWriteFldAlign(p, 13, 0, MR13_FSP_OP, JUST_TO_GLOBAL_VALUE);
1923 DramcMRWriteFldAlign(p, 13, 0, MR13_FSP_WR, JUST_TO_GLOBAL_VALUE);
1924 }
1925 else
1926 {
1927 DramcMRWriteFldAlign(p, 13, 1, MR13_FSP_OP, JUST_TO_GLOBAL_VALUE);
1928 DramcMRWriteFldAlign(p, 13, 1, MR13_FSP_WR, JUST_TO_GLOBAL_VALUE);
1929 }
1930 }
1931 vSetRank(p, backup_rank);
1932
1933 #if 0
1934 for(u4RankIdx =0; u4RankIdx < (U32)(p->support_rank_num); u4RankIdx++)
1935 {
1936 DramcModeRegWriteByRank(p, u4RankIdx, 13, u1MR13Value[RANK_0]);
1937 }
1938 #else
1939
1940
1941 if (p->support_rank_num == RANK_DUAL)
1942 u1set_mrsrk = 0x3;
1943 else
1944 u1set_mrsrk = RANK_0;
1945 DramcModeRegWriteByRank(p, u1set_mrsrk, 13, u1MR13Value[RANK_0]);
1946 #endif
1947
1948
1949 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR13), P_Fld(u1MR13Value[RANK_0] | (0x1 << 3), SHU_HWSET_MR13_HWSET_MR13_OP)
1950 | P_Fld(13, SHU_HWSET_MR13_HWSET_MR13_MRSMA));
1951
1952 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_VRCG), P_Fld(u1MR13Value[RANK_0] | (0x1 << 3), SHU_HWSET_VRCG_HWSET_VRCG_OP)
1953 | P_Fld(13, SHU_HWSET_VRCG_HWSET_VRCG_MRSMA));
1954
1955 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR2), P_Fld(u1MR02Value[operating_fsp], SHU_HWSET_MR2_HWSET_MR2_OP)
1956 | P_Fld(2, SHU_HWSET_MR2_HWSET_MR2_MRSMA));
1957 }
1958
1959 #ifndef DUMP_INIT_RG_LOG_TO_DE
1960
1961 if(p->dram_fsp == FSP_1)
1962 {
1963
1964 CmdOEOnOff(p, DISABLE, CMDOE_DIS_TO_ALL_CHANNEL);
1965 cbt_switch_freq(p, CBT_HIGH_FREQ);
1966 CmdOEOnOff(p, ENABLE, CMDOE_DIS_TO_ALL_CHANNEL);
1967 }
1968 #endif
1969 vSetPHY2ChannelMapping(p, backup_channel);
1970
1971 #if ENABLE_DFS_RUNTIME_MRW
1972 DFSRuntimeMRW_preset_BeforeK(p, vGet_Current_SRAMIdx(p));
1973 #endif
1974
1975 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), RANK_0, SWCMD_CTRL0_MRSRK);
1976
1977 DramcBroadcastOnOff(backup_broadcast);
1978
1979 #if SAMSUNG_TEST_MODE_MRS_FOR_PRELOADER
1980 vApplyProgramSequence(p);
1981 #endif
1982
1983 return DRAM_OK;
1984 }
1985
1986
MPLLInit(void)1987 void MPLLInit(void)
1988 {
1989 #if (FOR_DV_SIMULATION_USED==0)
1990 #if 0//__A60868_TO_BE_PORTING__
1991
1992 #if (FOR_DV_SIMULATION_USED == 0)
1993 unsigned int tmp;
1994
1995 DRV_WriteReg32(AP_PLL_CON0, 0x11);
1996 mcDELAY_US(100);
1997 DRV_WriteReg32(AP_PLL_CON0, 0x13);
1998 mcDELAY_MS(1);
1999 DRV_WriteReg32(MPLL_PWR_CON0, 0x3);
2000 mcDELAY_US(30);
2001 DRV_WriteReg32(MPLL_PWR_CON0, 0x1);
2002 mcDELAY_US(1);
2003 tmp = DRV_Reg32(MPLL_CON1);
2004 DRV_WriteReg32(MPLL_CON1, tmp | 0x80000000);
2005 DRV_WriteReg32(MPLL_CON0, 0x181);
2006 mcDELAY_US(20);
2007 #endif
2008 #else
2009 unsigned int tmp;
2010
2011 tmp = DRV_Reg32(MPLL_CON4);
2012 DRV_WriteReg32(MPLL_CON4, tmp | 0x1);
2013
2014
2015 tmp = DRV_Reg32(MPLL_CON4);
2016 DRV_WriteReg32(MPLL_CON4, tmp & 0xfffffffd);
2017
2018
2019 tmp = DRV_Reg32(MPLL_CON0);
2020 DRV_WriteReg32(MPLL_CON0, tmp & 0xffffefff);
2021
2022
2023 tmp = DRV_Reg32(MPLL_CON2);
2024 DRV_WriteReg32(MPLL_CON2, 0x84200000);
2025
2026
2027 tmp = DRV_Reg32(MPLL_CON0);
2028 DRV_WriteReg32(MPLL_CON0, tmp | 0x200);
2029
2030 #endif
2031 #endif
2032 }
2033
2034
2035 #if ENABLE_RODT_TRACKING_SAVE_MCK
SetTxWDQSStatusOnOff(U8 u1OnOff)2036 static void SetTxWDQSStatusOnOff(U8 u1OnOff)
2037 {
2038 u1WDQS_ON = u1OnOff;
2039 }
2040 #endif
2041
2042
2043 #if XRTRTR_NEW_CROSS_RK_MODE
XRTRTR_SHU_Setting(DRAMC_CTX_T * p)2044 void XRTRTR_SHU_Setting(DRAMC_CTX_T * p)
2045 {
2046 U8 u1RkSelUIMinus = 0, u1RkSelMCKMinus = 0;
2047 //U8 u1RankIdx = 0;
2048 //U8 u1Rank_backup = u1GetRank(p);
2049
2050 if (vGet_DDR_Loop_Mode(p) == SEMI_OPEN_LOOP_MODE)
2051 u1RkSelMCKMinus = 1;
2052 else if (p->frequency >= 1600)
2053 u1RkSelUIMinus = 2;
2054
2055
2056 /*vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ6, u1ShuRkMode, SHU_B0_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B0);
2057 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ6, u1ShuRkMode, SHU_B1_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B1);*/
2058
2059
2060 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, P_Fld(u1RkSelMCKMinus, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS)
2061 | P_Fld(u1RkSelUIMinus, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS)
2062 | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS)
2063 | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS)
2064 | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN)
2065 | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK)
2066 | P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK)
2067 | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE)
2068 | P_Fld(0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23)
2069 | P_Fld(0x1, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN));
2070 //Darren-vIO32WriteFldAlign_All(DRAMC_REG_SHU_STBCAL, 0x1, SHU_STBCAL_DQSIEN_RX_SELPH_OPT);
2071
2072 /*for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
2073 {
2074 vSetRank(p, u1RankIdx);
2075 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_RK_DQSCAL, P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENHLMTEN)
2076 | P_Fld(0x3f, MISC_SHU_RK_DQSCAL_DQSIENHLMT)
2077 | P_Fld(0x1, MISC_SHU_RK_DQSCAL_DQSIENLLMTEN)
2078 | P_Fld(0x60, MISC_SHU_RK_DQSCAL_DQSIENLLMT));
2079 }
2080 vSetRank(p, u1Rank_backup);*/
2081 }
2082
2083 #if 0
2084 static void ENABLE_XRTRTR_Setting(DRAMC_CTX_T * p)
2085 {
2086 #if 0
2087 U8 u1ByteIdx = 0;
2088 U32 u4ByteOffset = 0;
2089
2090
2091 for(u1ByteIdx=0; u1ByteIdx<DQS_NUMBER_LP4; u1ByteIdx++)
2092 {
2093 u4ByteOffset = u1ByteIdx*DDRPHY_AO_B0_B1_OFFSET;
2094
2095 vIO32WriteFldAlign_All(DDRPHY_REG_B0_DLL_ARPI1 + u4ByteOffset, 0x1, B0_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B0);
2096 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DLL_ARPI3 + u4ByteOffset, 0x1, SHU_B0_DLL_ARPI3_RG_ARPI_MCTL_EN_B0);
2097
2098 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ2 + u4ByteOffset, P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_PD_MCTL_SEL_B0)
2099 | P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0)
2100 | P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B0));
2101 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ10 + u4ByteOffset, P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B0)
2102 | P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B0));
2103 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ11 + u4ByteOffset, P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0)
2104 | P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0));
2105 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ13 + u4ByteOffset, 0x1, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0);
2106 }
2107
2108
2109 vIO32WriteFldMulti_All(DDRPHY_REG_B0_DQ9, P_Fld(0x0, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0x1, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0));
2110 vIO32WriteFldMulti_All(DDRPHY_REG_B1_DQ9, P_Fld(0x0, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0x1, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1));
2111 //vIO32WriteFldMulti_All(DDRPHY_REG_CA_CMD9, P_Fld(0, CA_CMD9_R_IN_GATE_EN_LOW_OPT_CA) | P_Fld(0, CA_CMD9_R_DMRXDVS_R_F_DLY_RK_OPT));
2112
2113
2114 vIO32WriteFldAlign_All(DDRPHY_REG_B0_DQ10, 0x1, B0_DQ10_ARPI_CG_RK1_SRC_SEL_B0);
2115 vIO32WriteFldAlign_All(DDRPHY_REG_B1_DQ10, 0x1, B1_DQ10_ARPI_CG_RK1_SRC_SEL_B1);
2116
2117
2118 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_STBCAL2, P_Fld(0x1, MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN)
2119 | P_Fld(0x1, MISC_STBCAL2_STB_RST_BY_RANK)
2120 | P_Fld(0x1, MISC_STBCAL2_STB_IG_XRANK_CG_RST));
2121
2122
2123 vIO32WriteFldAlign_All(DDRPHY_REG_B0_DQ9, 0x2, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0);
2124 vIO32WriteFldAlign_All(DDRPHY_REG_B1_DQ9, 0x2, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1);
2125 vIO32WriteFldAlign_All(DDRPHY_REG_B0_DQ9, 0x1, B0_DQ9_R_DMDQSIEN_VALID_LAT_B0);
2126 vIO32WriteFldAlign_All(DDRPHY_REG_B1_DQ9, 0x1, B1_DQ9_R_DMDQSIEN_VALID_LAT_B1);
2127 #endif
2128 }
2129 #endif
2130 #endif
2131
2132 #if XRTWTW_NEW_CROSS_RK_MODE
XRTWTW_SHU_Setting(DRAMC_CTX_T * p)2133 void XRTWTW_SHU_Setting(DRAMC_CTX_T * p)
2134 {
2135 U8 u1RankIdx, u1ByteIdx;
2136 U8 u1Rank_bak = u1GetRank(p);
2137 U16 u2TxDly_OEN_RK[2][2] = {0}, u2TxPI_UPD[2] = {0}, u2TxRankINCTL, u2TxDly_OEN_RK_max, u2TxPI_UPD_max;
2138
2139 for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
2140 {
2141 vSetRank(p, u1RankIdx);
2142
2143 u2TxDly_OEN_RK[u1RankIdx][0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_OEN_DQ0);
2144 u2TxDly_OEN_RK[u1RankIdx][1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_OEN_DQ1);
2145 }
2146 vSetRank(p, u1Rank_bak);
2147
2148 for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++)
2149 {
2150 u2TxDly_OEN_RK_max = (u2TxDly_OEN_RK[0][u1ByteIdx] > u2TxDly_OEN_RK[1][u1ByteIdx])? u2TxDly_OEN_RK[0][u1ByteIdx]: u2TxDly_OEN_RK[1][u1ByteIdx];
2151 if (p->frequency >= 1200)
2152 u2TxPI_UPD[u1ByteIdx] = (u2TxDly_OEN_RK_max > 2)? (u2TxDly_OEN_RK_max - 2): 0;
2153 else
2154 u2TxPI_UPD[u1ByteIdx] = (u2TxDly_OEN_RK_max > 1)? (u2TxDly_OEN_RK_max - 1): 0;
2155 }
2156
2157 u2TxPI_UPD_max = (u2TxPI_UPD[0] > u2TxPI_UPD[1])? u2TxPI_UPD[0]: u2TxPI_UPD[1];
2158 u2TxRankINCTL = (u2TxPI_UPD_max > 1)? (u2TxPI_UPD_max - 1): 0;
2159
2160 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_NEW_XRW2W_CTRL), P_Fld(0x0, SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE)
2161 | P_Fld(u2TxPI_UPD[0], SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0)
2162 | P_Fld(u2TxPI_UPD[1], SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1));
2163
2164 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_RANKCTL), P_Fld(0x0, SHU_TX_RANKCTL_TXRANKINCTL_ROOT)
2165 | P_Fld(u2TxRankINCTL, SHU_TX_RANKCTL_TXRANKINCTL)
2166 | P_Fld(u2TxRankINCTL, SHU_TX_RANKCTL_TXRANKINCTL_TXDLY));
2167 }
2168 #if 0
2169 static void ENABLE_XRTWTW_Setting(DRAMC_CTX_T * p)
2170 {
2171 #if 0
2172
2173 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ2, P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B0)
2174 | P_Fld(0x1, SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0));
2175 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ13, 0x1, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0);
2176
2177
2178 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ2, P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B1)
2179 | P_Fld(0x1, SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1));
2180 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ13, 0x1, SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1);
2181
2182
2183 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD2, P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_OFFSET_ASYNC_EN_CA)
2184 | P_Fld(0x0, SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA));
2185 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD13, 0x1, SHU_CA_CMD13_RG_TX_ARCA_DLY_LAT_EN_CA);
2186 #endif
2187 }
2188 #endif
2189 #endif
2190
2191 #if CMD_CKE_WORKAROUND_FIX
CMD_CKE_Modified_txp_Setting(DRAMC_CTX_T * p)2192 static void CMD_CKE_Modified_txp_Setting(DRAMC_CTX_T * p)
2193 {
2194 #if __A60868_TO_BE_PORTING__
2195
2196 U8 u1CmdTxPipe = 0, u1CkTxPipe = 0, u1SrefPdSel = 0;
2197
2198 if (vGet_Div_Mode(p) == DIV4_MODE)
2199 {
2200 u1CkTxPipe = 1;
2201 u1SrefPdSel = 1;
2202 }
2203 else if (p->frequency >= 1866)
2204 {
2205 u1CmdTxPipe = 1;
2206 u1CkTxPipe = 1;
2207 }
2208
2209 vIO32WriteFldAlign(DDRPHY_SHU_MISC0, u1CkTxPipe, SHU_MISC0_RG_CK_TXPIPE_BYPASS_EN);
2210 vIO32WriteFldAlign(DDRPHY_SHU_MISC0, u1CmdTxPipe, SHU_MISC0_RG_CMD_TXPIPE_BYPASS_EN);
2211 //vIO32WriteFldAlign(DRAMC_REG_SHU_CONF0, u1SrefPdSel, SHU_CONF0_SREF_PD_SEL);
2212 #endif //__A60868_TO_BE_PORTING__
2213 }
2214 #endif
2215
2216 #if TX_OE_EXTEND
UpdateTxOEN(DRAMC_CTX_T * p)2217 static void UpdateTxOEN(DRAMC_CTX_T *p)
2218 {
2219 U8 u1ByteIdx, backup_rank, ii;
2220 U8 u1DQ_OE_CNT;
2221
2222
2223
2224 u1DQ_OE_CNT = 3;
2225
2226 vIO32WriteFldMulti(DRAMC_REG_SHU_TX_SET0, P_Fld(1, SHU_TX_SET0_DQOE_OPT) | P_Fld(u1DQ_OE_CNT, SHU_TX_SET0_DQOE_CNT));
2227
2228 backup_rank = u1GetRank(p);
2229
2230 LP4_ShiftDQS_OENUI(p, -1, ALL_BYTES);
2231 ShiftDQ_OENUI_AllRK(p, -1, ALL_BYTES);
2232
2233 }
2234 #endif
2235 #if 0
2236 static DRAM_STATUS_T UpdateInitialSettings_LP4(DRAMC_CTX_T *p)
2237 {
2238 #if __A60868_TO_BE_PORTING__
2239
2240 U16 u2RXVrefDefault = 0x8;
2241 U16 u1ChannelIdx, u1RankIdx, u1ByteIdx;
2242 U16 u2Clk_Dyn_Gating_Sel = 0x4, u2CG_CK_SEL = 0xb;
2243 #if CBT_MOVE_CA_INSTEAD_OF_CLK
2244 U8 u1CaPI = 0, u1CaUI = 0;
2245 U8 u1RankIdxBak;
2246 #endif
2247
2248 if (p->odt_onoff == ODT_ON)
2249 {
2250 vIO32WriteFldAlign(DRAMC_REG_SHU_ODTCTRL, 1, SHU_ODTCTRL_ROEN);
2251 vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ7, 0x1, SHU_B0_DQ7_R_DMRODTEN_B0);
2252 vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ7, 0x1, SHU_B1_DQ7_R_DMRODTEN_B1);
2253 vIO32WriteFldMulti(DDRPHY_SHU_CA_CMD0, P_Fld(0x0, SHU_CA_CMD0_RG_TX_ARCMD_PRE_EN)
2254 | P_Fld(0x1, SHU_CA_CMD0_RG_TX_ARCLK_PRE_EN));
2255 }
2256 else
2257 {
2258 vIO32WriteFldAlign(DRAMC_REG_SHU_ODTCTRL, 0, SHU_ODTCTRL_ROEN);
2259 vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ7, 0x0, SHU_B0_DQ7_R_DMRODTEN_B0);
2260 vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ7, 0x0, SHU_B1_DQ7_R_DMRODTEN_B1);
2261 vIO32WriteFldMulti(DDRPHY_SHU_CA_CMD0, P_Fld(0x0, SHU_CA_CMD0_RG_TX_ARCMD_PRE_EN)
2262 | P_Fld(0x0, SHU_CA_CMD0_RG_TX_ARCLK_PRE_EN));
2263 }
2264
2265
2266 vIO32WriteFldMulti(DDRPHY_R0_B0_RXDVS2, P_Fld(0x0, R0_B0_RXDVS2_R_RK0_DVS_MODE_B0)
2267 | P_Fld(0x0, R0_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0)
2268 | P_Fld(0x0, R0_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0));
2269 vIO32WriteFldMulti(DDRPHY_R1_B0_RXDVS2, P_Fld(0x0, R1_B0_RXDVS2_R_RK1_DVS_MODE_B0)
2270 | P_Fld(0x0, R1_B0_RXDVS2_R_RK1_RX_DLY_RIS_TRACK_GATE_ENA_B0)
2271 | P_Fld(0x0, R1_B0_RXDVS2_R_RK1_RX_DLY_FAL_TRACK_GATE_ENA_B0));
2272 vIO32WriteFldMulti(DDRPHY_R0_B1_RXDVS2, P_Fld(0x0, R0_B1_RXDVS2_R_RK0_DVS_MODE_B1)
2273 | P_Fld(0x0, R0_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1)
2274 | P_Fld(0x0, R0_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1));
2275 vIO32WriteFldMulti(DDRPHY_R1_B1_RXDVS2, P_Fld(0x0, R1_B1_RXDVS2_R_RK1_DVS_MODE_B1)
2276 | P_Fld(0x0, R1_B1_RXDVS2_R_RK1_RX_DLY_RIS_TRACK_GATE_ENA_B1)
2277 | P_Fld(0x0, R1_B1_RXDVS2_R_RK1_RX_DLY_FAL_TRACK_GATE_ENA_B1));
2278
2279 vIO32WriteFldAlign(DDRPHY_SHU_CA_CMD7, 0, SHU_CA_CMD7_R_DMRANKRXDVS_CA);
2280
2281
2282
2283 vIO32WriteFldAlign(DDRPHY_CA_CMD3, 0x1, CA_CMD3_RG_RX_ARCMD_STBENCMP_EN);
2284
2285 vIO32WriteFldAlign(DDRPHY_CA_CMD10, 0x1, CA_CMD10_RG_RX_ARCLK_DQSIENMODE);
2286
2287 vIO32WriteFldAlign(DDRPHY_CA_CMD6, 0x2, CA_CMD6_RG_RX_ARCMD_BIAS_VREF_SEL);
2288
2289 vIO32WriteFldMulti(DDRPHY_B0_DQ3, P_Fld(0x1, B0_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B0)
2290 | P_Fld(0x1, B0_DQ3_RG_RX_ARDQM0_IN_BUFF_EN_B0)
2291 | P_Fld(0x1, B0_DQ3_RG_RX_ARDQS0_IN_BUFF_EN_B0));
2292 vIO32WriteFldMulti(DDRPHY_B1_DQ3, P_Fld(0x1, B1_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B1)
2293 | P_Fld(0x1, B1_DQ3_RG_RX_ARDQM0_IN_BUFF_EN_B1)
2294 | P_Fld(0x1, B1_DQ3_RG_RX_ARDQS0_IN_BUFF_EN_B1));
2295 vIO32WriteFldMulti(DDRPHY_CA_CMD3, P_Fld(0x1, CA_CMD3_RG_RX_ARCMD_IN_BUFF_EN)
2296 | P_Fld(0x1, CA_CMD3_RG_RX_ARCLK_IN_BUFF_EN));
2297
2298 vIO32WriteFldAlign(DDRPHY_B0_DQ3, 0x0, B0_DQ3_RG_RX_ARDQ_SMT_EN_B0);
2299 vIO32WriteFldAlign(DDRPHY_B1_DQ3, 0x0, B1_DQ3_RG_RX_ARDQ_SMT_EN_B1);
2300
2301 vIO32WriteFldAlign(DDRPHY_B0_DQ5, 0x1, B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0);
2302 vIO32WriteFldAlign(DDRPHY_B1_DQ5, 0x1, B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1);
2303 vIO32WriteFldAlign(DDRPHY_CA_CMD5, 0x1, CA_CMD5_RG_RX_ARCLK_DVS_EN);
2304
2305
2306 //vIO32WriteFldAlign(DDRPHY_MISC_VREF_CTRL, P_Fld(0x1, MISC_VREF_CTRL_RG_RVREF_DDR3_SEL)
2307 // | P_Fld(0x0, MISC_VREF_CTRL_RG_RVREF_DDR4_SEL));
2308
2309
2310 vIO32WriteFldMulti(DDRPHY_CA_CMD6, P_Fld(0x0, CA_CMD6_RG_TX_ARCMD_DDR3_SEL)
2311 | P_Fld(0x1, CA_CMD6_RG_TX_ARCMD_DDR4_SEL)
2312 | P_Fld(0x0, CA_CMD6_RG_RX_ARCMD_DDR3_SEL)
2313 | P_Fld(0x1, CA_CMD6_RG_RX_ARCMD_DDR4_SEL));
2314 vIO32WriteFldMulti(DDRPHY_CA_CMD6, P_Fld(0x0, CA_CMD6_RG_TX_ARCMD_DDR3_SEL)
2315 | P_Fld(0x1, CA_CMD6_RG_TX_ARCMD_DDR4_SEL)
2316 | P_Fld(0x0, CA_CMD6_RG_RX_ARCMD_DDR3_SEL)
2317 | P_Fld(0x1, CA_CMD6_RG_RX_ARCMD_DDR4_SEL));
2318 vIO32WriteFldMulti(DDRPHY_MISC_IMP_CTRL0, P_Fld(0x0, MISC_IMP_CTRL0_RG_RIMP_DDR3_SEL)
2319 | P_Fld(0x1, MISC_IMP_CTRL0_RG_RIMP_DDR4_SEL));
2320
2321
2322 vIO32WriteFldAlign(DDRPHY_B0_DQ6, 0x0, B0_DQ6_RG_RX_ARDQ_O1_SEL_B0);
2323 vIO32WriteFldAlign(DDRPHY_B1_DQ6, 0x0, B1_DQ6_RG_RX_ARDQ_O1_SEL_B1);
2324 vIO32WriteFldAlign(DDRPHY_CA_CMD6, 0x0, CA_CMD6_RG_RX_ARCMD_O1_SEL);
2325
2326 vIO32WriteFldAlign(DDRPHY_B0_DQ6, 0x1, B0_DQ6_RG_RX_ARDQ_BIAS_PS_B0);
2327 vIO32WriteFldAlign(DDRPHY_B1_DQ6, 0x1, B1_DQ6_RG_RX_ARDQ_BIAS_PS_B1);
2328 vIO32WriteFldAlign(DDRPHY_CA_CMD6, 0x1, CA_CMD6_RG_RX_ARCMD_BIAS_PS);
2329 vIO32WriteFldAlign(DDRPHY_CA_CMD6, 0x1, CA_CMD6_RG_RX_ARCMD_RES_BIAS_EN);
2330
2331 vIO32WriteFldAlign(DDRPHY_B0_DQ6, 0x0, B0_DQ6_RG_TX_ARDQ_ODTEN_EXT_DIS_B0);
2332 vIO32WriteFldAlign(DDRPHY_B1_DQ6, 0x0, B1_DQ6_RG_TX_ARDQ_ODTEN_EXT_DIS_B1);
2333 vIO32WriteFldAlign(DDRPHY_CA_CMD6, 0x0, CA_CMD6_RG_TX_ARCMD_ODTEN_EXT_DIS);
2334
2335 vIO32WriteFldAlign(DDRPHY_B0_DQ6, 0x1, B0_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B0);
2336 vIO32WriteFldAlign(DDRPHY_B1_DQ6, 0x1, B1_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B1);
2337 vIO32WriteFldAlign(DDRPHY_CA_CMD6, 0x1, CA_CMD6_RG_RX_ARCMD_RPRE_TOG_EN);
2338
2339 if (p->dram_type == TYPE_LPDDR4)
2340 {
2341 if (p->odt_onoff == ODT_ON)
2342 {
2343 u2RXVrefDefault = 0x17;
2344 }
2345 else
2346 {
2347 u2RXVrefDefault = 0x29;
2348 }
2349 }
2350 else if (p->dram_type == TYPE_LPDDR4X)
2351 {
2352 if (p->odt_onoff == ODT_ON)
2353 {
2354 u2RXVrefDefault = 0x17;
2355 }
2356 else
2357 {
2358 u2RXVrefDefault = 0x29;
2359 }
2360 }
2361 else //if(p->dram_type == TYPE_LPDDR4P)
2362 {
2363 u2RXVrefDefault = 0x10;
2364 }
2365
2366 #if CALIBRATION_SPEED_UP_DEBUG
2367 mcSHOW_DBG_MSG2(("\nInit Yulia RX Vref %d, apply to both rank0 and 1\n", u2RXVrefDefault));
2368 #endif
2369
2370 vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ5, u2RXVrefDefault, SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0);
2371 vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ5, u2RXVrefDefault, SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1);
2372 vIO32WriteFldAlign(DDRPHY_B0_DQ5, u2RXVrefDefault, B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0);
2373 vIO32WriteFldAlign(DDRPHY_B1_DQ5, u2RXVrefDefault, B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1);
2374
2375 for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < CHANNEL_NUM; u1ChannelIdx++)
2376 {
2377 for (u1RankIdx = RANK_0; u1RankIdx < RANK_MAX; u1RankIdx++)
2378 {
2379 for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++)
2380 {
2381 gFinalRXVrefDQ[u1ChannelIdx][u1RankIdx][u1ByteIdx] = u2RXVrefDefault;
2382 }
2383 }
2384 }
2385
2386 if ((p->dram_type == TYPE_LPDDR4X) || (p->dram_type == TYPE_LPDDR4P))
2387 {
2388
2389 vIO32WriteFldAlign(DDRPHY_B0_DQ8, 0x1, B0_DQ8_RG_TX_ARDQ_EN_LP4P_B0);
2390 vIO32WriteFldAlign(DDRPHY_B1_DQ8, 0x1, B1_DQ8_RG_TX_ARDQ_EN_LP4P_B1);
2391 vIO32WriteFldAlign(DDRPHY_CA_CMD9, 0x1, CA_CMD9_RG_TX_ARCMD_EN_LP4P);
2392 }
2393
2394
2395
2396 DramcGatingMode(p, 1);
2397
2398 vIO32WriteFldAlign(DDRPHY_CA_CMD8, 0x1, CA_CMD8_RG_TX_RRESETB_DDR3_SEL);
2399 vIO32WriteFldAlign(DDRPHY_CA_CMD8, 0x0, CA_CMD8_RG_TX_RRESETB_DDR4_SEL);
2400
2401
2402
2403 vIO32WriteFldAlign(DRAMC_REG_SHU_MISC, 0x2, SHU_MISC_REQQUE_MAXCNT);
2404
2405
2406 vIO32WriteFldMulti(DRAMC_REG_SHU_DQSG, P_Fld(0x2a, SHU_DQSG_SCINTV) | P_Fld(0x1, SHU_DQSG_DQSINCTL_PRE_SEL));
2407
2408
2409
2410 vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ5, 0x0, SHU_B0_DQ5_RG_ARPI_FB_B0);
2411 vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ5, 0x0, SHU_B1_DQ5_RG_ARPI_FB_B1);
2412 vIO32WriteFldAlign(DDRPHY_SHU_CA_CMD5, 0x0, SHU_CA_CMD5_RG_ARPI_FB_CA);
2413
2414
2415
2416 DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
2417 vIO32WriteFldAlign_All(DDRPHY_SHU_B0_DQ6, 0x0, SHU_B0_DQ6_RG_ARPI_OFFSET_DQSIEN_B0);
2418 vIO32WriteFldAlign_All(DDRPHY_SHU_B1_DQ6, 0x0, SHU_B1_DQ6_RG_ARPI_OFFSET_DQSIEN_B1);
2419 vIO32WriteFldMulti_All(DDRPHY_SHU_CA_CMD6, P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_OFFSET_CLKIEN)
2420 | P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_OFFSET_MCTL_CA));
2421 DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
2422
2423
2424 vIO32WriteFldMulti(DRAMC_REG_SHU_IMPCAL1, P_Fld(8, SHU_IMPCAL1_IMPCAL_CALICNT) | P_Fld(0x10, SHU_IMPCAL1_IMPCALCNT)
2425 | P_Fld(4, SHU_IMPCAL1_IMPCAL_CALEN_CYCLE) | P_Fld(1, SHU_IMPCAL1_IMPCALCNT_OPT)
2426 | P_Fld((p->frequency * 25 / 8000) + 1, SHU_IMPCAL1_IMPCAL_CHKCYCLE));
2427
2428
2429 vIO32WriteFldMulti(DRAMC_REG_SREFCTRL, P_Fld(0x1, SREFCTRL_SCSM_CGAR)
2430 | P_Fld(0x1, SREFCTRL_SCARB_SM_CGAR)
2431 | P_Fld(0x1, SREFCTRL_RDDQSOSC_CGAR)
2432 | P_Fld(0x1, SREFCTRL_HMRRSEL_CGAR));
2433 vIO32WriteFldAlign(DRAMC_REG_PRE_TDQSCK1, 0x1, PRE_TDQSCK1_TXUIPI_CAL_CGAR);
2434
2435 vIO32WriteFldAlign(DRAMC_REG_SHU_MISC, 0xf, SHU_MISC_PREA_INTV);
2436 vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ8, P_Fld(0x1, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0)
2437 | P_Fld(0x1, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0)
2438 | P_Fld(0x1, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0)
2439 | P_Fld(0x1, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0)
2440 | P_Fld(0x1, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0)
2441 | P_Fld(0x1, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0)
2442 | P_Fld(0x1, SHU_B0_DQ8_R_DMSTBEN_SYNC_CG_IG_B0)
2443 | P_Fld(0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0)
2444 | P_Fld(0x1, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0)
2445 | P_Fld(0x1, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0)
2446 | P_Fld(0x0, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0)
2447 | P_Fld(0x7fff, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0));
2448 vIO32WriteFldMulti(DDRPHY_SHU_B1_DQ8, P_Fld(0x1, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1)
2449 | P_Fld(0x1, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1)
2450 | P_Fld(0x1, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1)
2451 | P_Fld(0x1, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1)
2452 | P_Fld(0x1, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1)
2453 | P_Fld(0x1, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1)
2454 | P_Fld(0x1, SHU_B1_DQ8_R_DMSTBEN_SYNC_CG_IG_B1)
2455 | P_Fld(0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1)
2456 | P_Fld(0x1, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1)
2457 | P_Fld(0x1, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1)
2458 | P_Fld(0x0, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1)
2459 | P_Fld(0x7fff, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1));
2460 vIO32WriteFldMulti(DDRPHY_SHU_CA_CMD8, P_Fld(0x1, SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA)
2461 | P_Fld(0x1, SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA)
2462 | P_Fld(0x1, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA)
2463 | P_Fld(0x1, SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA)
2464 | P_Fld(0x1, SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA)
2465 | P_Fld(0x1, SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA)
2466 | P_Fld(0x1, SHU_CA_CMD8_R_DMSTBEN_SYNC_CG_IG_CA)
2467 | P_Fld(0x1, SHU_CA_CMD8_R_DMRXDLY_CG_IG_CA)
2468 | P_Fld(0x1, SHU_CA_CMD8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_CA)
2469 | P_Fld(0x1, SHU_CA_CMD8_R_DMRXDVS_RDSEL_PIPE_CG_IG_CA)
2470 | P_Fld(0x0, SHU_CA_CMD8_R_DMRXDVS_UPD_FORCE_EN_CA)
2471 | P_Fld(0x7fff, SHU_CA_CMD8_R_DMRXDVS_UPD_FORCE_CYC_CA));
2472 vIO32WriteFldAlign(DDRPHY_MISC_CTRL3, 0x1, MISC_CTRL3_R_DDRPHY_COMB_CG_IG);
2473
2474 vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0)
2475 | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0)
2476 | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0));
2477 vIO32WriteFldMulti(DDRPHY_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1)
2478 | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1)
2479 | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1));
2480
2481 vIO32WriteFldMulti(DRAMC_REG_CLKAR, P_Fld(0x1, CLKAR_SELPH_CMD_CG_DIS) | P_Fld(0x7FFF, CLKAR_REQQUE_PACG_DIS));
2482
2483 vIO32WriteFldAlign(DRAMC_REG_SHU_DQSG_RETRY, 0x0, SHU_DQSG_RETRY_R_RETRY_PA_DSIABLE);
2484 vIO32WriteFldAlign(DRAMC_REG_WRITE_LEV, 0x0, WRITE_LEV_DDRPHY_COMB_CG_SEL);
2485 vIO32WriteFldAlign(DRAMC_REG_DUMMY_RD, 0x1, DUMMY_RD_DUMMY_RD_PA_OPT);
2486 vIO32WriteFldMulti(DRAMC_REG_STBCAL2, P_Fld(0x0, STBCAL2_STB_UIDLYCG_IG)
2487 | P_Fld(0x0, STBCAL2_STB_PIDLYCG_IG));
2488 vIO32WriteFldMulti(DRAMC_REG_EYESCAN, P_Fld(0x1, EYESCAN_EYESCAN_DQS_SYNC_EN)
2489 | P_Fld(0x1, EYESCAN_EYESCAN_NEW_DQ_SYNC_EN)
2490 | P_Fld(0x1, EYESCAN_EYESCAN_DQ_SYNC_EN));
2491 //vIO32WriteFldMulti(DRAMC_REG_SHU_ODTCTRL, P_Fld(0x1, SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG)
2492 // | P_Fld(0x1, SHU_ODTCTRL_RODTEN_SELPH_CG_IG));
2493
2494 vIO32WriteFldAlign(DDRPHY_SHU_B0_DLL0, 0x1, SHU_B0_DLL0_RG_ARPISM_MCK_SEL_B0_SHU);
2495 vIO32WriteFldAlign(DDRPHY_SHU_B1_DLL0, 0x1, SHU_B1_DLL0_RG_ARPISM_MCK_SEL_B1_SHU);
2496 //vIO32WriteFldAlign(DDRPHY_SHU_CA_DLL0, 0x1, SHU_CA_DLL0_RG_ARPISM_MCK_SEL_CA_SHU);
2497
2498 vIO32WriteFldAlign(DDRPHY_CA_DLL_ARPI1, 0x1, CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA);
2499
2500
2501
2502
2503 #if (fcFOR_CHIP_ID == fcLafite)
2504
2505 vIO32WriteFldMulti(DRAMC_REG_PERFCTL0, P_Fld(0x1, PERFCTL0_WRFIFO_OPT)
2506 | P_Fld(0x0, PERFCTL0_REORDEREN)
2507 | P_Fld(0x1, PERFCTL0_RWSPLIT));
2508 #endif
2509 vIO32WriteFldAlign(DRAMC_REG_SREFCTRL, 0x1, SREFCTRL_SREF2_OPTION);
2510 vIO32WriteFldAlign(DRAMC_REG_SHUCTRL1, 0x1a, SHUCTRL1_FC_PRDCNT);
2511
2512 #ifdef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY
2513 vIO32WriteFldMulti(DDRPHY_B0_DQ6, P_Fld(0x1, B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0)
2514 | P_Fld(0x1, B0_DQ6_RG_RX_ARDQ_BIAS_EN_B0));
2515 vIO32WriteFldMulti(DDRPHY_B1_DQ6, P_Fld(0x1, B1_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B1)
2516 | P_Fld(0x1, B1_DQ6_RG_RX_ARDQ_BIAS_EN_B1));
2517 vIO32WriteFldMulti(DDRPHY_CA_CMD6, P_Fld(0x1, CA_CMD6_RG_RX_ARCMD_OP_BIAS_SW_EN)
2518 | P_Fld(0x1, CA_CMD6_RG_RX_ARCMD_BIAS_EN));
2519 vIO32WriteFldAlign(DRAMC_REG_STBCAL2, 0x1, STBCAL2_STB_PICG_EARLY_1T_EN);
2520 vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0)
2521 | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0)
2522 | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0)
2523 | P_Fld(0x1, SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0));
2524 vIO32WriteFldMulti(DDRPHY_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1)
2525 | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1)
2526 | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1)
2527 | P_Fld(0x1, SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1));
2528 #else
2529 vIO32WriteFldMulti(DDRPHY_B0_DQ6, P_Fld(0x0, B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0)
2530 | P_Fld(0x0, B0_DQ6_RG_RX_ARDQ_BIAS_EN_B0));
2531 vIO32WriteFldMulti(DDRPHY_B1_DQ6, P_Fld(0x0, B1_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B1)
2532 | P_Fld(0x0, B1_DQ6_RG_RX_ARDQ_BIAS_EN_B1));
2533 vIO32WriteFldMulti(DDRPHY_CA_CMD6, P_Fld(0x0, CA_CMD6_RG_RX_ARCMD_OP_BIAS_SW_EN)
2534 | P_Fld(0x0, CA_CMD6_RG_RX_ARCMD_BIAS_EN));
2535 #endif
2536
2537
2538 //vIO32WriteFldAlign(DRAMC_REG_SHU_RODTENSTB, 0, SHU_RODTENSTB_RODTENSTB_TRACK_EN);
2539
2540
2541 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_DQSG), \
2542 P_Fld(9, SHU_DQSG_STB_UPDMASKCYC) | \
2543 P_Fld(1, SHU_DQSG_STB_UPDMASK_EN));
2544 vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQSCAL, P_Fld(0, SHURK0_DQSCAL_R0DQSIENLLMTEN) | P_Fld(0, SHURK0_DQSCAL_R0DQSIENHLMTEN));
2545 vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQSCAL, P_Fld(0, SHURK1_DQSCAL_R1DQSIENLLMTEN) | P_Fld(0, SHURK1_DQSCAL_R1DQSIENHLMTEN));
2546 vIO32WriteFldMulti(DRAMC_REG_SHU_STBCAL, P_Fld(1, SHU_STBCAL_DQSG_MODE)
2547 | P_Fld(1, SHU_STBCAL_PICGLAT));
2548
2549 #ifdef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY
2550 vIO32WriteFldAlign(DDRPHY_B0_DQ9, 0x4, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0);
2551 vIO32WriteFldAlign(DDRPHY_B1_DQ9, 0x4, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1);
2552 #else
2553
2554 vIO32WriteFldAlign(DDRPHY_B0_DQ9, 0x7, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0);
2555 vIO32WriteFldAlign(DDRPHY_B1_DQ9, 0x7, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1);
2556 #endif
2557 vIO32WriteFldAlign(DDRPHY_CA_CMD10, 0x0, CA_CMD10_R_IN_GATE_EN_LOW_OPT_CA);
2558
2559 vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ8, 0x1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0);
2560 vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ8, 0x1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1);
2561
2562 #ifdef DUMMY_READ_FOR_DQS_GATING_RETRY
2563 if (p->support_rank_num == RANK_SINGLE)
2564 {
2565 vIO32WriteFldAlign(DRAMC_REG_SHU_DQSG_RETRY, 1, SHU_DQSG_RETRY_R_RETRY_1RANK);
2566 }
2567 #endif
2568
2569
2570 #if ENABLE_TX_WDQS
2571 mcSHOW_DBG_MSG2(("Enable WDQS\n"));
2572
2573 vIO32WriteFldMulti(DDRPHY_SHU_B0_DLL1, P_Fld(1, SHU_B0_DLL1_RG_READ_BASE_DQS_EN_B0) | P_Fld(1, SHU_B0_DLL1_RG_READ_BASE_DQSB_EN_B0)
2574 | P_Fld(!p->odt_onoff, SHU_B0_DLL1_RG_ODT_DISABLE_B0));
2575 vIO32WriteFldMulti(DDRPHY_SHU_B1_DLL1, P_Fld(1, SHU_B1_DLL1_RG_READ_BASE_DQS_EN_B1) | P_Fld(1, SHU_B1_DLL1_RG_READ_BASE_DQSB_EN_B1)
2576 | P_Fld(!p->odt_onoff, SHU_B1_DLL1_RG_ODT_DISABLE_B1));
2577 vIO32WriteFldMulti(DRAMC_REG_SHU_ODTCTRL, P_Fld(0x1, SHU_ODTCTRL_RODTE)
2578 | P_Fld(0x1, SHU_ODTCTRL_RODTE2)
2579 | P_Fld(0x1, SHU_ODTCTRL_ROEN));
2580
2581 vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ7, 0x1, SHU_B0_DQ7_R_DMRODTEN_B0);
2582 vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ7, 0x1, SHU_B1_DQ7_R_DMRODTEN_B1);
2583 #if ENABLE_RODT_TRACKING_SAVE_MCK
2584 SetTxWDQSStatusOnOff(1);
2585 #endif
2586
2587 #else
2588
2589 vIO32WriteFldMulti(DDRPHY_SHU_B0_DLL1, P_Fld(0, SHU_B0_DLL1_RG_READ_BASE_DQS_EN_B0) | P_Fld(0, SHU_B0_DLL1_RG_READ_BASE_DQSB_EN_B0)
2590 | P_Fld(0, SHU_B0_DLL1_RG_ODT_DISABLE_B0));
2591 vIO32WriteFldMulti(DDRPHY_SHU_B1_DLL1, P_Fld(0, SHU_B1_DLL1_RG_READ_BASE_DQS_EN_B1) | P_Fld(0, SHU_B1_DLL1_RG_READ_BASE_DQSB_EN_B1)
2592 | P_Fld(0, SHU_B1_DLL1_RG_ODT_DISABLE_B1));
2593 #endif
2594
2595
2596
2597 vIO32WriteFldAlign(DRAMC_REG_DRSCTRL, 0x1, DRSCTRL_DRS_SELFWAKE_DMYRD_DIS);
2598 vIO32WriteFldAlign(DRAMC_REG_REFCTRL0, 0x1, REFCTRL0_REFNA_OPT);
2599 vIO32WriteFldAlign(DRAMC_REG_ZQCS, 0x1, ZQCS_ZQCS_MASK_SEL_CGAR);
2600 vIO32WriteFldMulti(DRAMC_REG_DUMMY_RD, P_Fld(0x1, DUMMY_RD_DMYRD_REORDER_DIS) | P_Fld(0x0, DUMMY_RD_DMYRD_HPRI_DIS));
2601 vIO32WriteFldAlign(DRAMC_REG_SHUCTRL2, 0x1, SHUCTRL2_R_DVFS_SREF_OPT);
2602 vIO32WriteFldAlign(DRAMC_REG_SHUCTRL3, 0xb, SHUCTRL3_VRCGDIS_PRDCNT);
2603 vIO32WriteFldAlign(DDRPHY_MISC_CTRL3, 0x1, MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG);
2604
2605 vIO32WriteFldMulti(DDRPHY_B0_DLL_ARPI1, P_Fld(0x1, B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0_REG_OPT)
2606 | P_Fld(0x1, B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0));
2607 vIO32WriteFldMulti(DDRPHY_B1_DLL_ARPI1, P_Fld(0x1, B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1_REG_OPT)
2608 | P_Fld(0x1, B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1));
2609 vIO32WriteFldAlign(DDRPHY_CA_DLL_ARPI1, 0x1, CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT);
2610 vIO32WriteFldAlign(DDRPHY_MISC_CTRL0, 0, MISC_CTRL0_R_DMSHU_PHYDCM_FORCEOFF);
2611
2612 vIO32WriteFldAlign(DDRPHY_MISC_RXDVS2, 1, MISC_RXDVS2_R_DMRXDVS_SHUFFLE_CTRL_CG_IG);
2613 vIO32WriteFldAlign(DRAMC_REG_CLKCTRL, 0x1, CLKCTRL_SEQCLKRUN3);
2614 vIO32WriteFldAlign(DRAMC_REG_REFCTRL1, 1, REFCTRL1_SREF_CG_OPT);
2615 vIO32WriteFldMulti(DRAMC_REG_SHUCTRL, P_Fld(0x0, SHUCTRL_DVFS_CG_OPT) | P_Fld(0x3, SHUCTRL_R_DVFS_PICG_MARGIN2) | P_Fld(0x3, SHUCTRL_R_DVFS_PICG_MARGIN3));
2616 //vIO32WriteFldMulti(DRAMC_REG_SHUCTRL, P_Fld(0x3, SHUCTRL_R_DVFS_PICG_MARGIN2) | P_Fld(0x3, SHUCTRL_R_DVFS_PICG_MARGIN3));
2617 vIO32WriteFldMulti(DRAMC_REG_SHUCTRL2, P_Fld(0x1, SHUCTRL2_SHORTQ_OPT) | P_Fld(0x3, SHUCTRL2_R_DVFS_PICG_MARGIN));
2618 vIO32WriteFldAlign(DRAMC_REG_STBCAL2, 0x0, STBCAL2_STB_DBG_EN);
2619 vIO32WriteFldMulti(DRAMC_REG_PRE_TDQSCK1, P_Fld(0x0, PRE_TDQSCK1_APHY_CG_OPT1) | P_Fld(0x0, PRE_TDQSCK1_SHU_PRELOAD_TX_HW));
2620
2621 #ifndef FIRST_BRING_UP
2622 if (u2DFSGetHighestFreq(p) >= 1866)
2623 #endif
2624 {
2625
2626 vIO32WriteFldAlign(DRAMC_REG_CLKAR, 1, CLKAR_SELPH_4LCG_DIS);
2627 }
2628
2629 #if TX_OE_EXTEND
2630 UpdateTxOEN(p);
2631 #endif
2632
2633 vIO32WriteFldAlign(DRAMC_REG_CKECTRL, 0x1, CKECTRL_CKEPBDIS);
2634
2635 vIO32WriteFldMulti(DDRPHY_CA_TX_MCK, P_Fld(0x1, CA_TX_MCK_R_DMRESET_FRPHY_OPT) | P_Fld(0xa, CA_TX_MCK_R_DMRESETB_DRVP_FRPHY) | P_Fld(0xa, CA_TX_MCK_R_DMRESETB_DRVN_FRPHY));
2636
2637
2638 vIO32WriteFldAlign(DRAMC_REG_CKECTRL, 0x0, CKECTRL_CKELCKFIX);
2639
2640
2641 vIO32WriteFldAlign(DRAMC_REG_SHU_RODTENSTB, 0x0, SHU_RODTENSTB_RODTENSTB_4BYTE_EN);
2642
2643 #if (fcFOR_CHIP_ID == fcLafite)
2644
2645 vIO32WriteFldAlign(DRAMC_REG_SHU_ODTCTRL, 0x1, SHU_ODTCTRL_RODTEN_OPT);
2646 vIO32WriteFldMulti(DRAMC_REG_SHU_RODTENSTB, P_Fld(0, SHU_RODTENSTB_RODTEN_P1_ENABLE)
2647 | P_Fld(1, SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL)
2648 | P_Fld(1, SHU_RODTENSTB_RODTENSTB_SELPH_MODE));
2649 vIO32WriteFldAlign(DRAMC_REG_SHU_STBCAL, 0x0, SHU_STBCAL_DQSIEN_PICG_MODE);
2650 #if ENABLE_RODT_TRACKING
2651 if (vGet_Div_Mode(p) == DIV4_MODE)
2652 vIO32WriteFldAlign(DRAMC_REG_SHU_RODTENSTB, 0x21, SHU_RODTENSTB_RODTENSTB_OFFSET);
2653 else
2654 vIO32WriteFldAlign(DRAMC_REG_SHU_RODTENSTB, 0x11, SHU_RODTENSTB_RODTENSTB_OFFSET);
2655 #endif
2656
2657
2658 U8 u1ReadROEN;
2659 u1ReadROEN = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_ODTCTRL), SHU_ODTCTRL_ROEN);
2660 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_RODTENSTB), P_Fld(0xff, SHU_RODTENSTB_RODTENSTB_EXT) | \
2661 P_Fld(u1ReadROEN, SHU_RODTENSTB_RODTENSTB_TRACK_EN));
2662 #endif
2663
2664 #if (fcFOR_CHIP_ID == fcLafite)
2665 vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ3, 0x0, SHU_B0_DQ3_RG_TX_ARDQS0_PU_PRE_B0);
2666 vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ3, 0x0, SHU_B1_DQ3_RG_TX_ARDQS0_PU_PRE_B1);
2667 #endif
2668
2669 #if ENABLE_FIX_PRE8_DVFS_AT_CKEPRD
2670 vIO32WriteFldAlign(DRAMC_REG_MISCTL0, 0x1, MISCTL0_PG_WAKEUP_OPT);
2671 #endif
2672
2673 #if ENABLE_TMRRI_NEW_MODE
2674
2675 vIO32WriteFldAlign(DRAMC_REG_SPCMDCTRL, (p->support_rank_num == RANK_DUAL)? (1): (0), SPCMDCTRL_HMR4_TOG_OPT);
2676 #else
2677 vIO32WriteFldAlign(DRAMC_REG_SPCMDCTRL, 0x0, SPCMDCTRL_HMR4_TOG_OPT);
2678 #endif
2679
2680 #if RX_PICG_NEW_MODE
2681 RXPICGSetting(p);
2682 #endif
2683
2684
2685 vIO32WriteFldAlign(DDRPHY_B0_DQ9, 0x1, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0);
2686 vIO32WriteFldAlign(DDRPHY_B1_DQ9, 0x1, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1);
2687
2688
2689 vIO32WriteFldMulti(DDRPHY_B0_DQ9, P_Fld(4, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0) | P_Fld(0, B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0));
2690 vIO32WriteFldMulti(DDRPHY_B1_DQ9, P_Fld(4, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1) | P_Fld(0, B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1));
2691 vIO32WriteFldMulti(DDRPHY_CA_CMD10, P_Fld(0, CA_CMD10_R_IN_GATE_EN_LOW_OPT_CA) | P_Fld(0, CA_CMD10_R_DMRXDVS_R_F_DLY_RK_OPT));
2692 vIO32WriteFldAlign(DDRPHY_MISC_CTRL3, 0x0, MISC_CTRL3_ARPI_CG_RK1_SRC_SEL);
2693 vIO32WriteFldAlign(DRAMC_REG_SHU_RANK_SEL_STB, 0x1, SHU_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK);
2694 vIO32WriteFldAlign(DRAMC_REG_SHU_RANK_SEL_STB, 0x0, SHU_RANK_SEL_STB_RANK_SEL_STB_SERMODE);
2695
2696
2697 vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ3, P_Fld(0, SHU_B0_DQ3_RG_TX_ARDQS0_PDB_B0) | P_Fld(0, SHU_B0_DQ3_RG_TX_ARDQ_PDB_B0));
2698 vIO32WriteFldMulti(DDRPHY_SHU_B1_DQ3, P_Fld(0, SHU_B1_DQ3_RG_TX_ARDQS0_PDB_B1) | P_Fld(0, SHU_B1_DQ3_RG_TX_ARDQ_PDB_B1));
2699
2700
2701 vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ5, 0x4, SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0);
2702 vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ5, 0x4, SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1);
2703
2704 #if ENABLE_REMOVE_MCK8X_UNCERT_LOWPOWER_OPTION
2705 vIO32WriteFldAlign(DDRPHY_MISC_VREF_CTRL, 0x7F, MISC_VREF_CTRL_MISC_LP_8X_MUX);
2706 vIO32WriteFldAlign(DDRPHY_MISC_VREF_CTRL, 0x7F, MISC_VREF_CTRL_MISC_LP_DDR400_MUX);
2707 #endif
2708
2709 #if ENABLE_REMOVE_MCK8X_UNCERT_DFS_OPTION
2710 vIO32WriteFldAlign(DDRPHY_DVFS_EMI_CLK, 1, DVFS_EMI_CLK_R_DDRPHY_SHUFFLE_MUX_ENABLE);
2711 vIO32WriteFldAlign(DRAMC_REG_DVFSDLL2, 1, DVFSDLL2_R_SHUFFLE_PI_RESET_ENABLE);
2712 vIO32WriteFldAlign(DRAMC_REG_DVFSDLL2, 3, DVFSDLL2_R_DVFS_MCK8X_MARGIN);
2713
2714 vIO32WriteFldAlign(DDRPHY_B0_DLL_ARPI0, 1, B0_DLL_ARPI0_RG_ARPI_MCK8X_SEL_B0);
2715 vIO32WriteFldAlign(DDRPHY_B1_DLL_ARPI0, 1, B1_DLL_ARPI0_RG_ARPI_MCK8X_SEL_B1);
2716 vIO32WriteFldAlign(DDRPHY_CA_DLL_ARPI0, 1, CA_DLL_ARPI0_RG_ARPI_MCK8X_SEL_CA);
2717
2718 vIO32WriteFldAlign(DRAMC_REG_DVFSDLL2, 3, DVFSDLL2_R_DVFS_PICG_MARGIN4_NEW);
2719 #endif
2720
2721 vIO32WriteFldAlign(DDRPHY_SHU_MISC1, 0x00000020, SHU_MISC1_DR_EMI_RESERVE);
2722
2723
2724 vIO32WriteFldMulti(DRAMC_REG_SHU_DQSG_RETRY, P_Fld(0x0, SHU_DQSG_RETRY_R_RETRY_USE_BURST_MDOE)
2725 | P_Fld(0x0, SHU_DQSG_RETRY_R_RDY_SEL_DLE)
2726 | P_Fld(0x0, SHU_DQSG_RETRY_R_DQSIENLAT)
2727 | P_Fld(0x0, SHU_DQSG_RETRY_R_RETRY_ROUND_NUM)
2728 | P_Fld(0x0, SHU_DQSG_RETRY_R_RETRY_ONCE));
2729
2730 vIO32WriteFldAlign(DRAMC_REG_PRE_TDQSCK1, 0x1, PRE_TDQSCK1_TX_TRACKING_OPT);
2731
2732
2733 vIO32WriteFldAlign(DRAMC_REG_SPCMDCTRL, 0x1, SPCMDCTRL_SPDR_MR4_OPT);
2734
2735
2736 vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ6, 0x0, SHU_B0_DQ6_RG_ARPI_OFFSET_MCTL_B0);
2737 vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ6, 0x0, SHU_B1_DQ6_RG_ARPI_OFFSET_MCTL_B1);
2738 vIO32WriteFldAlign(DDRPHY_CA_CMD5, 0x29, CA_CMD5_RG_RX_ARCMD_EYE_VREF_SEL);
2739 vIO32WriteFldAlign(DDRPHY_SHU_CA_CMD5, 0x4, SHU_CA_CMD5_RG_RX_ARCMD_FIFO_DQSI_DLY);
2740
2741
2742 #if CMD_CKE_WORKAROUND_FIX
2743 CMD_CKE_Modified_txp_Setting(p);
2744 #endif
2745
2746 #if RX_PIPE_BYPASS_ENABLE
2747 vIO32WriteFldAlign(DDRPHY_SHU_MISC0, 0x1, SHU_MISC0_R_RX_PIPE_BYPASS_EN);
2748 #endif
2749
2750 #if CBT_MOVE_CA_INSTEAD_OF_CLK
2751 if (u1IsPhaseMode(p) == FALSE)
2752 {
2753 u1CaUI = 0;
2754 u1CaPI = 32;
2755 }
2756 else
2757 {
2758 u1CaUI = 0;
2759 u1CaPI = 24;
2760 }
2761
2762 DramcCmdUIDelaySetting(p, u1CaUI);
2763
2764
2765
2766 u1RankIdxBak = u1GetRank(p);
2767
2768 for (u1RankIdx = 0; u1RankIdx < (U32)(p->support_rank_num); u1RankIdx++)
2769 {
2770 vSetRank(p, u1RankIdx);
2771
2772 CBTDelayCACLK(p, u1CaPI);
2773 }
2774
2775 vSetRank(p, u1RankIdxBak);
2776 #endif
2777
2778
2779 #if XRTRTR_NEW_CROSS_RK_MODE
2780 vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ6, 0, SHU_B0_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B0);
2781 vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ6, 0, SHU_B1_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B1);
2782 vIO32WriteFldAlign(DRAMC_REG_SHU_RANK_SEL_STB, 0, SHU_RANK_SEL_STB_RANK_SEL_STB_EN);
2783 #endif
2784
2785
2786
2787 vIO32WriteFldAlign(DRAMC_REG_DRSCTRL, 0x1, DRSCTRL_DRSCLR_RK0_EN);
2788 vIO32WriteFldMulti(DRAMC_REG_STBCAL2, P_Fld(0x7, STBCAL2_STBCAL_UI_UPD_MASK_OPT)
2789 |P_Fld(0x1, STBCAL2_STBCAL_UI_UPD_MASK_EN));
2790 #if XRTRTR_NEW_CROSS_RK_MODE
2791 vIO32WriteFldMulti(DRAMC_REG_SHU_PHY_RX_CTRL, P_Fld(0x2, SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET)
2792 |P_Fld(0x2, SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET)
2793 |P_Fld(0x1, SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN));
2794 #endif
2795
2796 #endif// #if __A60868_TO_BE_PORTING__
2797 return DRAM_OK;
2798 }
2799 #endif
2800 #if __A60868_TO_BE_PORTING__
2801 #if LEGACY_DELAY_CELL
2802
LegacyDlyCellInitLP4_DDR2667(DRAMC_CTX_T * p)2803 static void LegacyDlyCellInitLP4_DDR2667(DRAMC_CTX_T *p)
2804 {
2805 vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ0, P_Fld(0xa, SHU_R1_B0_DQ0_RK1_TX_ARDQ7_DLY_B0)
2806 | P_Fld(0xa, SHU_R1_B0_DQ0_RK1_TX_ARDQ6_DLY_B0)
2807 | P_Fld(0xa, SHU_R1_B0_DQ0_RK1_TX_ARDQ5_DLY_B0)
2808 | P_Fld(0xa, SHU_R1_B0_DQ0_RK1_TX_ARDQ4_DLY_B0)
2809 | P_Fld(0xa, SHU_R1_B0_DQ0_RK1_TX_ARDQ3_DLY_B0)
2810 | P_Fld(0xa, SHU_R1_B0_DQ0_RK1_TX_ARDQ2_DLY_B0)
2811 | P_Fld(0xa, SHU_R1_B0_DQ0_RK1_TX_ARDQ1_DLY_B0)
2812 | P_Fld(0xa, SHU_R1_B0_DQ0_RK1_TX_ARDQ0_DLY_B0));
2813 vIO32WriteFldAlign(DDRPHY_SHU_R1_B0_DQ1, 0xa, SHU_R1_B0_DQ1_RK1_TX_ARDQM0_DLY_B0);
2814 vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ0, P_Fld(0xa, SHU_R1_B1_DQ0_RK1_TX_ARDQ7_DLY_B1)
2815 | P_Fld(0xa, SHU_R1_B1_DQ0_RK1_TX_ARDQ6_DLY_B1)
2816 | P_Fld(0xa, SHU_R1_B1_DQ0_RK1_TX_ARDQ5_DLY_B1)
2817 | P_Fld(0xa, SHU_R1_B1_DQ0_RK1_TX_ARDQ4_DLY_B1)
2818 | P_Fld(0xa, SHU_R1_B1_DQ0_RK1_TX_ARDQ3_DLY_B1)
2819 | P_Fld(0xa, SHU_R1_B1_DQ0_RK1_TX_ARDQ2_DLY_B1)
2820 | P_Fld(0xa, SHU_R1_B1_DQ0_RK1_TX_ARDQ1_DLY_B1)
2821 | P_Fld(0xa, SHU_R1_B1_DQ0_RK1_TX_ARDQ0_DLY_B1));
2822 vIO32WriteFldAlign(DDRPHY_SHU_R1_B1_DQ1, 0xa, SHU_R1_B1_DQ1_RK1_TX_ARDQM0_DLY_B1);
2823 }
2824
LegacyDlyCellInitLP4_DDR1600(DRAMC_CTX_T * p)2825 static void LegacyDlyCellInitLP4_DDR1600(DRAMC_CTX_T *p)
2826 {
2827 vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ0, P_Fld(0xd, SHU_R1_B0_DQ0_RK1_TX_ARDQ7_DLY_B0)
2828 | P_Fld(0xd, SHU_R1_B0_DQ0_RK1_TX_ARDQ6_DLY_B0)
2829 | P_Fld(0xd, SHU_R1_B0_DQ0_RK1_TX_ARDQ5_DLY_B0)
2830 | P_Fld(0xd, SHU_R1_B0_DQ0_RK1_TX_ARDQ4_DLY_B0)
2831 | P_Fld(0xd, SHU_R1_B0_DQ0_RK1_TX_ARDQ3_DLY_B0)
2832 | P_Fld(0xd, SHU_R1_B0_DQ0_RK1_TX_ARDQ2_DLY_B0)
2833 | P_Fld(0xd, SHU_R1_B0_DQ0_RK1_TX_ARDQ1_DLY_B0)
2834 | P_Fld(0xd, SHU_R1_B0_DQ0_RK1_TX_ARDQ0_DLY_B0));
2835 vIO32WriteFldAlign(DDRPHY_SHU_R1_B0_DQ1, 0xd, SHU_R1_B0_DQ1_RK1_TX_ARDQM0_DLY_B0);
2836 vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ0, P_Fld(0xd, SHU_R1_B1_DQ0_RK1_TX_ARDQ7_DLY_B1)
2837 | P_Fld(0xd, SHU_R1_B1_DQ0_RK1_TX_ARDQ6_DLY_B1)
2838 | P_Fld(0xd, SHU_R1_B1_DQ0_RK1_TX_ARDQ5_DLY_B1)
2839 | P_Fld(0xd, SHU_R1_B1_DQ0_RK1_TX_ARDQ4_DLY_B1)
2840 | P_Fld(0xd, SHU_R1_B1_DQ0_RK1_TX_ARDQ3_DLY_B1)
2841 | P_Fld(0xd, SHU_R1_B1_DQ0_RK1_TX_ARDQ2_DLY_B1)
2842 | P_Fld(0xd, SHU_R1_B1_DQ0_RK1_TX_ARDQ1_DLY_B1)
2843 | P_Fld(0xd, SHU_R1_B1_DQ0_RK1_TX_ARDQ0_DLY_B1));
2844 vIO32WriteFldAlign(DDRPHY_SHU_R1_B1_DQ1, 0xd, SHU_R1_B1_DQ1_RK1_TX_ARDQM0_DLY_B1);
2845 }
2846
LegacyDlyCellInitLP4_DDR3200(DRAMC_CTX_T * p)2847 static void LegacyDlyCellInitLP4_DDR3200(DRAMC_CTX_T *p)
2848 {
2849 vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ0, P_Fld(0xa, SHU_R1_B0_DQ0_RK1_TX_ARDQ7_DLY_B0)
2850 | P_Fld(0xa, SHU_R1_B0_DQ0_RK1_TX_ARDQ6_DLY_B0)
2851 | P_Fld(0xa, SHU_R1_B0_DQ0_RK1_TX_ARDQ5_DLY_B0)
2852 | P_Fld(0xa, SHU_R1_B0_DQ0_RK1_TX_ARDQ4_DLY_B0)
2853 | P_Fld(0xa, SHU_R1_B0_DQ0_RK1_TX_ARDQ3_DLY_B0)
2854 | P_Fld(0xa, SHU_R1_B0_DQ0_RK1_TX_ARDQ2_DLY_B0)
2855 | P_Fld(0xa, SHU_R1_B0_DQ0_RK1_TX_ARDQ1_DLY_B0)
2856 | P_Fld(0xa, SHU_R1_B0_DQ0_RK1_TX_ARDQ0_DLY_B0));
2857 vIO32WriteFldAlign(DDRPHY_SHU_R1_B0_DQ1, 0xa, SHU_R1_B0_DQ1_RK1_TX_ARDQM0_DLY_B0);
2858 vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ0, P_Fld(0xa, SHU_R1_B1_DQ0_RK1_TX_ARDQ7_DLY_B1)
2859 | P_Fld(0xa, SHU_R1_B1_DQ0_RK1_TX_ARDQ6_DLY_B1)
2860 | P_Fld(0xa, SHU_R1_B1_DQ0_RK1_TX_ARDQ5_DLY_B1)
2861 | P_Fld(0xa, SHU_R1_B1_DQ0_RK1_TX_ARDQ4_DLY_B1)
2862 | P_Fld(0xa, SHU_R1_B1_DQ0_RK1_TX_ARDQ3_DLY_B1)
2863 | P_Fld(0xa, SHU_R1_B1_DQ0_RK1_TX_ARDQ2_DLY_B1)
2864 | P_Fld(0xa, SHU_R1_B1_DQ0_RK1_TX_ARDQ1_DLY_B1)
2865 | P_Fld(0xa, SHU_R1_B1_DQ0_RK1_TX_ARDQ0_DLY_B1));
2866 vIO32WriteFldAlign(DDRPHY_SHU_R1_B1_DQ1, 0xa, SHU_R1_B1_DQ1_RK1_TX_ARDQM0_DLY_B1);
2867 }
2868 #endif
2869
2870 #if LEGACY_TX_TRACK
2871
LegacyTxTrackLP4_DDR2667(DRAMC_CTX_T * p)2872 static void LegacyTxTrackLP4_DDR2667(DRAMC_CTX_T *p)
2873 {
2874 vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSCTHRD, P_Fld(0xc, SHU_DQSOSCTHRD_DQSOSCTHRD_DEC_RK0)
2875 | P_Fld(0xc, SHU_DQSOSCTHRD_DQSOSCTHRD_INC_RK0)
2876 | P_Fld(0xc, SHU_DQSOSCTHRD_DQSOSCTHRD_INC_RK1_7TO0));
2877 vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSC_PRD, P_Fld(0xc, SHU_DQSOSC_PRD_DQSOSCTHRD_DEC_RK1)
2878 | P_Fld(0x0, SHU_DQSOSC_PRD_DQSOSCTHRD_INC_RK1_11TO8)
2879 | P_Fld(0x10, SHU_DQSOSC_PRD_DQSOSC_PRDCNT));
2880 vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQSOSC, P_Fld(0x1ae, SHURK0_DQSOSC_DQSOSC_BASE_RK0_B1)
2881 | P_Fld(0x1ae, SHURK0_DQSOSC_DQSOSC_BASE_RK0));
2882 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
2883 {
2884 vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL1, P_Fld(0x354, SHURK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)
2885 | P_Fld(0x354, SHURK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0));
2886 vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL2, P_Fld(0x354, SHURK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)
2887 | P_Fld(0x354, SHURK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0));
2888 }
2889 else
2890 {
2891 vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL1, P_Fld(0x254, SHURK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)
2892 | P_Fld(0x254, SHURK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0));
2893 vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL2, P_Fld(0x254, SHURK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)
2894 | P_Fld(0x254, SHURK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0));
2895 }
2896 vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL3, P_Fld(0x14, SHURK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1_B4TO0)
2897 | P_Fld(0x14, SHURK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0_B4TO0)
2898 | P_Fld(0x18, SHURK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1)
2899 | P_Fld(0x18, SHURK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0));
2900 vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL4, P_Fld(0x14, SHURK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1_B4TO0)
2901 | P_Fld(0x14, SHURK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0_B4TO0)
2902 | P_Fld(0x18, SHURK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1)
2903 | P_Fld(0x18, SHURK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0));
2904 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
2905 {
2906 vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL5, P_Fld(0x354, SHURK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)
2907 | P_Fld(0x354, SHURK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0));
2908 }
2909 else
2910 {
2911 vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL5, P_Fld(0x254, SHURK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)
2912 | P_Fld(0x254, SHURK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0));
2913 }
2914 vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQSOSC, P_Fld(0x160, SHURK1_DQSOSC_DQSOSC_BASE_RK1_B1)
2915 | P_Fld(0x160, SHURK1_DQSOSC_DQSOSC_BASE_RK1));
2916 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
2917 {
2918 vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL1, P_Fld(0x354, SHURK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ1)
2919 | P_Fld(0x354, SHURK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ0));
2920 vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL2, P_Fld(0x354, SHURK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ1)
2921 | P_Fld(0x354, SHURK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ0));
2922 }
2923 else
2924 {
2925 vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL1, P_Fld(0x254, SHURK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ1)
2926 | P_Fld(0x254, SHURK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ0));
2927 vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL2, P_Fld(0x254, SHURK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ1)
2928 | P_Fld(0x254, SHURK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ0));
2929 }
2930 vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL3, P_Fld(0x14, SHURK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ1_B4TO0)
2931 | P_Fld(0x14, SHURK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ0_B4TO0)
2932 | P_Fld(0x18, SHURK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ1)
2933 | P_Fld(0x18, SHURK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ0));
2934 vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL4, P_Fld(0x14, SHURK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM1_B4TO0)
2935 | P_Fld(0x14, SHURK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM0_B4TO0)
2936 | P_Fld(0x18, SHURK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM1)
2937 | P_Fld(0x18, SHURK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM0));
2938 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
2939 {
2940 vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL5, P_Fld(0x354, SHURK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM1)
2941 | P_Fld(0x354, SHURK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM0));
2942 }
2943 else
2944 {
2945 vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL5, P_Fld(0x254, SHURK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM1)
2946 | P_Fld(0x254, SHURK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM0));
2947 }
2948 }
2949
LegacyTxTrackLP4_DDR1600(DRAMC_CTX_T * p)2950 static void LegacyTxTrackLP4_DDR1600(DRAMC_CTX_T *p)
2951 {
2952 vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSCTHRD, P_Fld(0x14, SHU_DQSOSCTHRD_DQSOSCTHRD_DEC_RK0)
2953 | P_Fld(0x14, SHU_DQSOSCTHRD_DQSOSCTHRD_INC_RK0)
2954 | P_Fld(0x14, SHU_DQSOSCTHRD_DQSOSCTHRD_INC_RK1_7TO0));
2955 vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSC_PRD, P_Fld(0x14, SHU_DQSOSC_PRD_DQSOSCTHRD_DEC_RK1)
2956 | P_Fld(0x0, SHU_DQSOSC_PRD_DQSOSCTHRD_INC_RK1_11TO8)
2957 | P_Fld(0xf, SHU_DQSOSC_PRD_DQSOSC_PRDCNT));
2958 vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQSOSC, P_Fld(0x2d0, SHURK0_DQSOSC_DQSOSC_BASE_RK0_B1)
2959 | P_Fld(0x2d0, SHURK0_DQSOSC_DQSOSC_BASE_RK0));
2960 vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL1, P_Fld(0x23a, SHURK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)
2961 | P_Fld(0x23a, SHURK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0));
2962 vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL2, P_Fld(0x23a, SHURK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)
2963 | P_Fld(0x23a, SHURK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0));
2964 vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL3, P_Fld(0x1a, SHURK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1_B4TO0)
2965 | P_Fld(0x1a, SHURK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0_B4TO0)
2966 | P_Fld(0xf, SHURK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1)
2967 | P_Fld(0xf, SHURK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0));
2968 vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL4, P_Fld(0x1a, SHURK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1_B4TO0)
2969 | P_Fld(0x1a, SHURK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0_B4TO0)
2970 | P_Fld(0xf, SHURK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1)
2971 | P_Fld(0xf, SHURK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0));
2972 vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL5, P_Fld(0x23e, SHURK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)
2973 | P_Fld(0x23e, SHURK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0));
2974 vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQSOSC, P_Fld(0x24e, SHURK1_DQSOSC_DQSOSC_BASE_RK1_B1)
2975 | P_Fld(0x24e, SHURK1_DQSOSC_DQSOSC_BASE_RK1));
2976 vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL1, P_Fld(0x23e, SHURK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ1)
2977 | P_Fld(0x23e, SHURK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ0));
2978 vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL2, P_Fld(0x23e, SHURK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ1)
2979 | P_Fld(0x23e, SHURK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ0));
2980 vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL3, P_Fld(0x1e, SHURK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ1_B4TO0)
2981 | P_Fld(0x1e, SHURK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ0_B4TO0)
2982 | P_Fld(0xf, SHURK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ1)
2983 | P_Fld(0xf, SHURK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ0));
2984 vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL4, P_Fld(0x1e, SHURK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM1_B4TO0)
2985 | P_Fld(0x1e, SHURK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM0_B4TO0)
2986 | P_Fld(0xf, SHURK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM1)
2987 | P_Fld(0xf, SHURK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM0));
2988 vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL5, P_Fld(0x23e, SHURK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM1)
2989 | P_Fld(0x23e, SHURK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM0));
2990 }
2991
LegacyTxTrackLP4_DDR3200(DRAMC_CTX_T * p)2992 static void LegacyTxTrackLP4_DDR3200(DRAMC_CTX_T *p)
2993 {
2994 vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSCTHRD, P_Fld(0xa, SHU_DQSOSCTHRD_DQSOSCTHRD_DEC_RK0)
2995 | P_Fld(0xa, SHU_DQSOSCTHRD_DQSOSCTHRD_INC_RK0)
2996 | P_Fld(0xa, SHU_DQSOSCTHRD_DQSOSCTHRD_INC_RK1_7TO0));
2997 vIO32WriteFldMulti(DRAMC_REG_SHU_DQSOSC_PRD, P_Fld(0xa, SHU_DQSOSC_PRD_DQSOSCTHRD_DEC_RK1)
2998 | P_Fld(0x0, SHU_DQSOSC_PRD_DQSOSCTHRD_INC_RK1_11TO8)
2999 | P_Fld(0x10, SHU_DQSOSC_PRD_DQSOSC_PRDCNT));
3000 vIO32WriteFldAlign(DRAMC_REG_SHU_DQSOSCR, 0x10, SHU_DQSOSCR_DQSOSCRCNT);
3001 vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQSOSC, P_Fld(0x168, SHURK0_DQSOSC_DQSOSC_BASE_RK0_B1)
3002 | P_Fld(0x168, SHURK0_DQSOSC_DQSOSC_BASE_RK0));
3003 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
3004 {
3005 vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL1, P_Fld(0x3da, SHURK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)
3006 | P_Fld(0x3da, SHURK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0));
3007 vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL2, P_Fld(0x3da, SHURK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)
3008 | P_Fld(0x3da, SHURK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0));
3009 }
3010 else
3011 {
3012 vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL1, P_Fld(0x2da, SHURK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1)
3013 | P_Fld(0x2da, SHURK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0));
3014 vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL2, P_Fld(0x2da, SHURK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1)
3015 | P_Fld(0x2da, SHURK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0));
3016 }
3017 vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL3, P_Fld(0x1a, SHURK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1_B4TO0)
3018 | P_Fld(0x1a, SHURK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0_B4TO0)
3019 | P_Fld(0x1c, SHURK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1)
3020 | P_Fld(0x1c, SHURK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0));
3021 vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL4, P_Fld(0x1a, SHURK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1_B4TO0)
3022 | P_Fld(0x1a, SHURK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0_B4TO0)
3023 | P_Fld(0x1c, SHURK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1)
3024 | P_Fld(0x1c, SHURK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0));
3025 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
3026 {
3027 vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL5, P_Fld(0x3da, SHURK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)
3028 | P_Fld(0x3da, SHURK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0));
3029 }
3030 else
3031 {
3032 vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQS2DQ_CAL5, P_Fld(0x2da, SHURK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1)
3033 | P_Fld(0x2da, SHURK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0));
3034 }
3035 vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQSOSC, P_Fld(0x127, SHURK1_DQSOSC_DQSOSC_BASE_RK1_B1)
3036 | P_Fld(0x127, SHURK1_DQSOSC_DQSOSC_BASE_RK1));
3037 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
3038 {
3039 vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL1, P_Fld(0x3d4, SHURK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ1)
3040 | P_Fld(0x3d4, SHURK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ0));
3041 vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL2, P_Fld(0x3d4, SHURK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ1)
3042 | P_Fld(0x3d4, SHURK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ0));
3043 }
3044 else
3045 {
3046 vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL1, P_Fld(0x2d4, SHURK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ1)
3047 | P_Fld(0x2d4, SHURK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ0));
3048 vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL2, P_Fld(0x2d4, SHURK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ1)
3049 | P_Fld(0x2d4, SHURK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ0));
3050 }
3051 vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL3, P_Fld(0x14, SHURK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ1_B4TO0)
3052 | P_Fld(0x14, SHURK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ0_B4TO0)
3053 | P_Fld(0x1c, SHURK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ1)
3054 | P_Fld(0x1c, SHURK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ0));
3055 vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL4, P_Fld(0x14, SHURK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM1_B4TO0)
3056 | P_Fld(0x14, SHURK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM0_B4TO0)
3057 | P_Fld(0x1c, SHURK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM1)
3058 | P_Fld(0x1c, SHURK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM0));
3059 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
3060 {
3061 vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL5, P_Fld(0x3d4, SHURK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM1)
3062 | P_Fld(0x3d4, SHURK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM0));
3063 }
3064 else
3065 {
3066 vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQS2DQ_CAL5, P_Fld(0x2d4, SHURK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM1)
3067 | P_Fld(0x2d4, SHURK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM0));
3068 }
3069 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
3070 {
3071 vIO32WriteFldAlign(DRAMC_REG_DQSOSCR, 0x1, DQSOSCR_RK0_BYTE_MODE);
3072 vIO32WriteFldAlign(DRAMC_REG_DQSOSCR, 0x1, DQSOSCR_RK1_BYTE_MODE);
3073 }
3074 }
3075 #endif
3076
3077 #if LEGACY_TDQSCK_PRECAL
3078
LegacyPreCalLP4_DDR2667(DRAMC_CTX_T * p)3079 static void LegacyPreCalLP4_DDR2667(DRAMC_CTX_T *p)
3080 {
3081 vIO32WriteFldMulti(DRAMC_REG_PRE_TDQSCK2, P_Fld(0x1a, PRE_TDQSCK2_TDDQSCK_JUMP_RATIO0)
3082 | P_Fld(0x10, PRE_TDQSCK2_TDDQSCK_JUMP_RATIO1)
3083 | P_Fld(0x0, PRE_TDQSCK2_TDDQSCK_JUMP_RATIO2)
3084 | P_Fld(0x26, PRE_TDQSCK2_TDDQSCK_JUMP_RATIO3));
3085 vIO32WriteFldMulti(DRAMC_REG_PRE_TDQSCK3, P_Fld(0x13, PRE_TDQSCK3_TDDQSCK_JUMP_RATIO4)
3086 | P_Fld(0x0, PRE_TDQSCK3_TDDQSCK_JUMP_RATIO5)
3087 | P_Fld(0x40, PRE_TDQSCK3_TDDQSCK_JUMP_RATIO6)
3088 | P_Fld(0x35, PRE_TDQSCK3_TDDQSCK_JUMP_RATIO7));
3089 vIO32WriteFldMulti(DRAMC_REG_PRE_TDQSCK4, P_Fld(0x0, PRE_TDQSCK4_TDDQSCK_JUMP_RATIO8)
3090 | P_Fld(0x0, PRE_TDQSCK4_TDDQSCK_JUMP_RATIO9)
3091 | P_Fld(0x0, PRE_TDQSCK4_TDDQSCK_JUMP_RATIO10)
3092 | P_Fld(0x0, PRE_TDQSCK4_TDDQSCK_JUMP_RATIO11));
3093 vIO32WriteFldAlign(DRAMC_REG_RK0_PRE_TDQSCK1, 0xa, RK0_PRE_TDQSCK1_TDQSCK_UIFREQ2_B0R0);
3094 vIO32WriteFldMulti(DRAMC_REG_RK0_PRE_TDQSCK2, P_Fld(0x0, RK0_PRE_TDQSCK2_TDQSCK_PIFREQ4_B0R0)
3095 | P_Fld(0x0, RK0_PRE_TDQSCK2_TDQSCK_UIFREQ4_B0R0)
3096 | P_Fld(0xb, RK0_PRE_TDQSCK2_TDQSCK_PIFREQ3_B0R0)
3097 | P_Fld(0xd, RK0_PRE_TDQSCK2_TDQSCK_UIFREQ3_B0R0));
3098 vIO32WriteFldMulti(DRAMC_REG_RK0_PRE_TDQSCK3, P_Fld(0x0, RK0_PRE_TDQSCK3_TDQSCK_UIFREQ4_P1_B0R0)
3099 | P_Fld(0x11, RK0_PRE_TDQSCK3_TDQSCK_UIFREQ3_P1_B0R0)
3100 | P_Fld(0xe, RK0_PRE_TDQSCK3_TDQSCK_UIFREQ2_P1_B0R0));
3101 vIO32WriteFldAlign(DRAMC_REG_RK0_PRE_TDQSCK4, 0xa, RK0_PRE_TDQSCK4_TDQSCK_UIFREQ2_B1R0);
3102 vIO32WriteFldMulti(DRAMC_REG_RK0_PRE_TDQSCK5, P_Fld(0x0, RK0_PRE_TDQSCK5_TDQSCK_PIFREQ4_B1R0)
3103 | P_Fld(0x0, RK0_PRE_TDQSCK5_TDQSCK_UIFREQ4_B1R0)
3104 | P_Fld(0xb, RK0_PRE_TDQSCK5_TDQSCK_PIFREQ3_B1R0)
3105 | P_Fld(0xd, RK0_PRE_TDQSCK5_TDQSCK_UIFREQ3_B1R0));
3106 vIO32WriteFldMulti(DRAMC_REG_RK0_PRE_TDQSCK6, P_Fld(0x0, RK0_PRE_TDQSCK6_TDQSCK_UIFREQ4_P1_B1R0)
3107 | P_Fld(0x11, RK0_PRE_TDQSCK6_TDQSCK_UIFREQ3_P1_B1R0)
3108 | P_Fld(0xe, RK0_PRE_TDQSCK6_TDQSCK_UIFREQ2_P1_B1R0));
3109 vIO32WriteFldMulti(DRAMC_REG_RK1_PRE_TDQSCK1, P_Fld(0x8, RK1_PRE_TDQSCK1_TDQSCK_PIFREQ2_B0R1)
3110 | P_Fld(0x10, RK1_PRE_TDQSCK1_TDQSCK_UIFREQ2_B0R1));
3111 vIO32WriteFldMulti(DRAMC_REG_RK1_PRE_TDQSCK2, P_Fld(0x0, RK1_PRE_TDQSCK2_TDQSCK_PIFREQ4_B0R1)
3112 | P_Fld(0x0, RK1_PRE_TDQSCK2_TDQSCK_UIFREQ4_B0R1)
3113 | P_Fld(0xe, RK1_PRE_TDQSCK2_TDQSCK_PIFREQ3_B0R1)
3114 | P_Fld(0x10, RK1_PRE_TDQSCK2_TDQSCK_UIFREQ3_B0R1));
3115 vIO32WriteFldMulti(DRAMC_REG_RK1_PRE_TDQSCK3, P_Fld(0x0, RK1_PRE_TDQSCK3_TDQSCK_UIFREQ4_P1_B0R1)
3116 | P_Fld(0x14, RK1_PRE_TDQSCK3_TDQSCK_UIFREQ3_P1_B0R1)
3117 | P_Fld(0x14, RK1_PRE_TDQSCK3_TDQSCK_UIFREQ2_P1_B0R1));
3118 vIO32WriteFldMulti(DRAMC_REG_RK1_PRE_TDQSCK4, P_Fld(0x8, RK1_PRE_TDQSCK4_TDQSCK_PIFREQ2_B1R1)
3119 | P_Fld(0x10, RK1_PRE_TDQSCK4_TDQSCK_UIFREQ2_B1R1));
3120 vIO32WriteFldMulti(DRAMC_REG_RK1_PRE_TDQSCK5, P_Fld(0x0, RK1_PRE_TDQSCK5_TDQSCK_PIFREQ4_B1R1)
3121 | P_Fld(0x0, RK1_PRE_TDQSCK5_TDQSCK_UIFREQ4_B1R1)
3122 | P_Fld(0xe, RK1_PRE_TDQSCK5_TDQSCK_PIFREQ3_B1R1)
3123 | P_Fld(0x10, RK1_PRE_TDQSCK5_TDQSCK_UIFREQ3_B1R1));
3124 vIO32WriteFldMulti(DRAMC_REG_RK1_PRE_TDQSCK6, P_Fld(0x0, RK1_PRE_TDQSCK6_TDQSCK_UIFREQ4_P1_B1R1)
3125 | P_Fld(0x14, RK1_PRE_TDQSCK6_TDQSCK_UIFREQ3_P1_B1R1)
3126 | P_Fld(0x14, RK1_PRE_TDQSCK6_TDQSCK_UIFREQ2_P1_B1R1));
3127 }
3128
LegacyPreCalLP4_DDR1600(DRAMC_CTX_T * p)3129 static void LegacyPreCalLP4_DDR1600(DRAMC_CTX_T *p)
3130 {
3131 vIO32WriteFldMulti(DRAMC_REG_PRE_TDQSCK2, P_Fld(0x1a, PRE_TDQSCK2_TDDQSCK_JUMP_RATIO0)
3132 | P_Fld(0x10, PRE_TDQSCK2_TDDQSCK_JUMP_RATIO1)
3133 | P_Fld(0x0, PRE_TDQSCK2_TDDQSCK_JUMP_RATIO2)
3134 | P_Fld(0x26, PRE_TDQSCK2_TDDQSCK_JUMP_RATIO3));
3135 vIO32WriteFldMulti(DRAMC_REG_PRE_TDQSCK3, P_Fld(0x13, PRE_TDQSCK3_TDDQSCK_JUMP_RATIO4)
3136 | P_Fld(0x0, PRE_TDQSCK3_TDDQSCK_JUMP_RATIO5)
3137 | P_Fld(0x40, PRE_TDQSCK3_TDDQSCK_JUMP_RATIO6)
3138 | P_Fld(0x35, PRE_TDQSCK3_TDDQSCK_JUMP_RATIO7));
3139 vIO32WriteFldMulti(DRAMC_REG_PRE_TDQSCK4, P_Fld(0x0, PRE_TDQSCK4_TDDQSCK_JUMP_RATIO8)
3140 | P_Fld(0x0, PRE_TDQSCK4_TDDQSCK_JUMP_RATIO9)
3141 | P_Fld(0x0, PRE_TDQSCK4_TDDQSCK_JUMP_RATIO10)
3142 | P_Fld(0x0, PRE_TDQSCK4_TDDQSCK_JUMP_RATIO11));
3143 vIO32WriteFldAlign(DRAMC_REG_RK0_PRE_TDQSCK1, 0xa, RK0_PRE_TDQSCK1_TDQSCK_UIFREQ2_B0R0);
3144 vIO32WriteFldMulti(DRAMC_REG_RK0_PRE_TDQSCK2, P_Fld(0x0, RK0_PRE_TDQSCK2_TDQSCK_PIFREQ4_B0R0)
3145 | P_Fld(0x0, RK0_PRE_TDQSCK2_TDQSCK_UIFREQ4_B0R0)
3146 | P_Fld(0xb, RK0_PRE_TDQSCK2_TDQSCK_PIFREQ3_B0R0)
3147 | P_Fld(0xd, RK0_PRE_TDQSCK2_TDQSCK_UIFREQ3_B0R0));
3148 vIO32WriteFldMulti(DRAMC_REG_RK0_PRE_TDQSCK3, P_Fld(0x0, RK0_PRE_TDQSCK3_TDQSCK_UIFREQ4_P1_B0R0)
3149 | P_Fld(0x11, RK0_PRE_TDQSCK3_TDQSCK_UIFREQ3_P1_B0R0)
3150 | P_Fld(0xe, RK0_PRE_TDQSCK3_TDQSCK_UIFREQ2_P1_B0R0));
3151 vIO32WriteFldAlign(DRAMC_REG_RK0_PRE_TDQSCK4, 0xa, RK0_PRE_TDQSCK4_TDQSCK_UIFREQ2_B1R0);
3152 vIO32WriteFldMulti(DRAMC_REG_RK0_PRE_TDQSCK5, P_Fld(0x0, RK0_PRE_TDQSCK5_TDQSCK_PIFREQ4_B1R0)
3153 | P_Fld(0x0, RK0_PRE_TDQSCK5_TDQSCK_UIFREQ4_B1R0)
3154 | P_Fld(0xb, RK0_PRE_TDQSCK5_TDQSCK_PIFREQ3_B1R0)
3155 | P_Fld(0xd, RK0_PRE_TDQSCK5_TDQSCK_UIFREQ3_B1R0));
3156 vIO32WriteFldMulti(DRAMC_REG_RK0_PRE_TDQSCK6, P_Fld(0x0, RK0_PRE_TDQSCK6_TDQSCK_UIFREQ4_P1_B1R0)
3157 | P_Fld(0x11, RK0_PRE_TDQSCK6_TDQSCK_UIFREQ3_P1_B1R0)
3158 | P_Fld(0xe, RK0_PRE_TDQSCK6_TDQSCK_UIFREQ2_P1_B1R0));
3159 vIO32WriteFldMulti(DRAMC_REG_RK1_PRE_TDQSCK1, P_Fld(0x8, RK1_PRE_TDQSCK1_TDQSCK_PIFREQ2_B0R1)
3160 | P_Fld(0x10, RK1_PRE_TDQSCK1_TDQSCK_UIFREQ2_B0R1));
3161 vIO32WriteFldMulti(DRAMC_REG_RK1_PRE_TDQSCK2, P_Fld(0x0, RK1_PRE_TDQSCK2_TDQSCK_PIFREQ4_B0R1)
3162 | P_Fld(0x0, RK1_PRE_TDQSCK2_TDQSCK_UIFREQ4_B0R1)
3163 | P_Fld(0xe, RK1_PRE_TDQSCK2_TDQSCK_PIFREQ3_B0R1)
3164 | P_Fld(0x10, RK1_PRE_TDQSCK2_TDQSCK_UIFREQ3_B0R1));
3165 vIO32WriteFldMulti(DRAMC_REG_RK1_PRE_TDQSCK3, P_Fld(0x0, RK1_PRE_TDQSCK3_TDQSCK_UIFREQ4_P1_B0R1)
3166 | P_Fld(0x14, RK1_PRE_TDQSCK3_TDQSCK_UIFREQ3_P1_B0R1)
3167 | P_Fld(0x14, RK1_PRE_TDQSCK3_TDQSCK_UIFREQ2_P1_B0R1));
3168 vIO32WriteFldMulti(DRAMC_REG_RK1_PRE_TDQSCK4, P_Fld(0x8, RK1_PRE_TDQSCK4_TDQSCK_PIFREQ2_B1R1)
3169 | P_Fld(0x10, RK1_PRE_TDQSCK4_TDQSCK_UIFREQ2_B1R1));
3170 vIO32WriteFldMulti(DRAMC_REG_RK1_PRE_TDQSCK5, P_Fld(0x0, RK1_PRE_TDQSCK5_TDQSCK_PIFREQ4_B1R1)
3171 | P_Fld(0x0, RK1_PRE_TDQSCK5_TDQSCK_UIFREQ4_B1R1)
3172 | P_Fld(0xe, RK1_PRE_TDQSCK5_TDQSCK_PIFREQ3_B1R1)
3173 | P_Fld(0x10, RK1_PRE_TDQSCK5_TDQSCK_UIFREQ3_B1R1));
3174 vIO32WriteFldMulti(DRAMC_REG_RK1_PRE_TDQSCK6, P_Fld(0x0, RK1_PRE_TDQSCK6_TDQSCK_UIFREQ4_P1_B1R1)
3175 | P_Fld(0x14, RK1_PRE_TDQSCK6_TDQSCK_UIFREQ3_P1_B1R1)
3176 | P_Fld(0x14, RK1_PRE_TDQSCK6_TDQSCK_UIFREQ2_P1_B1R1));
3177 }
3178
LegacyPreCalLP4_DDR3200(DRAMC_CTX_T * p)3179 static void LegacyPreCalLP4_DDR3200(DRAMC_CTX_T *p)
3180 {
3181 vIO32WriteFldMulti(DRAMC_REG_PRE_TDQSCK2, P_Fld(0x25, PRE_TDQSCK2_TDDQSCK_JUMP_RATIO0)
3182 | P_Fld(0x18, PRE_TDQSCK2_TDDQSCK_JUMP_RATIO1)
3183 | P_Fld(0x10, PRE_TDQSCK2_TDDQSCK_JUMP_RATIO2)
3184 | P_Fld(0x1b, PRE_TDQSCK2_TDDQSCK_JUMP_RATIO3));
3185 vIO32WriteFldMulti(DRAMC_REG_PRE_TDQSCK3, P_Fld(0x14, PRE_TDQSCK3_TDDQSCK_JUMP_RATIO4)
3186 | P_Fld(0xd, PRE_TDQSCK3_TDDQSCK_JUMP_RATIO5)
3187 | P_Fld(0x2a, PRE_TDQSCK3_TDDQSCK_JUMP_RATIO6)
3188 | P_Fld(0x31, PRE_TDQSCK3_TDDQSCK_JUMP_RATIO7));
3189 vIO32WriteFldMulti(DRAMC_REG_PRE_TDQSCK4, P_Fld(0x15, PRE_TDQSCK4_TDDQSCK_JUMP_RATIO8)
3190 | P_Fld(0x40, PRE_TDQSCK4_TDDQSCK_JUMP_RATIO9)
3191 | P_Fld(0x4a, PRE_TDQSCK4_TDDQSCK_JUMP_RATIO10)
3192 | P_Fld(0x30, PRE_TDQSCK4_TDDQSCK_JUMP_RATIO11));
3193 vIO32WriteFldMulti(DRAMC_REG_RK0_PRE_TDQSCK1, P_Fld(0x1a, RK0_PRE_TDQSCK1_TDQSCK_PIFREQ2_B0R0)
3194 | P_Fld(0x1c, RK0_PRE_TDQSCK1_TDQSCK_UIFREQ2_B0R0)
3195 | P_Fld(0x14, RK0_PRE_TDQSCK1_TDQSCK_UIFREQ1_B0R0));
3196 vIO32WriteFldMulti(DRAMC_REG_RK0_PRE_TDQSCK2, P_Fld(0xb, RK0_PRE_TDQSCK2_TDQSCK_PIFREQ4_B0R0)
3197 | P_Fld(0xd, RK0_PRE_TDQSCK2_TDQSCK_UIFREQ4_B0R0)
3198 | P_Fld(0x10, RK0_PRE_TDQSCK2_TDQSCK_PIFREQ3_B0R0)
3199 | P_Fld(0xa, RK0_PRE_TDQSCK2_TDQSCK_UIFREQ3_B0R0));
3200 vIO32WriteFldMulti(DRAMC_REG_RK0_PRE_TDQSCK3, P_Fld(0x11, RK0_PRE_TDQSCK3_TDQSCK_UIFREQ4_P1_B0R0)
3201 | P_Fld(0xe, RK0_PRE_TDQSCK3_TDQSCK_UIFREQ3_P1_B0R0)
3202 | P_Fld(0x20, RK0_PRE_TDQSCK3_TDQSCK_UIFREQ2_P1_B0R0)
3203 | P_Fld(0x18, RK0_PRE_TDQSCK3_TDQSCK_UIFREQ1_P1_B0R0));
3204 vIO32WriteFldMulti(DRAMC_REG_RK0_PRE_TDQSCK4, P_Fld(0x1a, RK0_PRE_TDQSCK4_TDQSCK_PIFREQ2_B1R0)
3205 | P_Fld(0x1c, RK0_PRE_TDQSCK4_TDQSCK_UIFREQ2_B1R0)
3206 | P_Fld(0x14, RK0_PRE_TDQSCK4_TDQSCK_UIFREQ1_B1R0));
3207 vIO32WriteFldMulti(DRAMC_REG_RK0_PRE_TDQSCK5, P_Fld(0xb, RK0_PRE_TDQSCK5_TDQSCK_PIFREQ4_B1R0)
3208 | P_Fld(0xd, RK0_PRE_TDQSCK5_TDQSCK_UIFREQ4_B1R0)
3209 | P_Fld(0x10, RK0_PRE_TDQSCK5_TDQSCK_PIFREQ3_B1R0)
3210 | P_Fld(0xa, RK0_PRE_TDQSCK5_TDQSCK_UIFREQ3_B1R0));
3211 vIO32WriteFldMulti(DRAMC_REG_RK0_PRE_TDQSCK6, P_Fld(0x11, RK0_PRE_TDQSCK6_TDQSCK_UIFREQ4_P1_B1R0)
3212 | P_Fld(0xe, RK0_PRE_TDQSCK6_TDQSCK_UIFREQ3_P1_B1R0)
3213 | P_Fld(0x20, RK0_PRE_TDQSCK6_TDQSCK_UIFREQ2_P1_B1R0)
3214 | P_Fld(0x18, RK0_PRE_TDQSCK6_TDQSCK_UIFREQ1_P1_B1R0));
3215 vIO32WriteFldMulti(DRAMC_REG_RK1_PRE_TDQSCK1, P_Fld(0xb, RK1_PRE_TDQSCK1_TDQSCK_PIFREQ2_B0R1)
3216 | P_Fld(0x23, RK1_PRE_TDQSCK1_TDQSCK_UIFREQ2_B0R1)
3217 | P_Fld(0xf, RK1_PRE_TDQSCK1_TDQSCK_PIFREQ1_B0R1)
3218 | P_Fld(0x19, RK1_PRE_TDQSCK1_TDQSCK_UIFREQ1_B0R1));
3219 vIO32WriteFldMulti(DRAMC_REG_RK1_PRE_TDQSCK2, P_Fld(0xe, RK1_PRE_TDQSCK2_TDQSCK_PIFREQ4_B0R1)
3220 | P_Fld(0x10, RK1_PRE_TDQSCK2_TDQSCK_UIFREQ4_B0R1)
3221 | P_Fld(0x1f, RK1_PRE_TDQSCK2_TDQSCK_PIFREQ3_B0R1)
3222 | P_Fld(0xe, RK1_PRE_TDQSCK2_TDQSCK_UIFREQ3_B0R1));
3223 vIO32WriteFldMulti(DRAMC_REG_RK1_PRE_TDQSCK3, P_Fld(0x14, RK1_PRE_TDQSCK3_TDQSCK_UIFREQ4_P1_B0R1)
3224 | P_Fld(0x12, RK1_PRE_TDQSCK3_TDQSCK_UIFREQ3_P1_B0R1)
3225 | P_Fld(0x27, RK1_PRE_TDQSCK3_TDQSCK_UIFREQ2_P1_B0R1)
3226 | P_Fld(0x1d, RK1_PRE_TDQSCK3_TDQSCK_UIFREQ1_P1_B0R1));
3227 vIO32WriteFldMulti(DRAMC_REG_RK1_PRE_TDQSCK4, P_Fld(0xb, RK1_PRE_TDQSCK4_TDQSCK_PIFREQ2_B1R1)
3228 | P_Fld(0x23, RK1_PRE_TDQSCK4_TDQSCK_UIFREQ2_B1R1)
3229 | P_Fld(0xf, RK1_PRE_TDQSCK4_TDQSCK_PIFREQ1_B1R1)
3230 | P_Fld(0x19, RK1_PRE_TDQSCK4_TDQSCK_UIFREQ1_B1R1));
3231 vIO32WriteFldMulti(DRAMC_REG_RK1_PRE_TDQSCK5, P_Fld(0xe, RK1_PRE_TDQSCK5_TDQSCK_PIFREQ4_B1R1)
3232 | P_Fld(0x10, RK1_PRE_TDQSCK5_TDQSCK_UIFREQ4_B1R1)
3233 | P_Fld(0x1f, RK1_PRE_TDQSCK5_TDQSCK_PIFREQ3_B1R1)
3234 | P_Fld(0xe, RK1_PRE_TDQSCK5_TDQSCK_UIFREQ3_B1R1));
3235 vIO32WriteFldMulti(DRAMC_REG_RK1_PRE_TDQSCK6, P_Fld(0x14, RK1_PRE_TDQSCK6_TDQSCK_UIFREQ4_P1_B1R1)
3236 | P_Fld(0x12, RK1_PRE_TDQSCK6_TDQSCK_UIFREQ3_P1_B1R1)
3237 | P_Fld(0x27, RK1_PRE_TDQSCK6_TDQSCK_UIFREQ2_P1_B1R1)
3238 | P_Fld(0x1d, RK1_PRE_TDQSCK6_TDQSCK_UIFREQ1_P1_B1R1));
3239 }
3240 #endif
3241
3242 #if LEGACY_GATING_DLY
3243
LegacyGatingDlyLP3(DRAMC_CTX_T * p)3244 static void LegacyGatingDlyLP3(DRAMC_CTX_T *p)
3245 {
3246 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_ODTEN0, P_Fld(0x0, SHURK0_SELPH_ODTEN0_TXDLY_B3_RODTEN_P1)
3247 | P_Fld(0x0, SHURK0_SELPH_ODTEN0_TXDLY_B3_RODTEN)
3248 | P_Fld(0x0, SHURK0_SELPH_ODTEN0_TXDLY_B2_RODTEN_P1)
3249 | P_Fld(0x0, SHURK0_SELPH_ODTEN0_TXDLY_B2_RODTEN)
3250 | P_Fld(0x0, SHURK0_SELPH_ODTEN0_TXDLY_B1_RODTEN_P1)
3251 | P_Fld(0x0, SHURK0_SELPH_ODTEN0_TXDLY_B1_RODTEN)
3252 | P_Fld(0x0, SHURK0_SELPH_ODTEN0_TXDLY_B0_RODTEN_P1)
3253 | P_Fld(0x0, SHURK0_SELPH_ODTEN0_TXDLY_B0_RODTEN));
3254 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_ODTEN1, P_Fld(0x4, SHURK0_SELPH_ODTEN1_DLY_B3_RODTEN_P1)
3255 | P_Fld(0x4, SHURK0_SELPH_ODTEN1_DLY_B3_RODTEN)
3256 | P_Fld(0x4, SHURK0_SELPH_ODTEN1_DLY_B2_RODTEN_P1)
3257 | P_Fld(0x4, SHURK0_SELPH_ODTEN1_DLY_B2_RODTEN)
3258 | P_Fld(0x4, SHURK0_SELPH_ODTEN1_DLY_B1_RODTEN_P1)
3259 | P_Fld(0x4, SHURK0_SELPH_ODTEN1_DLY_B1_RODTEN)
3260 | P_Fld(0x4, SHURK0_SELPH_ODTEN1_DLY_B0_RODTEN_P1)
3261 | P_Fld(0x4, SHURK0_SELPH_ODTEN1_DLY_B0_RODTEN));
3262 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_ODTEN0, P_Fld(0x0, SHURK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN_P1)
3263 | P_Fld(0x0, SHURK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN)
3264 | P_Fld(0x0, SHURK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN_P1)
3265 | P_Fld(0x0, SHURK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN)
3266 | P_Fld(0x0, SHURK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN_P1)
3267 | P_Fld(0x0, SHURK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN)
3268 | P_Fld(0x0, SHURK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN_P1)
3269 | P_Fld(0x0, SHURK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN));
3270 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_ODTEN1, P_Fld(0x0, SHURK1_SELPH_ODTEN1_DLY_B3_R1RODTEN_P1)
3271 | P_Fld(0x0, SHURK1_SELPH_ODTEN1_DLY_B3_R1RODTEN)
3272 | P_Fld(0x4, SHURK1_SELPH_ODTEN1_DLY_B2_R1RODTEN_P1)
3273 | P_Fld(0x4, SHURK1_SELPH_ODTEN1_DLY_B2_R1RODTEN)
3274 | P_Fld(0x4, SHURK1_SELPH_ODTEN1_DLY_B1_R1RODTEN_P1)
3275 | P_Fld(0x4, SHURK1_SELPH_ODTEN1_DLY_B1_R1RODTEN)
3276 | P_Fld(0x4, SHURK1_SELPH_ODTEN1_DLY_B0_R1RODTEN_P1)
3277 | P_Fld(0x4, SHURK1_SELPH_ODTEN1_DLY_B0_R1RODTEN));
3278 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG0, P_Fld(0x1, SHURK0_SELPH_DQSG0_TX_DLY_DQS3_GATED_P1)
3279 | P_Fld(0x1, SHURK0_SELPH_DQSG0_TX_DLY_DQS3_GATED)
3280 | P_Fld(0x1, SHURK0_SELPH_DQSG0_TX_DLY_DQS2_GATED_P1)
3281 | P_Fld(0x1, SHURK0_SELPH_DQSG0_TX_DLY_DQS2_GATED)
3282 | P_Fld(0x1, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1)
3283 | P_Fld(0x1, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED)
3284 | P_Fld(0x1, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1)
3285 | P_Fld(0x1, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED));
3286 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG1, P_Fld(0x4, SHURK0_SELPH_DQSG1_REG_DLY_DQS3_GATED_P1)
3287 | P_Fld(0x2, SHURK0_SELPH_DQSG1_REG_DLY_DQS3_GATED)
3288 | P_Fld(0x4, SHURK0_SELPH_DQSG1_REG_DLY_DQS2_GATED_P1)
3289 | P_Fld(0x2, SHURK0_SELPH_DQSG1_REG_DLY_DQS2_GATED)
3290 | P_Fld(0x4, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1)
3291 | P_Fld(0x2, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED)
3292 | P_Fld(0x4, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1)
3293 | P_Fld(0x2, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED));
3294 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG0, P_Fld(0x2, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS3_GATED_P1)
3295 | P_Fld(0x1, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS3_GATED)
3296 | P_Fld(0x2, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS2_GATED_P1)
3297 | P_Fld(0x1, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS2_GATED)
3298 | P_Fld(0x2, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED_P1)
3299 | P_Fld(0x1, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED)
3300 | P_Fld(0x2, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED_P1)
3301 | P_Fld(0x1, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED));
3302 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG1, P_Fld(0x1, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS3_GATED_P1)
3303 | P_Fld(0x7, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS3_GATED)
3304 | P_Fld(0x1, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS2_GATED_P1)
3305 | P_Fld(0x7, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS2_GATED)
3306 | P_Fld(0x1, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED_P1)
3307 | P_Fld(0x7, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED)
3308 | P_Fld(0x1, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED_P1)
3309 | P_Fld(0x7, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED));
3310 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG0 + SHIFT_TO_CHB_ADDR, P_Fld(0x1, SHURK0_SELPH_DQSG0_TX_DLY_DQS3_GATED_P1)
3311 | P_Fld(0x1, SHURK0_SELPH_DQSG0_TX_DLY_DQS3_GATED)
3312 | P_Fld(0x1, SHURK0_SELPH_DQSG0_TX_DLY_DQS2_GATED_P1)
3313 | P_Fld(0x1, SHURK0_SELPH_DQSG0_TX_DLY_DQS2_GATED)
3314 | P_Fld(0x1, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1)
3315 | P_Fld(0x1, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED)
3316 | P_Fld(0x1, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1)
3317 | P_Fld(0x1, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED));
3318 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG1 + SHIFT_TO_CHB_ADDR, P_Fld(0x3, SHURK0_SELPH_DQSG1_REG_DLY_DQS3_GATED_P1)
3319 | P_Fld(0x1, SHURK0_SELPH_DQSG1_REG_DLY_DQS3_GATED)
3320 | P_Fld(0x3, SHURK0_SELPH_DQSG1_REG_DLY_DQS2_GATED_P1)
3321 | P_Fld(0x1, SHURK0_SELPH_DQSG1_REG_DLY_DQS2_GATED)
3322 | P_Fld(0x3, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1)
3323 | P_Fld(0x1, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED)
3324 | P_Fld(0x3, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1)
3325 | P_Fld(0x1, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED));
3326 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG0 + SHIFT_TO_CHB_ADDR, P_Fld(0x2, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS3_GATED_P1)
3327 | P_Fld(0x1, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS3_GATED)
3328 | P_Fld(0x2, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS2_GATED_P1)
3329 | P_Fld(0x1, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS2_GATED)
3330 | P_Fld(0x2, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED_P1)
3331 | P_Fld(0x1, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED)
3332 | P_Fld(0x2, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED_P1)
3333 | P_Fld(0x1, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED));
3334 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG1 + SHIFT_TO_CHB_ADDR, P_Fld(0x1, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS3_GATED_P1)
3335 | P_Fld(0x7, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS3_GATED)
3336 | P_Fld(0x1, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS2_GATED_P1)
3337 | P_Fld(0x7, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS2_GATED)
3338 | P_Fld(0x1, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED_P1)
3339 | P_Fld(0x7, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED)
3340 | P_Fld(0x1, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED_P1)
3341 | P_Fld(0x7, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED));
3342 }
3343
LegacyGatingDlyLP4_DDR800(DRAMC_CTX_T * p)3344 static void LegacyGatingDlyLP4_DDR800(DRAMC_CTX_T *p)
3345 {
3346
3347 U8 ucR0GatingMCK = 0, ucR0GatingB0UI = 0, ucR0GatingB1UI = 0;
3348 U8 ucR0GatingP1MCK = 0, ucR0GatingB0P1UI = 0, ucR0GatingB1P1UI = 0;
3349
3350 U8 ucR1GatingMCK = 0, ucR1GatingB0UI = 0, ucR1GatingB1UI = 0;
3351 U8 ucR1GatingP1MCK = 0, ucR1GatingB0P1UI = 0, ucR1GatingB1P1UI = 0;
3352
3353 U8 ucR0GatingB0PI = 0, ucR0GatingB1PI = 0;
3354 U8 ucR1GatingB0PI = 0, ucR1GatingB1PI = 0;
3355
3356 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
3357 {
3358
3359 ucR0GatingMCK = 0x2;
3360 ucR0GatingP1MCK = 0x2;
3361 ucR0GatingB0UI = 0x2;
3362 ucR0GatingB1UI = 0x2;
3363 ucR0GatingB0P1UI = 0x6;
3364 ucR0GatingB1P1UI = 0x6;
3365
3366 ucR1GatingMCK = 0x2;
3367 ucR1GatingP1MCK = 0x3;
3368 ucR1GatingB0UI = 0x5;
3369 ucR1GatingB1UI = 0x5;
3370 ucR1GatingB0P1UI = 0x1;
3371 ucR1GatingB1P1UI = 0x1;
3372 }
3373 else
3374 {
3375
3376 ucR0GatingMCK = 0x1;
3377 ucR0GatingP1MCK = 0x1;
3378 ucR0GatingB0UI = 0x4;
3379 ucR0GatingB1UI = 0x4;
3380 ucR0GatingB0P1UI = 0x6;
3381 ucR0GatingB1P1UI = 0x6;
3382
3383 ucR1GatingMCK = 0x1;
3384 ucR1GatingP1MCK = 0x1;
3385 ucR1GatingB0UI = 0x5;
3386 ucR1GatingB1UI = 0x5;
3387 ucR1GatingB0P1UI = 0x7;
3388 ucR1GatingB1P1UI = 0x7;
3389 }
3390
3391
3392 if (vGet_DDR800_Mode(p) == DDR800_CLOSE_LOOP)
3393 {
3394 ucR0GatingB0PI = 0xc;
3395 ucR0GatingB1PI = 0xe;
3396 ucR1GatingB0PI = 0x1e;
3397 ucR1GatingB1PI = 0x1e;
3398 }
3399 else
3400 {
3401
3402 ucR0GatingB0PI = 0x0;
3403 ucR0GatingB1PI = 0x0;
3404 ucR1GatingB0PI = 0x0;
3405 ucR1GatingB1PI = 0x0;
3406 }
3407
3408
3409 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG0, P_Fld(ucR0GatingP1MCK, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1)
3410 | P_Fld(ucR0GatingMCK, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED)
3411 | P_Fld(ucR0GatingP1MCK, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1)
3412 | P_Fld(ucR0GatingMCK, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED));
3413
3414 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG1, P_Fld(ucR0GatingB1P1UI, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1)
3415 | P_Fld(ucR0GatingB1UI, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED)
3416 | P_Fld(ucR0GatingB0P1UI, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1)
3417 | P_Fld(ucR0GatingB0UI, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED));
3418
3419
3420 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG0, P_Fld(ucR1GatingP1MCK, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED_P1)
3421 | P_Fld(ucR1GatingMCK, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED)
3422 | P_Fld(ucR1GatingP1MCK, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED_P1)
3423 | P_Fld(ucR1GatingMCK, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED));
3424
3425 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG1, P_Fld(ucR1GatingB1P1UI, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED_P1)
3426 | P_Fld(ucR1GatingB1UI, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED)
3427 | P_Fld(ucR1GatingB0P1UI, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED_P1)
3428 | P_Fld(ucR1GatingB0UI, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED));
3429
3430
3431 vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQSIEN, P_Fld(ucR0GatingB1PI, SHURK0_DQSIEN_R0DQS1IEN)
3432 | P_Fld(ucR0GatingB0PI, SHURK0_DQSIEN_R0DQS0IEN));
3433
3434 vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQSIEN, P_Fld(ucR1GatingB1PI, SHURK1_DQSIEN_R1DQS1IEN)
3435 | P_Fld(ucR1GatingB0PI, SHURK1_DQSIEN_R1DQS0IEN));
3436 }
3437
3438
LegacyGatingDlyLP4_DDR1600(DRAMC_CTX_T * p)3439 static void LegacyGatingDlyLP4_DDR1600(DRAMC_CTX_T *p)
3440 {
3441 U8 ucR0GatingMCK = 0, ucR0GatingB0UI = 0, ucR0GatingB1UI = 0;
3442 U8 ucR0GatingP1MCK = 0, ucR0GatingB0P1UI = 0, ucR0GatingB1P1UI = 0;
3443
3444 U8 ucR1GatingMCK = 0, ucR1GatingB0UI = 0, ucR1GatingB1UI = 0;
3445 U8 ucR1GatingP1MCK = 0, ucR1GatingB0P1UI = 0, ucR1GatingB1P1UI = 0;
3446
3447 U8 ucR0GatingB0PI = 0, ucR0GatingB1PI = 0;
3448 U8 ucR1GatingB0PI = 0, ucR1GatingB1PI = 0;
3449
3450 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
3451 {
3452
3453 if ((p->dram_cbt_mode[RANK_0] == CBT_BYTE_MODE1) && (p->dram_cbt_mode[RANK_1] == CBT_NORMAL_MODE))
3454 {
3455
3456 ucR0GatingMCK = 0x2;
3457 ucR0GatingP1MCK = 0x2;
3458 ucR0GatingB0UI = 0x0;
3459 ucR0GatingB1UI = 0x0;
3460 ucR0GatingB0P1UI = 0x4;
3461 ucR0GatingB1P1UI = 0x4;
3462
3463 ucR1GatingMCK = 0x2;
3464 ucR1GatingP1MCK = 0x2;
3465 ucR1GatingB0UI = 0x3;
3466 ucR1GatingB1UI = 0x2;
3467 ucR1GatingB0P1UI = 0x7;
3468 ucR1GatingB1P1UI = 0x6;
3469 }
3470 else
3471 {
3472
3473 ucR0GatingMCK = 0x2;
3474 ucR0GatingP1MCK = 0x2;
3475 ucR0GatingB0UI = 0x0;
3476 ucR0GatingB1UI = 0x1;
3477 ucR0GatingB0P1UI = 0x4;
3478 ucR0GatingB1P1UI = 0x5;
3479
3480 ucR1GatingMCK = 0x1;
3481 ucR1GatingP1MCK = 0x2;
3482 ucR1GatingB0UI = 0x7;
3483 ucR1GatingB1UI = 0x7;
3484 ucR1GatingB0P1UI = 0x3;
3485 ucR1GatingB1P1UI = 0x3;
3486 }
3487 }
3488 else
3489 {
3490
3491 if (vGet_Div_Mode(p) == DIV4_MODE)
3492 {
3493
3494 ucR0GatingMCK = 0x1;
3495 ucR0GatingP1MCK = 0x1;
3496 ucR0GatingB0UI = 0x4;
3497 ucR0GatingB1UI = 0x4;
3498 ucR0GatingB0P1UI = 0x6;
3499 ucR0GatingB1P1UI = 0x6;
3500
3501 ucR1GatingMCK = 0x1;
3502 ucR1GatingP1MCK = 0x2;
3503 ucR1GatingB0UI = 0x7;
3504 ucR1GatingB1UI = 0x7;
3505 ucR1GatingB0P1UI = 0x1;
3506 ucR1GatingB1P1UI = 0x1;
3507 }
3508 else
3509 {
3510
3511 ucR0GatingMCK = 0x2;
3512 ucR0GatingP1MCK = 0x3;
3513 ucR0GatingB0UI = 0x4;
3514 ucR0GatingB1UI = 0x4;
3515 ucR0GatingB0P1UI = 0x0;
3516 ucR0GatingB1P1UI = 0x0;
3517
3518 ucR1GatingMCK = 0x2;
3519 ucR1GatingP1MCK = 0x3;
3520 ucR1GatingB0UI = 0x7;
3521 ucR1GatingB1UI = 0x7;
3522 ucR1GatingB0P1UI = 0x3;
3523 ucR1GatingB1P1UI = 0x3;
3524 }
3525 }
3526
3527
3528 if (vGet_Div_Mode(p) == DIV4_MODE)
3529 {
3530 ucR0GatingB0PI = 0xb;
3531 ucR0GatingB1PI = 0x0;
3532 ucR1GatingB0PI = 0x1;
3533 ucR1GatingB1PI = 0x1;
3534 }
3535 else
3536 {
3537
3538 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
3539 {
3540 if ((p->dram_cbt_mode[RANK_0] == CBT_BYTE_MODE1) && (p->dram_cbt_mode[RANK_1] == CBT_BYTE_MODE1))
3541 {
3542 ucR0GatingB0PI = 0xa;
3543 ucR0GatingB1PI = 0x0;
3544 ucR1GatingB0PI = 0xc;
3545 ucR1GatingB1PI = 0x16;
3546 }
3547 else if ((p->dram_cbt_mode[RANK_0] == CBT_BYTE_MODE1) && (p->dram_cbt_mode[RANK_1] == CBT_NORMAL_MODE))
3548 {
3549 ucR0GatingB0PI = 0xa;
3550 ucR0GatingB1PI = 0x1e;
3551 ucR1GatingB0PI = 0xc;
3552 ucR1GatingB1PI = 0xc;
3553 }
3554 else
3555 {
3556 ucR0GatingB0PI = 0xa;
3557 ucR0GatingB1PI = 0x0;
3558 ucR1GatingB0PI = 0xc;
3559 ucR1GatingB1PI = 0xc;
3560
3561 }
3562 }
3563 else
3564 {
3565 ucR0GatingB0PI = 0x0;
3566 ucR0GatingB1PI = 0x0;
3567 ucR1GatingB0PI = 0x0;
3568 ucR1GatingB1PI = 0x0;
3569 }
3570 }
3571
3572
3573 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG0, P_Fld(ucR0GatingP1MCK, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1)
3574 | P_Fld(ucR0GatingMCK, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED)
3575 | P_Fld(ucR0GatingP1MCK, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1)
3576 | P_Fld(ucR0GatingMCK, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED));
3577
3578 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG1, P_Fld(ucR0GatingB1P1UI, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1)
3579 | P_Fld(ucR0GatingB1UI, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED)
3580 | P_Fld(ucR0GatingB0P1UI, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1)
3581 | P_Fld(ucR0GatingB0UI, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED));
3582
3583
3584 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG0, P_Fld(ucR1GatingP1MCK, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED_P1)
3585 | P_Fld(ucR1GatingMCK, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED)
3586 | P_Fld(ucR1GatingP1MCK, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED_P1)
3587 | P_Fld(ucR1GatingMCK, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED));
3588
3589 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG1, P_Fld(ucR1GatingB1P1UI, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED_P1)
3590 | P_Fld(ucR1GatingB1UI, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED)
3591 | P_Fld(ucR1GatingB0P1UI, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED_P1)
3592 | P_Fld(ucR1GatingB0UI, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED));
3593
3594
3595 vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQSIEN, P_Fld(ucR0GatingB1PI, SHURK0_DQSIEN_R0DQS1IEN)
3596 | P_Fld(ucR0GatingB0PI, SHURK0_DQSIEN_R0DQS0IEN));
3597
3598 vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQSIEN, P_Fld(ucR1GatingB1PI, SHURK1_DQSIEN_R1DQS1IEN)
3599 | P_Fld(ucR1GatingB0PI, SHURK1_DQSIEN_R1DQS0IEN));
3600 }
3601
LegacyGatingDlyLP4_DDR2667(DRAMC_CTX_T * p)3602 static void LegacyGatingDlyLP4_DDR2667(DRAMC_CTX_T *p)
3603 {
3604 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
3605 {
3606 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_ODTEN0, P_Fld(0x1, SHURK0_SELPH_ODTEN0_TXDLY_B1_RODTEN_P1)
3607 | P_Fld(0x1, SHURK0_SELPH_ODTEN0_TXDLY_B1_RODTEN)
3608 | P_Fld(0x1, SHURK0_SELPH_ODTEN0_TXDLY_B0_RODTEN_P1)
3609 | P_Fld(0x1, SHURK0_SELPH_ODTEN0_TXDLY_B0_RODTEN));
3610 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_ODTEN1, P_Fld(0x1, SHURK0_SELPH_ODTEN1_DLY_B1_RODTEN_P1)
3611 | P_Fld(0x1, SHURK0_SELPH_ODTEN1_DLY_B1_RODTEN)
3612 | P_Fld(0x1, SHURK0_SELPH_ODTEN1_DLY_B0_RODTEN_P1)
3613 | P_Fld(0x1, SHURK0_SELPH_ODTEN1_DLY_B0_RODTEN));
3614 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG0, P_Fld(0x2, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1)
3615 | P_Fld(0x2, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED)
3616 | P_Fld(0x2, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1)
3617 | P_Fld(0x2, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED));
3618 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG1, P_Fld(0x6, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1)
3619 | P_Fld(0x2, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED)
3620 | P_Fld(0x6, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1)
3621 | P_Fld(0x2, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED));
3622 }
3623 else
3624 {
3625 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_ODTEN0, P_Fld(0x2, SHURK0_SELPH_ODTEN0_TXDLY_B1_RODTEN_P1)
3626 | P_Fld(0x2, SHURK0_SELPH_ODTEN0_TXDLY_B1_RODTEN)
3627 | P_Fld(0x2, SHURK0_SELPH_ODTEN0_TXDLY_B0_RODTEN_P1)
3628 | P_Fld(0x2, SHURK0_SELPH_ODTEN0_TXDLY_B0_RODTEN));
3629 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_ODTEN1, P_Fld(0x1, SHURK0_SELPH_ODTEN1_DLY_B1_RODTEN_P1)
3630 | P_Fld(0x1, SHURK0_SELPH_ODTEN1_DLY_B1_RODTEN)
3631 | P_Fld(0x1, SHURK0_SELPH_ODTEN1_DLY_B0_RODTEN_P1)
3632 | P_Fld(0x1, SHURK0_SELPH_ODTEN1_DLY_B0_RODTEN));
3633
3634 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG0, P_Fld(0x3, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1)
3635 | P_Fld(0x3, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED)
3636 | P_Fld(0x3, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1)
3637 | P_Fld(0x3, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED));
3638 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG1, P_Fld(0x4, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1)
3639 | P_Fld(0x0, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED)
3640 | P_Fld(0x4, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1)
3641 | P_Fld(0x0, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED));
3642 }
3643 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
3644 {
3645 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_ODTEN0, P_Fld(0x1, SHURK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN_P1)
3646 | P_Fld(0x1, SHURK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN)
3647 | P_Fld(0x1, SHURK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN_P1)
3648 | P_Fld(0x1, SHURK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN));
3649 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_ODTEN1, P_Fld(0x6, SHURK1_SELPH_ODTEN1_DLY_B1_R1RODTEN_P1)
3650 | P_Fld(0x6, SHURK1_SELPH_ODTEN1_DLY_B1_R1RODTEN)
3651 | P_Fld(0x6, SHURK1_SELPH_ODTEN1_DLY_B0_R1RODTEN_P1)
3652 | P_Fld(0x6, SHURK1_SELPH_ODTEN1_DLY_B0_R1RODTEN));
3653 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG0, P_Fld(0x3, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED_P1)
3654 | P_Fld(0x3, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED)
3655 | P_Fld(0x3, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED_P1)
3656 | P_Fld(0x3, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED));
3657 }
3658 else
3659 {
3660 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_ODTEN0, P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN_P1)
3661 | P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN)
3662 | P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN_P1)
3663 | P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN));
3664 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_ODTEN1, P_Fld(0x6, SHURK1_SELPH_ODTEN1_DLY_B1_R1RODTEN_P1)
3665 | P_Fld(0x6, SHURK1_SELPH_ODTEN1_DLY_B1_R1RODTEN)
3666 | P_Fld(0x6, SHURK1_SELPH_ODTEN1_DLY_B0_R1RODTEN_P1)
3667 | P_Fld(0x6, SHURK1_SELPH_ODTEN1_DLY_B0_R1RODTEN));
3668 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG0, P_Fld(0x4, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED_P1)
3669 | P_Fld(0x3, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED)
3670 | P_Fld(0x4, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED_P1)
3671 | P_Fld(0x3, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED));
3672 }
3673 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG1, P_Fld(0x2, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED_P1)
3674 | P_Fld(0x6, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED)
3675 | P_Fld(0x2, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED_P1)
3676 | P_Fld(0x6, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED));
3677 }
3678
LegacyGatingDlyLP4_DDR3200(DRAMC_CTX_T * p)3679 static void LegacyGatingDlyLP4_DDR3200(DRAMC_CTX_T *p)
3680 {
3681 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
3682 {
3683 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_ODTEN1, P_Fld(0x2, SHURK0_SELPH_ODTEN1_DLY_B3_RODTEN_P1)
3684 | P_Fld(0x2, SHURK0_SELPH_ODTEN1_DLY_B3_RODTEN)
3685 | P_Fld(0x2, SHURK0_SELPH_ODTEN1_DLY_B2_RODTEN_P1)
3686 | P_Fld(0x2, SHURK0_SELPH_ODTEN1_DLY_B2_RODTEN)
3687 | P_Fld(0x6, SHURK0_SELPH_ODTEN1_DLY_B1_RODTEN_P1)
3688 | P_Fld(0x6, SHURK0_SELPH_ODTEN1_DLY_B1_RODTEN)
3689 | P_Fld(0x6, SHURK0_SELPH_ODTEN1_DLY_B0_RODTEN_P1)
3690 | P_Fld(0x6, SHURK0_SELPH_ODTEN1_DLY_B0_RODTEN));
3691 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_ODTEN0, P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN_P1)
3692 | P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN)
3693 | P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN_P1)
3694 | P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN)
3695 | P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN_P1)
3696 | P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN)
3697 | P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN_P1)
3698 | P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN));
3699 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_ODTEN1, P_Fld(0x4, SHURK1_SELPH_ODTEN1_DLY_B3_R1RODTEN_P1)
3700 | P_Fld(0x4, SHURK1_SELPH_ODTEN1_DLY_B3_R1RODTEN)
3701 | P_Fld(0x4, SHURK1_SELPH_ODTEN1_DLY_B2_R1RODTEN_P1)
3702 | P_Fld(0x4, SHURK1_SELPH_ODTEN1_DLY_B2_R1RODTEN)
3703 | P_Fld(0x2, SHURK1_SELPH_ODTEN1_DLY_B1_R1RODTEN_P1)
3704 | P_Fld(0x2, SHURK1_SELPH_ODTEN1_DLY_B1_R1RODTEN)
3705 | P_Fld(0x2, SHURK1_SELPH_ODTEN1_DLY_B0_R1RODTEN_P1)
3706 | P_Fld(0x2, SHURK1_SELPH_ODTEN1_DLY_B0_R1RODTEN));
3707 }
3708 else
3709 {
3710 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_ODTEN1, P_Fld(0x2, SHURK0_SELPH_ODTEN1_DLY_B3_RODTEN_P1)
3711 | P_Fld(0x2, SHURK0_SELPH_ODTEN1_DLY_B3_RODTEN)
3712 | P_Fld(0x2, SHURK0_SELPH_ODTEN1_DLY_B2_RODTEN_P1)
3713 | P_Fld(0x2, SHURK0_SELPH_ODTEN1_DLY_B2_RODTEN));
3714 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_ODTEN0, P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN_P1)
3715 | P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN)
3716 | P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN_P1)
3717 | P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN));
3718 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_ODTEN1, P_Fld(0x4, SHURK1_SELPH_ODTEN1_DLY_B3_R1RODTEN_P1)
3719 | P_Fld(0x4, SHURK1_SELPH_ODTEN1_DLY_B3_R1RODTEN)
3720 | P_Fld(0x4, SHURK1_SELPH_ODTEN1_DLY_B2_R1RODTEN_P1)
3721 | P_Fld(0x4, SHURK1_SELPH_ODTEN1_DLY_B2_R1RODTEN)
3722 | P_Fld(0x7, SHURK1_SELPH_ODTEN1_DLY_B1_R1RODTEN_P1)
3723 | P_Fld(0x7, SHURK1_SELPH_ODTEN1_DLY_B1_R1RODTEN)
3724 | P_Fld(0x7, SHURK1_SELPH_ODTEN1_DLY_B0_R1RODTEN_P1)
3725 | P_Fld(0x7, SHURK1_SELPH_ODTEN1_DLY_B0_R1RODTEN));
3726 }
3727 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
3728 {
3729 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG0, P_Fld(0x4, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1)
3730 | P_Fld(0x3, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED)
3731 | P_Fld(0x3, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1)
3732 | P_Fld(0x3, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED));
3733 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG1, P_Fld(0x4, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED)
3734 | P_Fld(0x7, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1)
3735 | P_Fld(0x3, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED));
3736 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG0, P_Fld(0x4, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED_P1)
3737 | P_Fld(0x3, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED)
3738 | P_Fld(0x4, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED_P1)
3739 | P_Fld(0x4, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED));
3740 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG1, P_Fld(0x3, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED_P1)
3741 | P_Fld(0x7, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED)
3742 | P_Fld(0x5, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED_P1)
3743 | P_Fld(0x1, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED));
3744 }
3745 else
3746 {
3747 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG0, P_Fld(0x2, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1)
3748 | P_Fld(0x2, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED)
3749 | P_Fld(0x2, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1)
3750 | P_Fld(0x2, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED));
3751 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG1, P_Fld(0x6, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1)
3752 | P_Fld(0x2, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED)
3753 | P_Fld(0x6, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1)
3754 | P_Fld(0x2, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED));
3755 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG0, P_Fld(0x3, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED_P1)
3756 | P_Fld(0x3, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED)
3757 | P_Fld(0x3, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED_P1)
3758 | P_Fld(0x3, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED));
3759 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG1, P_Fld(0x4, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED_P1)
3760 | P_Fld(0x4, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED_P1));
3761 }
3762 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
3763 {
3764 }
3765 else
3766 {
3767 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG0, P_Fld(0x3, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1)
3768 | P_Fld(0x3, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED)
3769 | P_Fld(0x3, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1)
3770 | P_Fld(0x3, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED));
3771 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG0, P_Fld(0x4, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED_P1)
3772 | P_Fld(0x4, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED)
3773 | P_Fld(0x4, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED_P1)
3774 | P_Fld(0x4, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED));
3775 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_ODTEN0, P_Fld(0x2, SHURK0_SELPH_ODTEN0_TXDLY_B1_RODTEN)
3776 | P_Fld(0x2, SHURK0_SELPH_ODTEN0_TXDLY_B0_RODTEN));
3777 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_ODTEN0, P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN)
3778 | P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN));
3779 }
3780 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
3781 {
3782 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_ODTEN0, P_Fld(0x0, SHURK0_SELPH_ODTEN0_TXDLY_B3_RODTEN_P1)
3783 | P_Fld(0x0, SHURK0_SELPH_ODTEN0_TXDLY_B3_RODTEN)
3784 | P_Fld(0x0, SHURK0_SELPH_ODTEN0_TXDLY_B2_RODTEN_P1)
3785 | P_Fld(0x0, SHURK0_SELPH_ODTEN0_TXDLY_B2_RODTEN)
3786 | P_Fld(0x2, SHURK0_SELPH_ODTEN0_TXDLY_B1_RODTEN_P1)
3787 | P_Fld(0x2, SHURK0_SELPH_ODTEN0_TXDLY_B1_RODTEN)
3788 | P_Fld(0x2, SHURK0_SELPH_ODTEN0_TXDLY_B0_RODTEN_P1)
3789 | P_Fld(0x2, SHURK0_SELPH_ODTEN0_TXDLY_B0_RODTEN));
3790 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_ODTEN1, P_Fld(0x0, SHURK0_SELPH_ODTEN1_DLY_B3_RODTEN_P1)
3791 | P_Fld(0x0, SHURK0_SELPH_ODTEN1_DLY_B3_RODTEN)
3792 | P_Fld(0x0, SHURK0_SELPH_ODTEN1_DLY_B2_RODTEN_P1)
3793 | P_Fld(0x0, SHURK0_SELPH_ODTEN1_DLY_B2_RODTEN)
3794 | P_Fld(0x0, SHURK0_SELPH_ODTEN1_DLY_B1_RODTEN_P1)
3795 | P_Fld(0x0, SHURK0_SELPH_ODTEN1_DLY_B1_RODTEN)
3796 | P_Fld(0x0, SHURK0_SELPH_ODTEN1_DLY_B0_RODTEN_P1)
3797 | P_Fld(0x0, SHURK0_SELPH_ODTEN1_DLY_B0_RODTEN));
3798 vIO32WriteFldAlign(DRAMC_REG_SHURK0_SELPH_DQSG0, 0x4, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1);
3799 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG1, P_Fld(0x1, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1)
3800 | P_Fld(0x5, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED)
3801 | P_Fld(0x0, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1)
3802 | P_Fld(0x4, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED));
3803 }
3804 else
3805 {
3806 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_ODTEN0, P_Fld(0x0, SHURK0_SELPH_ODTEN0_TXDLY_B3_RODTEN_P1)
3807 | P_Fld(0x0, SHURK0_SELPH_ODTEN0_TXDLY_B3_RODTEN)
3808 | P_Fld(0x0, SHURK0_SELPH_ODTEN0_TXDLY_B2_RODTEN_P1)
3809 | P_Fld(0x0, SHURK0_SELPH_ODTEN0_TXDLY_B2_RODTEN)
3810 | P_Fld(0x2, SHURK0_SELPH_ODTEN0_TXDLY_B1_RODTEN_P1)
3811 | P_Fld(0x2, SHURK0_SELPH_ODTEN0_TXDLY_B0_RODTEN_P1));
3812 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_ODTEN1, P_Fld(0x0, SHURK0_SELPH_ODTEN1_DLY_B3_RODTEN_P1)
3813 | P_Fld(0x0, SHURK0_SELPH_ODTEN1_DLY_B3_RODTEN)
3814 | P_Fld(0x0, SHURK0_SELPH_ODTEN1_DLY_B2_RODTEN_P1)
3815 | P_Fld(0x0, SHURK0_SELPH_ODTEN1_DLY_B2_RODTEN)
3816 | P_Fld(0x0, SHURK0_SELPH_ODTEN1_DLY_B1_RODTEN_P1)
3817 | P_Fld(0x0, SHURK0_SELPH_ODTEN1_DLY_B1_RODTEN)
3818 | P_Fld(0x0, SHURK0_SELPH_ODTEN1_DLY_B0_RODTEN_P1)
3819 | P_Fld(0x0, SHURK0_SELPH_ODTEN1_DLY_B0_RODTEN));
3820 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG1, P_Fld(0x7, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1)
3821 | P_Fld(0x3, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED)
3822 | P_Fld(0x7, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1)
3823 | P_Fld(0x3, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED));
3824 }
3825 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
3826 {
3827 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_ODTEN0, P_Fld(0x0, SHURK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN_P1)
3828 | P_Fld(0x0, SHURK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN)
3829 | P_Fld(0x0, SHURK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN_P1)
3830 | P_Fld(0x0, SHURK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN));
3831 }
3832 else
3833 {
3834 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_ODTEN0, P_Fld(0x0, SHURK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN_P1)
3835 | P_Fld(0x0, SHURK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN)
3836 | P_Fld(0x0, SHURK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN_P1)
3837 | P_Fld(0x0, SHURK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN)
3838 | P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN_P1)
3839 | P_Fld(0x2, SHURK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN_P1));
3840 }
3841 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_ODTEN1, P_Fld(0x0, SHURK1_SELPH_ODTEN1_DLY_B3_R1RODTEN_P1)
3842 | P_Fld(0x0, SHURK1_SELPH_ODTEN1_DLY_B3_R1RODTEN)
3843 | P_Fld(0x0, SHURK1_SELPH_ODTEN1_DLY_B2_R1RODTEN_P1)
3844 | P_Fld(0x0, SHURK1_SELPH_ODTEN1_DLY_B2_R1RODTEN)
3845 | P_Fld(0x0, SHURK1_SELPH_ODTEN1_DLY_B1_R1RODTEN_P1)
3846 | P_Fld(0x0, SHURK1_SELPH_ODTEN1_DLY_B1_R1RODTEN)
3847 | P_Fld(0x0, SHURK1_SELPH_ODTEN1_DLY_B0_R1RODTEN_P1)
3848 | P_Fld(0x0, SHURK1_SELPH_ODTEN1_DLY_B0_R1RODTEN));
3849 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
3850 {
3851 vIO32WriteFldAlign(DRAMC_REG_SHURK1_SELPH_DQSG0, 0x4, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED);
3852 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG1, P_Fld(0x4, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED_P1)
3853 | P_Fld(0x0, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED)
3854 | P_Fld(0x6, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED_P1)
3855 | P_Fld(0x2, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED));
3856 }
3857 else
3858 {
3859 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG1, P_Fld(0x5, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED_P1)
3860 | P_Fld(0x1, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED)
3861 | P_Fld(0x5, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED_P1)
3862 | P_Fld(0x1, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED));
3863 }
3864 }
3865
LegacyGatingDlyLP4_DDR3733(DRAMC_CTX_T * p)3866 static void LegacyGatingDlyLP4_DDR3733(DRAMC_CTX_T *p)
3867 {
3868 U8 ucR0GatingMCK = 0, ucR0GatingB0UI = 0, ucR0GatingB1UI = 0;
3869 U8 ucR1GatingMCK = 0, ucR1GatingB0UI = 0, ucR1GatingB1UI = 0;
3870
3871 U8 ucR0GatingP1MCK = 0, ucR0GatingB0P1UI = 0, ucR0GatingB1P1UI = 0;
3872 U8 ucR1GatingP1MCK = 0, ucR1GatingB0P1UI = 0, ucR1GatingB1P1UI = 0;
3873
3874 U8 ucR0GatingB0PI = 0, ucR0GatingB1PI = 0;
3875 U8 ucR1GatingB0PI = 0, ucR1GatingB1PI = 0;
3876
3877 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
3878 {
3879
3880 ucR0GatingMCK = 0x3;
3881 ucR0GatingP1MCK = 0x3;
3882 ucR0GatingB0UI = 0x3;
3883 ucR0GatingB1UI = 0x3;
3884 ucR0GatingB0P1UI = 0x7;
3885 ucR0GatingB1P1UI = 0x7;
3886 ucR0GatingB0PI = 0x14;
3887 ucR0GatingB1PI = 0x14;
3888
3889 ucR1GatingMCK = 0x4;
3890 ucR1GatingP1MCK = 0x4;
3891 ucR1GatingB0UI = 0x4;
3892 ucR1GatingB1UI = 0x4;
3893 ucR1GatingB0P1UI = 0x7;
3894 ucR1GatingB1P1UI = 0x7;
3895 ucR1GatingB0PI = 0x4;
3896 ucR1GatingB1PI = 0x4;
3897 }
3898 else
3899 {
3900
3901 ucR0GatingMCK = 0x2;
3902 ucR0GatingP1MCK = 0x2;
3903 ucR0GatingB0UI = 0x3;
3904 ucR0GatingB1UI = 0x3;
3905 ucR0GatingB0P1UI = 0x7;
3906 ucR0GatingB1P1UI = 0x7;
3907 ucR0GatingB0PI = 0x11;
3908 ucR0GatingB1PI = 0x11;
3909
3910 ucR1GatingMCK = 0x3;
3911 ucR1GatingP1MCK = 0x3;
3912 ucR1GatingB0UI = 0x2;
3913 ucR1GatingB1UI = 0x2;
3914 ucR1GatingB0P1UI = 0x6;
3915 ucR1GatingB1P1UI = 0x6;
3916 ucR1GatingB0PI = 0x1f;
3917 ucR1GatingB1PI = 0x1f;
3918 }
3919
3920 #if ENABLE_READ_DBI
3921 ucR0GatingMCK++;
3922 ucR0GatingP1MCK++;
3923 ucR1GatingMCK++;
3924 ucR1GatingP1MCK++;
3925 #endif
3926
3927
3928 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG0, P_Fld(ucR0GatingP1MCK, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1)
3929 | P_Fld(ucR0GatingMCK, SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED)
3930 | P_Fld(ucR0GatingP1MCK, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1)
3931 | P_Fld(ucR0GatingMCK, SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED));
3932
3933 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQSG1, P_Fld(ucR0GatingB1P1UI, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1)
3934 | P_Fld(ucR0GatingB1UI, SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED)
3935 | P_Fld(ucR0GatingB0P1UI, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1)
3936 | P_Fld(ucR0GatingB0UI, SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED));
3937
3938
3939 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG0, P_Fld(ucR1GatingP1MCK, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED_P1)
3940 | P_Fld(ucR1GatingMCK, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED)
3941 | P_Fld(ucR1GatingP1MCK, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED_P1)
3942 | P_Fld(ucR1GatingMCK, SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED));
3943
3944 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQSG1, P_Fld(ucR1GatingB1P1UI, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED_P1)
3945 | P_Fld(ucR1GatingB1UI, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED)
3946 | P_Fld(ucR1GatingB0P1UI, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED_P1)
3947 | P_Fld(ucR1GatingB0UI, SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED));
3948
3949
3950 vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQSIEN, P_Fld(0x0, SHURK0_DQSIEN_R0DQS3IEN)
3951 | P_Fld(0x0, SHURK0_DQSIEN_R0DQS2IEN)
3952 | P_Fld(ucR0GatingB1PI, SHURK0_DQSIEN_R0DQS1IEN)
3953 | P_Fld(ucR0GatingB0PI, SHURK0_DQSIEN_R0DQS0IEN));
3954
3955
3956 vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQSIEN, P_Fld(0x0, SHURK1_DQSIEN_R1DQS3IEN)
3957 | P_Fld(0x0, SHURK1_DQSIEN_R1DQS2IEN)
3958 | P_Fld(ucR1GatingB1PI, SHURK1_DQSIEN_R1DQS1IEN)
3959 | P_Fld(ucR1GatingB0PI, SHURK1_DQSIEN_R1DQS0IEN));
3960 }
3961
3962 #endif
3963
3964 #if LEGACY_RX_DLY
3965
LegacyRxDly_LP4_DDR2667(DRAMC_CTX_T * p)3966 static void LegacyRxDly_LP4_DDR2667(DRAMC_CTX_T *p)
3967 {
3968 vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ2, P_Fld(0xa, SHU_R0_B0_DQ2_RK0_RX_ARDQ1_R_DLY_B0)
3969 | P_Fld(0xa, SHU_R0_B0_DQ2_RK0_RX_ARDQ0_R_DLY_B0));
3970 vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ3, P_Fld(0xa, SHU_R0_B0_DQ3_RK0_RX_ARDQ3_R_DLY_B0)
3971 | P_Fld(0xa, SHU_R0_B0_DQ3_RK0_RX_ARDQ2_R_DLY_B0));
3972 vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ4, P_Fld(0xa, SHU_R0_B0_DQ4_RK0_RX_ARDQ5_R_DLY_B0)
3973 | P_Fld(0xa, SHU_R0_B0_DQ4_RK0_RX_ARDQ4_R_DLY_B0));
3974 vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ5, P_Fld(0xa, SHU_R0_B0_DQ5_RK0_RX_ARDQ7_R_DLY_B0)
3975 | P_Fld(0xa, SHU_R0_B0_DQ5_RK0_RX_ARDQ6_R_DLY_B0));
3976 vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ6, P_Fld(0x15, SHU_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0)
3977 | P_Fld(0xa, SHU_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0));
3978 vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ2, P_Fld(0xa, SHU_R0_B1_DQ2_RK0_RX_ARDQ1_R_DLY_B1)
3979 | P_Fld(0xa, SHU_R0_B1_DQ2_RK0_RX_ARDQ0_R_DLY_B1));
3980 vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ3, P_Fld(0xa, SHU_R0_B1_DQ3_RK0_RX_ARDQ3_R_DLY_B1)
3981 | P_Fld(0xa, SHU_R0_B1_DQ3_RK0_RX_ARDQ2_R_DLY_B1));
3982 vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ4, P_Fld(0xa, SHU_R0_B1_DQ4_RK0_RX_ARDQ5_R_DLY_B1)
3983 | P_Fld(0xa, SHU_R0_B1_DQ4_RK0_RX_ARDQ4_R_DLY_B1));
3984 vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ5, P_Fld(0xa, SHU_R0_B1_DQ5_RK0_RX_ARDQ7_R_DLY_B1)
3985 | P_Fld(0xa, SHU_R0_B1_DQ5_RK0_RX_ARDQ6_R_DLY_B1));
3986 vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ6, P_Fld(0x15, SHU_R0_B1_DQ6_RK0_RX_ARDQS0_R_DLY_B1)
3987 | P_Fld(0xa, SHU_R0_B1_DQ6_RK0_RX_ARDQM0_R_DLY_B1));
3988 vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ2, P_Fld(0xb, SHU_R1_B0_DQ2_RK1_RX_ARDQ1_R_DLY_B0)
3989 | P_Fld(0xb, SHU_R1_B0_DQ2_RK1_RX_ARDQ0_R_DLY_B0));
3990 vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ3, P_Fld(0xb, SHU_R1_B0_DQ3_RK1_RX_ARDQ3_R_DLY_B0)
3991 | P_Fld(0xb, SHU_R1_B0_DQ3_RK1_RX_ARDQ2_R_DLY_B0));
3992 vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ4, P_Fld(0xb, SHU_R1_B0_DQ4_RK1_RX_ARDQ5_R_DLY_B0)
3993 | P_Fld(0xb, SHU_R1_B0_DQ4_RK1_RX_ARDQ4_R_DLY_B0));
3994 vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ5, P_Fld(0xb, SHU_R1_B0_DQ5_RK1_RX_ARDQ7_R_DLY_B0)
3995 | P_Fld(0xb, SHU_R1_B0_DQ5_RK1_RX_ARDQ6_R_DLY_B0));
3996 vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ6, P_Fld(0x16, SHU_R1_B0_DQ6_RK1_RX_ARDQS0_R_DLY_B0)
3997 | P_Fld(0xb, SHU_R1_B0_DQ6_RK1_RX_ARDQM0_R_DLY_B0));
3998 vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ2, P_Fld(0xb, SHU_R1_B1_DQ2_RK1_RX_ARDQ1_R_DLY_B1)
3999 | P_Fld(0xb, SHU_R1_B1_DQ2_RK1_RX_ARDQ0_R_DLY_B1));
4000 vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ3, P_Fld(0xb, SHU_R1_B1_DQ3_RK1_RX_ARDQ3_R_DLY_B1)
4001 | P_Fld(0xb, SHU_R1_B1_DQ3_RK1_RX_ARDQ2_R_DLY_B1));
4002 vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ4, P_Fld(0xb, SHU_R1_B1_DQ4_RK1_RX_ARDQ5_R_DLY_B1)
4003 | P_Fld(0xb, SHU_R1_B1_DQ4_RK1_RX_ARDQ4_R_DLY_B1));
4004 vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ5, P_Fld(0xb, SHU_R1_B1_DQ5_RK1_RX_ARDQ7_R_DLY_B1)
4005 | P_Fld(0xb, SHU_R1_B1_DQ5_RK1_RX_ARDQ6_R_DLY_B1));
4006 vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ6, P_Fld(0x16, SHU_R1_B1_DQ6_RK1_RX_ARDQS0_R_DLY_B1)
4007 | P_Fld(0xb, SHU_R1_B1_DQ6_RK1_RX_ARDQM0_R_DLY_B1));
4008 }
4009
LegacyRxDly_LP4_DDR800(DRAMC_CTX_T * p)4010 static void LegacyRxDly_LP4_DDR800(DRAMC_CTX_T *p)
4011 {
4012 U8 u1Dq = 0x0;
4013 U8 u1Dqm = 0x0;
4014 U8 u1Dqs = 0x26;
4015
4016
4017 vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ2, P_Fld(u1Dq, SHU_R0_B0_DQ2_RK0_RX_ARDQ1_R_DLY_B0)
4018 | P_Fld(u1Dq, SHU_R0_B0_DQ2_RK0_RX_ARDQ0_R_DLY_B0));
4019 vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ3, P_Fld(u1Dq, SHU_R0_B0_DQ3_RK0_RX_ARDQ3_R_DLY_B0)
4020 | P_Fld(u1Dq, SHU_R0_B0_DQ3_RK0_RX_ARDQ2_R_DLY_B0));
4021 vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ4, P_Fld(u1Dq, SHU_R0_B0_DQ4_RK0_RX_ARDQ5_R_DLY_B0)
4022 | P_Fld(u1Dq, SHU_R0_B0_DQ4_RK0_RX_ARDQ4_R_DLY_B0));
4023 vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ5, P_Fld(u1Dq, SHU_R0_B0_DQ5_RK0_RX_ARDQ7_R_DLY_B0)
4024 | P_Fld(u1Dq, SHU_R0_B0_DQ5_RK0_RX_ARDQ6_R_DLY_B0));
4025 vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ6, P_Fld(u1Dqs, SHU_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0)
4026 | P_Fld(u1Dqm, SHU_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0));
4027
4028 vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ2, P_Fld(u1Dq, SHU_R0_B1_DQ2_RK0_RX_ARDQ1_R_DLY_B1)
4029 | P_Fld(u1Dq, SHU_R0_B1_DQ2_RK0_RX_ARDQ0_R_DLY_B1));
4030 vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ3, P_Fld(u1Dq, SHU_R0_B1_DQ3_RK0_RX_ARDQ3_R_DLY_B1)
4031 | P_Fld(u1Dq, SHU_R0_B1_DQ3_RK0_RX_ARDQ2_R_DLY_B1));
4032 vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ4, P_Fld(u1Dq, SHU_R0_B1_DQ4_RK0_RX_ARDQ5_R_DLY_B1)
4033 | P_Fld(u1Dq, SHU_R0_B1_DQ4_RK0_RX_ARDQ4_R_DLY_B1));
4034 vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ5, P_Fld(u1Dq, SHU_R0_B1_DQ5_RK0_RX_ARDQ7_R_DLY_B1)
4035 | P_Fld(u1Dq, SHU_R0_B1_DQ5_RK0_RX_ARDQ6_R_DLY_B1));
4036 vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ6, P_Fld(u1Dqs, SHU_R0_B1_DQ6_RK0_RX_ARDQS0_R_DLY_B1)
4037 | P_Fld(u1Dqm, SHU_R0_B1_DQ6_RK0_RX_ARDQM0_R_DLY_B1));
4038
4039 vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ2, P_Fld(u1Dq, SHU_R1_B0_DQ2_RK1_RX_ARDQ1_R_DLY_B0)
4040 | P_Fld(u1Dq, SHU_R1_B0_DQ2_RK1_RX_ARDQ0_R_DLY_B0));
4041 vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ3, P_Fld(u1Dq, SHU_R1_B0_DQ3_RK1_RX_ARDQ3_R_DLY_B0)
4042 | P_Fld(u1Dq, SHU_R1_B0_DQ3_RK1_RX_ARDQ2_R_DLY_B0));
4043 vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ4, P_Fld(u1Dq, SHU_R1_B0_DQ4_RK1_RX_ARDQ5_R_DLY_B0)
4044 | P_Fld(u1Dq, SHU_R1_B0_DQ4_RK1_RX_ARDQ4_R_DLY_B0));
4045 vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ5, P_Fld(u1Dq, SHU_R1_B0_DQ5_RK1_RX_ARDQ7_R_DLY_B0)
4046 | P_Fld(u1Dq, SHU_R1_B0_DQ5_RK1_RX_ARDQ6_R_DLY_B0));
4047 vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ6, P_Fld(u1Dqs, SHU_R1_B0_DQ6_RK1_RX_ARDQS0_R_DLY_B0)
4048 | P_Fld(u1Dqm, SHU_R1_B0_DQ6_RK1_RX_ARDQM0_R_DLY_B0));
4049
4050 vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ2, P_Fld(u1Dq, SHU_R1_B1_DQ2_RK1_RX_ARDQ1_R_DLY_B1)
4051 | P_Fld(u1Dq, SHU_R1_B1_DQ2_RK1_RX_ARDQ0_R_DLY_B1));
4052 vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ3, P_Fld(u1Dq, SHU_R1_B1_DQ3_RK1_RX_ARDQ3_R_DLY_B1)
4053 | P_Fld(u1Dq, SHU_R1_B1_DQ3_RK1_RX_ARDQ2_R_DLY_B1));
4054 vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ4, P_Fld(u1Dq, SHU_R1_B1_DQ4_RK1_RX_ARDQ5_R_DLY_B1)
4055 | P_Fld(u1Dq, SHU_R1_B1_DQ4_RK1_RX_ARDQ4_R_DLY_B1));
4056 vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ5, P_Fld(u1Dq, SHU_R1_B1_DQ5_RK1_RX_ARDQ7_R_DLY_B1)
4057 | P_Fld(u1Dq, SHU_R1_B1_DQ5_RK1_RX_ARDQ6_R_DLY_B1));
4058 vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ6, P_Fld(u1Dqs, SHU_R1_B1_DQ6_RK1_RX_ARDQS0_R_DLY_B1)
4059 | P_Fld(u1Dqm, SHU_R1_B1_DQ6_RK1_RX_ARDQM0_R_DLY_B1));
4060 }
4061
LegacyRxDly_LP4_DDR1600(DRAMC_CTX_T * p)4062 static void LegacyRxDly_LP4_DDR1600(DRAMC_CTX_T *p)
4063 {
4064 U8 u1Rk0_Dq, u1Rk0_Dq5_6;
4065 U8 u1Rk0_Dqm;
4066 U8 u1Rk0_Dqs;
4067 U8 u1Rk1_Dq;
4068 U8 u1Rk1_Dqm;
4069 U8 u1Rk1_Dqs;
4070
4071 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
4072 {
4073 u1Rk0_Dq = 0x0;
4074 u1Rk0_Dq5_6 = 0x2;
4075 u1Rk0_Dqm = 0x0;
4076 u1Rk0_Dqs = 0x7;
4077 u1Rk1_Dq = 0x0;
4078 u1Rk1_Dqm = 0x0;
4079 u1Rk1_Dqs = 0x5;
4080 }
4081 else
4082 {
4083 u1Rk0_Dq = 0x4;
4084 u1Rk0_Dq5_6 = 0x4;
4085 u1Rk0_Dqm = 0x4;
4086 u1Rk0_Dqs = 0x15;
4087 u1Rk1_Dq = 0x5;
4088 u1Rk1_Dqm = 0x5;
4089 u1Rk1_Dqs = 0x16;
4090 }
4091
4092
4093 vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ2, P_Fld(u1Rk0_Dq, SHU_R0_B0_DQ2_RK0_RX_ARDQ1_R_DLY_B0)
4094 | P_Fld(u1Rk0_Dq, SHU_R0_B0_DQ2_RK0_RX_ARDQ0_R_DLY_B0));
4095 vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ3, P_Fld(u1Rk0_Dq, SHU_R0_B0_DQ3_RK0_RX_ARDQ3_R_DLY_B0)
4096 | P_Fld(u1Rk0_Dq, SHU_R0_B0_DQ3_RK0_RX_ARDQ2_R_DLY_B0));
4097 vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ4, P_Fld(u1Rk0_Dq5_6, SHU_R0_B0_DQ4_RK0_RX_ARDQ5_R_DLY_B0)
4098 | P_Fld(u1Rk0_Dq, SHU_R0_B0_DQ4_RK0_RX_ARDQ4_R_DLY_B0));
4099 vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ5, P_Fld(u1Rk0_Dq, SHU_R0_B0_DQ5_RK0_RX_ARDQ7_R_DLY_B0)
4100 | P_Fld(u1Rk0_Dq5_6, SHU_R0_B0_DQ5_RK0_RX_ARDQ6_R_DLY_B0));
4101 vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ6, P_Fld(u1Rk0_Dqs, SHU_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0)
4102 | P_Fld(u1Rk0_Dqm, SHU_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0));
4103
4104 vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ2, P_Fld(u1Rk0_Dq, SHU_R0_B1_DQ2_RK0_RX_ARDQ1_R_DLY_B1)
4105 | P_Fld(u1Rk0_Dq, SHU_R0_B1_DQ2_RK0_RX_ARDQ0_R_DLY_B1));
4106 vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ3, P_Fld(u1Rk0_Dq, SHU_R0_B1_DQ3_RK0_RX_ARDQ3_R_DLY_B1)
4107 | P_Fld(u1Rk0_Dq, SHU_R0_B1_DQ3_RK0_RX_ARDQ2_R_DLY_B1));
4108 vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ4, P_Fld(u1Rk0_Dq5_6, SHU_R0_B1_DQ4_RK0_RX_ARDQ5_R_DLY_B1)
4109 | P_Fld(u1Rk0_Dq, SHU_R0_B1_DQ4_RK0_RX_ARDQ4_R_DLY_B1));
4110 vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ5, P_Fld(u1Rk0_Dq, SHU_R0_B1_DQ5_RK0_RX_ARDQ7_R_DLY_B1)
4111 | P_Fld(u1Rk0_Dq5_6, SHU_R0_B1_DQ5_RK0_RX_ARDQ6_R_DLY_B1));
4112 vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ6, P_Fld(u1Rk0_Dqs, SHU_R0_B1_DQ6_RK0_RX_ARDQS0_R_DLY_B1)
4113 | P_Fld(u1Rk0_Dqm, SHU_R0_B1_DQ6_RK0_RX_ARDQM0_R_DLY_B1));
4114
4115 vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ2, P_Fld(u1Rk1_Dq, SHU_R1_B0_DQ2_RK1_RX_ARDQ1_R_DLY_B0)
4116 | P_Fld(u1Rk1_Dq, SHU_R1_B0_DQ2_RK1_RX_ARDQ0_R_DLY_B0));
4117 vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ3, P_Fld(u1Rk1_Dq, SHU_R1_B0_DQ3_RK1_RX_ARDQ3_R_DLY_B0)
4118 | P_Fld(u1Rk1_Dq, SHU_R1_B0_DQ3_RK1_RX_ARDQ2_R_DLY_B0));
4119 vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ4, P_Fld(u1Rk1_Dq, SHU_R1_B0_DQ4_RK1_RX_ARDQ5_R_DLY_B0)
4120 | P_Fld(u1Rk1_Dq, SHU_R1_B0_DQ4_RK1_RX_ARDQ4_R_DLY_B0));
4121 vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ5, P_Fld(u1Rk1_Dq, SHU_R1_B0_DQ5_RK1_RX_ARDQ7_R_DLY_B0)
4122 | P_Fld(u1Rk1_Dq, SHU_R1_B0_DQ5_RK1_RX_ARDQ6_R_DLY_B0));
4123 vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ6, P_Fld(u1Rk1_Dqs, SHU_R1_B0_DQ6_RK1_RX_ARDQS0_R_DLY_B0)
4124 | P_Fld(u1Rk1_Dqm, SHU_R1_B0_DQ6_RK1_RX_ARDQM0_R_DLY_B0));
4125
4126 vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ2, P_Fld(u1Rk1_Dq, SHU_R1_B1_DQ2_RK1_RX_ARDQ1_R_DLY_B1)
4127 | P_Fld(u1Rk1_Dq, SHU_R1_B1_DQ2_RK1_RX_ARDQ0_R_DLY_B1));
4128 vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ3, P_Fld(u1Rk1_Dq, SHU_R1_B1_DQ3_RK1_RX_ARDQ3_R_DLY_B1)
4129 | P_Fld(u1Rk1_Dq, SHU_R1_B1_DQ3_RK1_RX_ARDQ2_R_DLY_B1));
4130 vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ4, P_Fld(u1Rk1_Dq, SHU_R1_B1_DQ4_RK1_RX_ARDQ5_R_DLY_B1)
4131 | P_Fld(u1Rk1_Dq, SHU_R1_B1_DQ4_RK1_RX_ARDQ4_R_DLY_B1));
4132 vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ5, P_Fld(u1Rk1_Dq, SHU_R1_B1_DQ5_RK1_RX_ARDQ7_R_DLY_B1)
4133 | P_Fld(u1Rk1_Dq, SHU_R1_B1_DQ5_RK1_RX_ARDQ6_R_DLY_B1));
4134 vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ6, P_Fld(u1Rk1_Dqs, SHU_R1_B1_DQ6_RK1_RX_ARDQS0_R_DLY_B1)
4135 | P_Fld(u1Rk1_Dqm, SHU_R1_B1_DQ6_RK1_RX_ARDQM0_R_DLY_B1));
4136 }
4137
LegacyRxDly_LP4_DDR3200(DRAMC_CTX_T * p)4138 static void LegacyRxDly_LP4_DDR3200(DRAMC_CTX_T *p)
4139 {
4140 vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ2, P_Fld(0xa, SHU_R0_B0_DQ2_RK0_RX_ARDQ1_R_DLY_B0)
4141 | P_Fld(0xa, SHU_R0_B0_DQ2_RK0_RX_ARDQ0_R_DLY_B0));
4142 vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ3, P_Fld(0xa, SHU_R0_B0_DQ3_RK0_RX_ARDQ3_R_DLY_B0)
4143 | P_Fld(0xa, SHU_R0_B0_DQ3_RK0_RX_ARDQ2_R_DLY_B0));
4144 vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ4, P_Fld(0xa, SHU_R0_B0_DQ4_RK0_RX_ARDQ5_R_DLY_B0)
4145 | P_Fld(0xa, SHU_R0_B0_DQ4_RK0_RX_ARDQ4_R_DLY_B0));
4146 vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ5, P_Fld(0xa, SHU_R0_B0_DQ5_RK0_RX_ARDQ7_R_DLY_B0)
4147 | P_Fld(0xa, SHU_R0_B0_DQ5_RK0_RX_ARDQ6_R_DLY_B0));
4148 vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ6, P_Fld(0xc, SHU_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0)
4149 | P_Fld(0xa, SHU_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0));
4150 vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ2, P_Fld(0xb, SHU_R1_B0_DQ2_RK1_RX_ARDQ1_R_DLY_B0)
4151 | P_Fld(0xb, SHU_R1_B0_DQ2_RK1_RX_ARDQ0_R_DLY_B0));
4152 vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ3, P_Fld(0xb, SHU_R1_B0_DQ3_RK1_RX_ARDQ3_R_DLY_B0)
4153 | P_Fld(0xb, SHU_R1_B0_DQ3_RK1_RX_ARDQ2_R_DLY_B0));
4154 vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ4, P_Fld(0xb, SHU_R1_B0_DQ4_RK1_RX_ARDQ5_R_DLY_B0)
4155 | P_Fld(0xb, SHU_R1_B0_DQ4_RK1_RX_ARDQ4_R_DLY_B0));
4156 vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ5, P_Fld(0xb, SHU_R1_B0_DQ5_RK1_RX_ARDQ7_R_DLY_B0)
4157 | P_Fld(0xb, SHU_R1_B0_DQ5_RK1_RX_ARDQ6_R_DLY_B0));
4158 vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ6, P_Fld(0xd, SHU_R1_B0_DQ6_RK1_RX_ARDQS0_R_DLY_B0)
4159 | P_Fld(0xb, SHU_R1_B0_DQ6_RK1_RX_ARDQM0_R_DLY_B0));
4160 vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ2, P_Fld(0xa, SHU_R0_B1_DQ2_RK0_RX_ARDQ1_R_DLY_B1)
4161 | P_Fld(0xa, SHU_R0_B1_DQ2_RK0_RX_ARDQ0_R_DLY_B1));
4162 vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ3, P_Fld(0xa, SHU_R0_B1_DQ3_RK0_RX_ARDQ3_R_DLY_B1)
4163 | P_Fld(0xa, SHU_R0_B1_DQ3_RK0_RX_ARDQ2_R_DLY_B1));
4164 vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ4, P_Fld(0xa, SHU_R0_B1_DQ4_RK0_RX_ARDQ5_R_DLY_B1)
4165 | P_Fld(0xa, SHU_R0_B1_DQ4_RK0_RX_ARDQ4_R_DLY_B1));
4166 vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ5, P_Fld(0xa, SHU_R0_B1_DQ5_RK0_RX_ARDQ7_R_DLY_B1)
4167 | P_Fld(0xa, SHU_R0_B1_DQ5_RK0_RX_ARDQ6_R_DLY_B1));
4168 vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ6, P_Fld(0xc, SHU_R0_B1_DQ6_RK0_RX_ARDQS0_R_DLY_B1)
4169 | P_Fld(0xa, SHU_R0_B1_DQ6_RK0_RX_ARDQM0_R_DLY_B1));
4170 vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ2, P_Fld(0xb, SHU_R1_B1_DQ2_RK1_RX_ARDQ1_R_DLY_B1)
4171 | P_Fld(0xb, SHU_R1_B1_DQ2_RK1_RX_ARDQ0_R_DLY_B1));
4172 vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ3, P_Fld(0xb, SHU_R1_B1_DQ3_RK1_RX_ARDQ3_R_DLY_B1)
4173 | P_Fld(0xb, SHU_R1_B1_DQ3_RK1_RX_ARDQ2_R_DLY_B1));
4174 vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ4, P_Fld(0xb, SHU_R1_B1_DQ4_RK1_RX_ARDQ5_R_DLY_B1)
4175 | P_Fld(0xb, SHU_R1_B1_DQ4_RK1_RX_ARDQ4_R_DLY_B1));
4176 vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ5, P_Fld(0xb, SHU_R1_B1_DQ5_RK1_RX_ARDQ7_R_DLY_B1)
4177 | P_Fld(0xb, SHU_R1_B1_DQ5_RK1_RX_ARDQ6_R_DLY_B1));
4178 vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ6, P_Fld(0xd, SHU_R1_B1_DQ6_RK1_RX_ARDQS0_R_DLY_B1)
4179 | P_Fld(0xb, SHU_R1_B1_DQ6_RK1_RX_ARDQM0_R_DLY_B1));
4180 }
4181
LegacyRxDly_LP4_DDR3733(DRAMC_CTX_T * p)4182 static void LegacyRxDly_LP4_DDR3733(DRAMC_CTX_T *p)
4183 {
4184 U8 u1Dq = 0xf;
4185 U8 u1Dqm = 0xf;
4186 U8 u1Dqs = 0x0;
4187
4188
4189 vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ2, P_Fld(u1Dq, SHU_R0_B0_DQ2_RK0_RX_ARDQ1_R_DLY_B0)
4190 | P_Fld(u1Dq, SHU_R0_B0_DQ2_RK0_RX_ARDQ0_R_DLY_B0));
4191 vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ3, P_Fld(u1Dq, SHU_R0_B0_DQ3_RK0_RX_ARDQ3_R_DLY_B0)
4192 | P_Fld(u1Dq, SHU_R0_B0_DQ3_RK0_RX_ARDQ2_R_DLY_B0));
4193 vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ4, P_Fld(u1Dq, SHU_R0_B0_DQ4_RK0_RX_ARDQ5_R_DLY_B0)
4194 | P_Fld(u1Dq, SHU_R0_B0_DQ4_RK0_RX_ARDQ4_R_DLY_B0));
4195 vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ5, P_Fld(u1Dq, SHU_R0_B0_DQ5_RK0_RX_ARDQ7_R_DLY_B0)
4196 | P_Fld(u1Dq, SHU_R0_B0_DQ5_RK0_RX_ARDQ6_R_DLY_B0));
4197 vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ6, P_Fld(u1Dqs, SHU_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0)
4198 | P_Fld(u1Dqm, SHU_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0));
4199
4200 vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ2, P_Fld(u1Dq, SHU_R1_B0_DQ2_RK1_RX_ARDQ1_R_DLY_B0)
4201 | P_Fld(u1Dq, SHU_R1_B0_DQ2_RK1_RX_ARDQ0_R_DLY_B0));
4202 vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ3, P_Fld(u1Dq, SHU_R1_B0_DQ3_RK1_RX_ARDQ3_R_DLY_B0)
4203 | P_Fld(u1Dq, SHU_R1_B0_DQ3_RK1_RX_ARDQ2_R_DLY_B0));
4204 vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ4, P_Fld(u1Dq, SHU_R1_B0_DQ4_RK1_RX_ARDQ5_R_DLY_B0)
4205 | P_Fld(u1Dq, SHU_R1_B0_DQ4_RK1_RX_ARDQ4_R_DLY_B0));
4206 vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ5, P_Fld(u1Dq, SHU_R1_B0_DQ5_RK1_RX_ARDQ7_R_DLY_B0)
4207 | P_Fld(u1Dq, SHU_R1_B0_DQ5_RK1_RX_ARDQ6_R_DLY_B0));
4208 vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ6, P_Fld(u1Dqs, SHU_R1_B0_DQ6_RK1_RX_ARDQS0_R_DLY_B0)
4209 | P_Fld(u1Dqm, SHU_R1_B0_DQ6_RK1_RX_ARDQM0_R_DLY_B0));
4210
4211 vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ2, P_Fld(u1Dq, SHU_R0_B1_DQ2_RK0_RX_ARDQ1_R_DLY_B1)
4212 | P_Fld(u1Dq, SHU_R0_B1_DQ2_RK0_RX_ARDQ0_R_DLY_B1));
4213 vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ3, P_Fld(u1Dq, SHU_R0_B1_DQ3_RK0_RX_ARDQ3_R_DLY_B1)
4214 | P_Fld(u1Dq, SHU_R0_B1_DQ3_RK0_RX_ARDQ2_R_DLY_B1));
4215 vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ4, P_Fld(u1Dq, SHU_R0_B1_DQ4_RK0_RX_ARDQ5_R_DLY_B1)
4216 | P_Fld(u1Dq, SHU_R0_B1_DQ4_RK0_RX_ARDQ4_R_DLY_B1));
4217 vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ5, P_Fld(u1Dq, SHU_R0_B1_DQ5_RK0_RX_ARDQ7_R_DLY_B1)
4218 | P_Fld(u1Dq, SHU_R0_B1_DQ5_RK0_RX_ARDQ6_R_DLY_B1));
4219 vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ6, P_Fld(u1Dqs, SHU_R0_B1_DQ6_RK0_RX_ARDQS0_R_DLY_B1)
4220 | P_Fld(u1Dqm, SHU_R0_B1_DQ6_RK0_RX_ARDQM0_R_DLY_B1));
4221
4222 vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ2, P_Fld(u1Dq, SHU_R1_B1_DQ2_RK1_RX_ARDQ1_R_DLY_B1)
4223 | P_Fld(u1Dq, SHU_R1_B1_DQ2_RK1_RX_ARDQ0_R_DLY_B1));
4224 vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ3, P_Fld(u1Dq, SHU_R1_B1_DQ3_RK1_RX_ARDQ3_R_DLY_B1)
4225 | P_Fld(u1Dq, SHU_R1_B1_DQ3_RK1_RX_ARDQ2_R_DLY_B1));
4226 vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ4, P_Fld(u1Dq, SHU_R1_B1_DQ4_RK1_RX_ARDQ5_R_DLY_B1)
4227 | P_Fld(u1Dq, SHU_R1_B1_DQ4_RK1_RX_ARDQ4_R_DLY_B1));
4228 vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ5, P_Fld(u1Dq, SHU_R1_B1_DQ5_RK1_RX_ARDQ7_R_DLY_B1)
4229 | P_Fld(u1Dq, SHU_R1_B1_DQ5_RK1_RX_ARDQ6_R_DLY_B1));
4230 vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ6, P_Fld(u1Dqs, SHU_R1_B1_DQ6_RK1_RX_ARDQS0_R_DLY_B1)
4231 | P_Fld(u1Dqm, SHU_R1_B1_DQ6_RK1_RX_ARDQM0_R_DLY_B1));
4232 }
4233
4234 #endif
4235
4236 #if LEGACY_DAT_LAT
LegacyDatlatLP4_DDR3733(DRAMC_CTX_T * p)4237 static void LegacyDatlatLP4_DDR3733(DRAMC_CTX_T *p)
4238 {
4239
4240 #if 0
4241 vIO32WriteFldMulti(DRAMC_REG_SHU_RANKCTL, P_Fld(0x7, SHU_RANKCTL_RANKINCTL_PHY)
4242 | P_Fld(0x5, SHU_RANKCTL_RANKINCTL_ROOT1)
4243 | P_Fld(0x5, SHU_RANKCTL_RANKINCTL));
4244 #endif
4245
4246
4247 /*vIO32WriteFldMulti(DRAMC_REG_SHU_CONF1, P_Fld(0x11, SHU_CONF1_DATLAT)
4248 | P_Fld(0xf, SHU_CONF1_DATLAT_DSEL)
4249 | P_Fld(0xf, SHU_CONF1_DATLAT_DSEL_PHY));*/
4250
4251
4252 vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRDSEL_DIV2_OPT)
4253 | P_Fld(0x0, SHU_B0_DQ7_R_DMRDSEL_LOBYTE_OPT)
4254 | P_Fld(0x0, SHU_B0_DQ7_R_DMRDSEL_HIBYTE_OPT));
4255
4256
4257 vIO32WriteFldMulti(DRAMC_REG_SHU_PIPE, P_Fld(0x1, SHU_PIPE_READ_START_EXTEND1)
4258 | P_Fld(0x1, SHU_PIPE_DLE_LAST_EXTEND1)
4259 | P_Fld(0x1, SHU_PIPE_READ_START_EXTEND2)
4260 | P_Fld(0x1, SHU_PIPE_DLE_LAST_EXTEND2)
4261 | P_Fld(0x0, SHU_PIPE_READ_START_EXTEND3)
4262 | P_Fld(0x0, SHU_PIPE_DLE_LAST_EXTEND3));
4263 }
4264 #endif
4265 #endif //__A60868_TO_BE_PORTING__
4266
4267 #if __A60868_TO_BE_PORTING__
DramcSetting_LP4_TX_Delay_DDR3733(DRAMC_CTX_T * p,DRAM_RANK_T eRank)4268 static void DramcSetting_LP4_TX_Delay_DDR3733(DRAMC_CTX_T *p, DRAM_RANK_T eRank)
4269 {
4270 U8 ucR0TxdlyOendq = 0, ucR0Txdlydq = 0;
4271 U8 ucR1TxdlyOendq = 0, ucR1Txdlydq = 0;
4272
4273 if (eRank == RANK_0)
4274 {
4275 if (vGet_Div_Mode(p) == DIV4_MODE)
4276 {
4277 ucR0TxdlyOendq = 0x3;
4278 ucR0Txdlydq = 0x4;
4279 }
4280 else
4281 {
4282 ucR0TxdlyOendq = 0x3;
4283 ucR0Txdlydq = 0x4;
4284 }
4285
4286 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
4287 {
4288 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ0, P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ3)
4289 | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ2)
4290 | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ1)
4291 | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ0)
4292 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ0_TXDLY_DQ3)
4293 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ0_TXDLY_DQ2)
4294 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ0_TXDLY_DQ1)
4295 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ0_TXDLY_DQ0));
4296 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ1, P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM3)
4297 | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM2)
4298 | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM1)
4299 | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM0)
4300 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ1_TXDLY_DQM3)
4301 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ1_TXDLY_DQM2)
4302 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ1_TXDLY_DQM1)
4303 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ1_TXDLY_DQM0));
4304 }
4305 else
4306 {
4307 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ0, P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ3)
4308 | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ2)
4309 | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ1)
4310 | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ0)
4311 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ0_TXDLY_DQ3)
4312 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ0_TXDLY_DQ2)
4313 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ0_TXDLY_DQ1)
4314 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ0_TXDLY_DQ0));
4315 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ1, P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM3)
4316 | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM2)
4317 | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM1)
4318 | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM0)
4319 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ1_TXDLY_DQM3)
4320 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ1_TXDLY_DQM2)
4321 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ1_TXDLY_DQM1)
4322 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ1_TXDLY_DQM0));
4323 }
4324 if (vGet_Div_Mode(p) == DIV4_MODE)
4325 {
4326 ucR0TxdlyOendq = 0x2;
4327 ucR0Txdlydq = 0x1;
4328 }
4329 else
4330 {
4331 ucR0TxdlyOendq = 0x7;
4332 ucR0Txdlydq = 0x2;
4333 }
4334 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ2, P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ2_DLY_OEN_DQ3)
4335 | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ2_DLY_OEN_DQ2)
4336 | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ2_DLY_OEN_DQ1)
4337 | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ2_DLY_OEN_DQ0)
4338 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ2_DLY_DQ3)
4339 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ2_DLY_DQ2)
4340 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ2_DLY_DQ1)
4341 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ2_DLY_DQ0));
4342 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ3, P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ3_DLY_OEN_DQM3)
4343 | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ3_DLY_OEN_DQM2)
4344 | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ3_DLY_OEN_DQM1)
4345 | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ3_DLY_OEN_DQM0)
4346 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ3_DLY_DQM3)
4347 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ3_DLY_DQM2)
4348 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ3_DLY_DQM1)
4349 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ3_DLY_DQM0));
4350 }
4351 else
4352 {
4353 if (vGet_Div_Mode(p) == DIV4_MODE)
4354 {
4355 ucR1TxdlyOendq = 0x3;
4356 ucR1Txdlydq = 0x4;
4357 }
4358 else
4359 {
4360 ucR1TxdlyOendq = 0x4;
4361 ucR1Txdlydq = 0x4;
4362 }
4363 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
4364 {
4365 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ0, P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ3)
4366 | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ2)
4367 | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ1)
4368 | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ0)
4369 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ0_TX_DLY_R1DQ3)
4370 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ0_TX_DLY_R1DQ2)
4371 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ0_TX_DLY_R1DQ1)
4372 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ0_TX_DLY_R1DQ0));
4373 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ1, P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM3)
4374 | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM2)
4375 | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM1)
4376 | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM0)
4377 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ1_TX_DLY_R1DQM3)
4378 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ1_TX_DLY_R1DQM2)
4379 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ1_TX_DLY_R1DQM1)
4380 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ1_TX_DLY_R1DQM0));
4381 }
4382 else
4383 {
4384 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ0, P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ3)
4385 | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ2)
4386 | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ1)
4387 | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ0)
4388 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ0_TX_DLY_R1DQ3)
4389 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ0_TX_DLY_R1DQ2)
4390 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ0_TX_DLY_R1DQ1)
4391 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ0_TX_DLY_R1DQ0));
4392 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ1, P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM3)
4393 | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM2)
4394 | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM1)
4395 | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM0)
4396 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ1_TX_DLY_R1DQM3)
4397 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ1_TX_DLY_R1DQM2)
4398 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ1_TX_DLY_R1DQM1)
4399 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ1_TX_DLY_R1DQM0));
4400 }
4401 if (vGet_Div_Mode(p) == DIV4_MODE)
4402 {
4403 ucR1TxdlyOendq = 0x3;
4404 ucR1Txdlydq = 0x2;
4405 }
4406 else
4407 {
4408 ucR1TxdlyOendq = 0x0;
4409 ucR1Txdlydq = 0x3;
4410 }
4411 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ2, P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ3)
4412 | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ2)
4413 | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ1)
4414 | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ0)
4415 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ2_DLY_R1DQ3)
4416 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ2_DLY_R1DQ2)
4417 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ2_DLY_R1DQ1)
4418 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ2_DLY_R1DQ0));
4419 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ3, P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM3)
4420 | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM2)
4421 | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM1)
4422 | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM0)
4423 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ3_DLY_R1DQM3)
4424 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ3_DLY_R1DQM2)
4425 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ3_DLY_R1DQM1)
4426 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ3_DLY_R1DQM0));
4427 }
4428 }
4429
DramcSetting_Olympus_LP4_ByteMode_DDR4266(DRAMC_CTX_T * p)4430 static void DramcSetting_Olympus_LP4_ByteMode_DDR4266(DRAMC_CTX_T *p)
4431 {
4432 vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_OEN_DQS3)
4433 | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_OEN_DQS2)
4434 | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_OEN_DQS1)
4435 | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_OEN_DQS0)
4436 | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS3)
4437 | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS2)
4438 | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS1)
4439 | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS0));
4440 vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0x2, SHU_SELPH_DQS1_DLY_OEN_DQS3)
4441 | P_Fld(0x2, SHU_SELPH_DQS1_DLY_OEN_DQS2)
4442 | P_Fld(0x2, SHU_SELPH_DQS1_DLY_OEN_DQS1)
4443 | P_Fld(0x2, SHU_SELPH_DQS1_DLY_OEN_DQS0)
4444 | P_Fld(0x5, SHU_SELPH_DQS1_DLY_DQS3)
4445 | P_Fld(0x5, SHU_SELPH_DQS1_DLY_DQS2)
4446 | P_Fld(0x5, SHU_SELPH_DQS1_DLY_DQS1)
4447 | P_Fld(0x5, SHU_SELPH_DQS1_DLY_DQS0));
4448 }
4449
DramcSetting_Olympus_LP4_ByteMode_DDR3733(DRAMC_CTX_T * p)4450 static void DramcSetting_Olympus_LP4_ByteMode_DDR3733(DRAMC_CTX_T *p)
4451 {
4452 DramcSetting_LP4_TX_Delay_DDR3733(p, RANK_0);
4453 DramcSetting_LP4_TX_Delay_DDR3733(p, RANK_1);
4454
4455 vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ7, P_Fld(0xe, SHU_R0_B0_DQ7_RK0_ARPI_DQM_B0)
4456 | P_Fld(0x13, SHU_R0_B0_DQ7_RK0_ARPI_DQ_B0));
4457 vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ7, P_Fld(0xe, SHU_R0_B1_DQ7_RK0_ARPI_DQM_B1)
4458 | P_Fld(0x13, SHU_R0_B1_DQ7_RK0_ARPI_DQ_B1));
4459 vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ7, P_Fld(0x19, SHU_R1_B0_DQ7_RK1_ARPI_DQM_B0)
4460 | P_Fld(0x22, SHU_R1_B0_DQ7_RK1_ARPI_DQ_B0));
4461 vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ7, P_Fld(0x19, SHU_R1_B1_DQ7_RK1_ARPI_DQM_B1)
4462 | P_Fld(0x22, SHU_R1_B1_DQ7_RK1_ARPI_DQ_B1));
4463
4464
4465 vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS3)
4466 | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS2)
4467 | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS1)
4468 | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS0)
4469 | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS3)
4470 | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS2)
4471 | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS1)
4472 | P_Fld(0x4, SHU_SELPH_DQS0_TXDLY_DQS0));
4473
4474 vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0x6, SHU_SELPH_DQS1_DLY_OEN_DQS3)
4475 | P_Fld(0x6, SHU_SELPH_DQS1_DLY_OEN_DQS2)
4476 | P_Fld(0x6, SHU_SELPH_DQS1_DLY_OEN_DQS1)
4477 | P_Fld(0x6, SHU_SELPH_DQS1_DLY_OEN_DQS0)
4478 | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS3)
4479 | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS2)
4480 | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS1)
4481 | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS0));
4482
4483 #if LEGACY_GATING_DLY
4484 /*vIO32WriteFldMulti(DRAMC_REG_SHU_PHY_RX_CTRL, P_Fld(0x1, SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN)
4485 | P_Fld(0x2, SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET)
4486 | P_Fld(0x2, SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET)
4487 | P_Fld(0x1, SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD)
4488 | P_Fld(0x0, SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL)
4489 | P_Fld(0x2, SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD)
4490 | P_Fld(0x0, SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL));*/
4491
4492 LegacyGatingDlyLP4_DDR3733(p);
4493 #endif
4494
4495 #if LEGACY_RX_DLY
4496 LegacyRxDly_LP4_DDR3733(p);
4497 #endif
4498
4499
4500 #if LEGACY_DAT_LAT
4501 LegacyDatlatLP4_DDR3733(p);
4502 #endif
4503 }
4504
4505
DramcSetting_Olympus_LP4_ByteMode_DDR2667(DRAMC_CTX_T * p)4506 static void DramcSetting_Olympus_LP4_ByteMode_DDR2667(DRAMC_CTX_T *p)
4507 {
4508
4509 #if LEGACY_TDQSCK_PRECAL
4510 LegacyPreCalLP4_DDR2667(p);
4511 #endif
4512 //vIO32WriteFldAlign(DRAMC_REG_SHU_CONF2, 0x54, SHU_CONF2_FSPCHG_PRDCNT);//ACTiming related -> set in UpdateACTiming_Reg()
4513 #if 0
4514 vIO32WriteFldMulti(DRAMC_REG_SHU_RANKCTL, P_Fld(0x4, SHU_RANKCTL_RANKINCTL_PHY)
4515 | P_Fld(0x2, SHU_RANKCTL_RANKINCTL_ROOT1)
4516 | P_Fld(0x2, SHU_RANKCTL_RANKINCTL));
4517 #endif
4518 vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL, P_Fld(0x3, SHU_CKECTRL_TCKESRX));
4519 //| P_Fld(0x3, SHU_CKECTRL_CKEPRD));
4520 vIO32WriteFldMulti(DRAMC_REG_SHU_ODTCTRL, P_Fld(0x1, SHU_ODTCTRL_RODTE)
4521 | P_Fld(0x1, SHU_ODTCTRL_RODTE2)
4522 //| P_Fld(0x4, SHU_ODTCTRL_RODT) //Set in UpdateACTimingReg()
4523 | P_Fld(0x1, SHU_ODTCTRL_ROEN));
4524 vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ7, 0x1, SHU_B0_DQ7_R_DMRODTEN_B0);
4525 vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ7, 0x1, SHU_B1_DQ7_R_DMRODTEN_B1);
4526 #if LEGACY_TX_TRACK
4527 LegacyTxTrackLP4_DDR2667(p);
4528 #endif
4529 vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x2, SHU_SELPH_DQS0_TXDLY_OEN_DQS3)
4530 | P_Fld(0x2, SHU_SELPH_DQS0_TXDLY_OEN_DQS2)
4531 | P_Fld(0x2, SHU_SELPH_DQS0_TXDLY_OEN_DQS1)
4532 | P_Fld(0x2, SHU_SELPH_DQS0_TXDLY_OEN_DQS0)
4533 | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_DQS3)
4534 | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_DQS2)
4535 | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_DQS1)
4536 | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_DQS0));
4537 vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0x6, SHU_SELPH_DQS1_DLY_OEN_DQS3)
4538 | P_Fld(0x6, SHU_SELPH_DQS1_DLY_OEN_DQS2)
4539 | P_Fld(0x6, SHU_SELPH_DQS1_DLY_OEN_DQS1)
4540 | P_Fld(0x6, SHU_SELPH_DQS1_DLY_OEN_DQS0)
4541 | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS3)
4542 | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS2)
4543 | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS1)
4544 | P_Fld(0x1, SHU_SELPH_DQS1_DLY_DQS0));
4545
4546 vIO32WriteFldAlign(DRAMC_REG_SHU_DQS2DQ_TX, 0x7, SHU_DQS2DQ_TX_OE2DQ_OFFSET);
4547 //vIO32WriteFldAlign(DRAMC_REG_SHU_HWSET_MR2, 0x24, SHU_HWSET_MR2_HWSET_MR2_OP);
4548 //vIO32WriteFldAlign(DRAMC_REG_SHU_HWSET_MR13, 0xc8, SHU_HWSET_MR13_HWSET_MR13_OP);
4549 //vIO32WriteFldAlign(DRAMC_REG_SHU_HWSET_VRCG, 0xc0, SHU_HWSET_VRCG_HWSET_VRCG_OP);
4550 vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQSIEN, P_Fld(0x19, SHURK0_DQSIEN_R0DQS1IEN)
4551 | P_Fld(0x19, SHURK0_DQSIEN_R0DQS0IEN));
4552 vIO32WriteFldMulti(DRAMC_REG_SHURK0_PI, P_Fld(0x14, SHURK0_PI_RK0_ARPI_DQM_B1)
4553 | P_Fld(0x14, SHURK0_PI_RK0_ARPI_DQM_B0)
4554 | P_Fld(0x14, SHURK0_PI_RK0_ARPI_DQ_B1)
4555 | P_Fld(0x14, SHURK0_PI_RK0_ARPI_DQ_B0));
4556
4557 #if LEGACY_GATING_DLY
4558 LegacyGatingDlyLP4_DDR2667(p);
4559 #endif
4560
4561 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
4562 {
4563 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ0, P_Fld(0x2, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ3)
4564 | P_Fld(0x2, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ2)
4565 | P_Fld(0x2, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ1)
4566 | P_Fld(0x2, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ0)
4567 | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_DQ3)
4568 | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_DQ2)
4569 | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_DQ1)
4570 | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_DQ0));
4571 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ1, P_Fld(0x2, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM3)
4572 | P_Fld(0x2, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM2)
4573 | P_Fld(0x2, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM1)
4574 | P_Fld(0x2, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM0)
4575 | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_DQM3)
4576 | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_DQM2)
4577 | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_DQM1)
4578 | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_DQM0));
4579 }
4580 else
4581 {
4582 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ0, P_Fld(0x2, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ3)
4583 | P_Fld(0x2, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ2)
4584 | P_Fld(0x2, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ1)
4585 | P_Fld(0x2, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ0)
4586 | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_DQ3)
4587 | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_DQ2)
4588 | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_DQ1)
4589 | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_DQ0));
4590 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ1, P_Fld(0x2, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM3)
4591 | P_Fld(0x2, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM2)
4592 | P_Fld(0x2, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM1)
4593 | P_Fld(0x2, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM0)
4594 | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_DQM3)
4595 | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_DQM2)
4596 | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_DQM1)
4597 | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_DQM0));
4598 }
4599 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ2, P_Fld(0x6, SHURK0_SELPH_DQ2_DLY_OEN_DQ3)
4600 | P_Fld(0x6, SHURK0_SELPH_DQ2_DLY_OEN_DQ2)
4601 | P_Fld(0x6, SHURK0_SELPH_DQ2_DLY_OEN_DQ1)
4602 | P_Fld(0x6, SHURK0_SELPH_DQ2_DLY_OEN_DQ0)
4603 | P_Fld(0x1, SHURK0_SELPH_DQ2_DLY_DQ3)
4604 | P_Fld(0x1, SHURK0_SELPH_DQ2_DLY_DQ2)
4605 | P_Fld(0x1, SHURK0_SELPH_DQ2_DLY_DQ1)
4606 | P_Fld(0x1, SHURK0_SELPH_DQ2_DLY_DQ0));
4607 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ3, P_Fld(0x6, SHURK0_SELPH_DQ3_DLY_OEN_DQM3)
4608 | P_Fld(0x6, SHURK0_SELPH_DQ3_DLY_OEN_DQM2)
4609 | P_Fld(0x6, SHURK0_SELPH_DQ3_DLY_OEN_DQM1)
4610 | P_Fld(0x6, SHURK0_SELPH_DQ3_DLY_OEN_DQM0)
4611 | P_Fld(0x1, SHURK0_SELPH_DQ3_DLY_DQM3)
4612 | P_Fld(0x1, SHURK0_SELPH_DQ3_DLY_DQM2)
4613 | P_Fld(0x1, SHURK0_SELPH_DQ3_DLY_DQM1)
4614 | P_Fld(0x1, SHURK0_SELPH_DQ3_DLY_DQM0));
4615 //vIO32WriteFldAlign(DRAMC_REG_SHURK1_DQSCTL, 0x4, SHURK1_DQSCTL_R1DQSINCTL); //Set in UpdateACTimingReg()
4616 vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQSIEN, P_Fld(0x1f, SHURK1_DQSIEN_R1DQS1IEN)
4617 | P_Fld(0x1f, SHURK1_DQSIEN_R1DQS0IEN));
4618 vIO32WriteFldMulti(DRAMC_REG_SHURK1_PI, P_Fld(0x14, SHURK1_PI_RK1_ARPI_DQM_B1)
4619 | P_Fld(0x14, SHURK1_PI_RK1_ARPI_DQM_B0)
4620 | P_Fld(0x14, SHURK1_PI_RK1_ARPI_DQ_B1)
4621 | P_Fld(0x14, SHURK1_PI_RK1_ARPI_DQ_B0));
4622 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
4623 {
4624 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ0, P_Fld(0x2, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ3)
4625 | P_Fld(0x2, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ2)
4626 | P_Fld(0x2, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ1)
4627 | P_Fld(0x2, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ0)
4628 | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1DQ3)
4629 | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1DQ2)
4630 | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1DQ1)
4631 | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1DQ0));
4632 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ1, P_Fld(0x2, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM3)
4633 | P_Fld(0x2, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM2)
4634 | P_Fld(0x2, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM1)
4635 | P_Fld(0x2, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM0)
4636 | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1DQM3)
4637 | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1DQM2)
4638 | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1DQM1)
4639 | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1DQM0));
4640 }
4641 else
4642 {
4643 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ0, P_Fld(0x2, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ3)
4644 | P_Fld(0x2, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ2)
4645 | P_Fld(0x2, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ1)
4646 | P_Fld(0x2, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ0)
4647 | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1DQ3)
4648 | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1DQ2)
4649 | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1DQ1)
4650 | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1DQ0));
4651 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ1, P_Fld(0x2, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM3)
4652 | P_Fld(0x2, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM2)
4653 | P_Fld(0x2, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM1)
4654 | P_Fld(0x2, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM0)
4655 | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1DQM3)
4656 | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1DQM2)
4657 | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1DQM1)
4658 | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1DQM0));
4659 }
4660 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ2, P_Fld(0x7, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ3)
4661 | P_Fld(0x7, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ2)
4662 | P_Fld(0x7, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ1)
4663 | P_Fld(0x7, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ0)
4664 | P_Fld(0x2, SHURK1_SELPH_DQ2_DLY_R1DQ3)
4665 | P_Fld(0x2, SHURK1_SELPH_DQ2_DLY_R1DQ2)
4666 | P_Fld(0x2, SHURK1_SELPH_DQ2_DLY_R1DQ1)
4667 | P_Fld(0x2, SHURK1_SELPH_DQ2_DLY_R1DQ0));
4668 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ3, P_Fld(0x7, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM3)
4669 | P_Fld(0x7, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM2)
4670 | P_Fld(0x7, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM1)
4671 | P_Fld(0x7, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM0)
4672 | P_Fld(0x2, SHURK1_SELPH_DQ3_DLY_R1DQM3)
4673 | P_Fld(0x2, SHURK1_SELPH_DQ3_DLY_R1DQM2)
4674 | P_Fld(0x2, SHURK1_SELPH_DQ3_DLY_R1DQM1)
4675 | P_Fld(0x2, SHURK1_SELPH_DQ3_DLY_R1DQM0));
4676 vIO32WriteFldMulti(DRAMC_REG_SHU_DQSG_RETRY, P_Fld(0x4, SHU_DQSG_RETRY_R_DQSIENLAT)
4677 | P_Fld(0x1, SHU_DQSG_RETRY_R_DDR1866_PLUS));
4678
4679
4680 vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ5, 0x3, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0);
4681 //vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ6, P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B0)
4682 // | P_Fld(0x1, SHU_B0_DQ6_RG_ARPI_MIDPI_EN_B0));
4683 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
4684 {
4685 vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_MIDPI_DIV4_ENABLE)
4686 | P_Fld(0x1, SHU_B0_DQ7_MIDPI_ENABLE));
4687 }
4688 else
4689 {
4690 vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ7, P_Fld(0x1, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0)
4691 | P_Fld(0x1, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0)
4692 | P_Fld(0x0, SHU_B0_DQ7_MIDPI_DIV4_ENABLE)
4693 | P_Fld(0x1, SHU_B0_DQ7_MIDPI_ENABLE));
4694 }
4695 vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ5, 0x3, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1);
4696 //vIO32WriteFldMulti(DDRPHY_SHU_B1_DQ6, P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B1)
4697 // | P_Fld(0x1, SHU_B1_DQ6_RG_ARPI_MIDPI_EN_B1));
4698 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
4699 {
4700 }
4701 else
4702 {
4703 vIO32WriteFldMulti(DDRPHY_SHU_B1_DQ7, P_Fld(0x1, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1)
4704 | P_Fld(0x1, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1));
4705 }
4706 //DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
4707 //vIO32WriteFldMulti(DDRPHY_SHU_CA_CMD6, P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_MIDPI_CKDIV4_EN_CA)
4708 // | P_Fld(0x1, SHU_CA_CMD6_RG_ARPI_MIDPI_EN_CA));
4709 //vIO32WriteFldMulti(DDRPHY_SHU_CA_CMD6+SHIFT_TO_CHB_ADDR, P_Fld(0x0, SHU_CA_CMD6_RG_ARPI_MIDPI_CKDIV4_EN_CA)
4710 // | P_Fld(0x1, SHU_CA_CMD6_RG_ARPI_MIDPI_EN_CA));
4711 //DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
4712 //vIO32WriteFldAlign(DDRPHY_SHU_PLL5, 0x3300, SHU_PLL5_RG_RPHYPLL_SDM_PCW);
4713 //vIO32WriteFldAlign(DDRPHY_SHU_PLL7, 0x3300, SHU_PLL7_RG_RCLRPLL_SDM_PCW);
4714 vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ7, P_Fld(0x1e, SHU_R0_B0_DQ7_RK0_ARPI_DQM_B0)
4715 | P_Fld(0x1e, SHU_R0_B0_DQ7_RK0_ARPI_DQ_B0));
4716 vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ7, P_Fld(0x1e, SHU_R0_B1_DQ7_RK0_ARPI_DQM_B1)
4717 | P_Fld(0x1e, SHU_R0_B1_DQ7_RK0_ARPI_DQ_B1));
4718 vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ7, P_Fld(0x1e, SHU_R1_B0_DQ7_RK1_ARPI_DQM_B0)
4719 | P_Fld(0x1e, SHU_R1_B0_DQ7_RK1_ARPI_DQ_B0));
4720 vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ7, P_Fld(0x1e, SHU_R1_B1_DQ7_RK1_ARPI_DQM_B1)
4721 | P_Fld(0x1e, SHU_R1_B1_DQ7_RK1_ARPI_DQ_B1));
4722 #if LEGACY_RX_DLY
4723 LegacyRxDly_LP4_DDR2667(p);
4724 #endif
4725 #if LEGACY_DELAY_CELL
4726 LegacyDlyCellInitLP4_DDR2667(p);
4727 #endif
4728
4729 }
4730
DramcSetting_LP4_TX_Delay_DDR1600(DRAMC_CTX_T * p,DRAM_RANK_T eRank)4731 static void DramcSetting_LP4_TX_Delay_DDR1600(DRAMC_CTX_T *p, DRAM_RANK_T eRank)
4732 {
4733 U8 ucR0TxdlyOendq = 0, ucR0Txdlydq = 0;
4734 U8 ucR1TxdlyOendq = 0, ucR1Txdlydq = 0;
4735 U8 u1R0B0Pi = 0, u1R0B1Pi = 0;
4736 U8 u1R1B0Pi = 0, u1R1B1Pi = 0;
4737
4738 if (eRank == RANK_0)
4739 {
4740 if (vGet_Div_Mode(p) == DIV4_MODE)
4741 {
4742 ucR0TxdlyOendq = 0x3;
4743 ucR0Txdlydq = 0x4;
4744 }
4745 else
4746 {
4747 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
4748 {
4749 ucR0TxdlyOendq = 0x1;
4750 ucR0Txdlydq = 0x2;
4751 }
4752 else
4753 {
4754 ucR0TxdlyOendq = 0x1;
4755 ucR0Txdlydq = 0x2;
4756 }
4757 }
4758
4759 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
4760 {
4761 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ0, P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ3)
4762 | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ2)
4763 | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ1)
4764 | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ0)
4765 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ0_TXDLY_DQ3)
4766 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ0_TXDLY_DQ2)
4767 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ0_TXDLY_DQ1)
4768 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ0_TXDLY_DQ0));
4769 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ1, P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM3)
4770 | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM2)
4771 | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM1)
4772 | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM0)
4773 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ1_TXDLY_DQM3)
4774 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ1_TXDLY_DQM2)
4775 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ1_TXDLY_DQM1)
4776 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ1_TXDLY_DQM0));
4777 }
4778 else
4779 {
4780 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ0, P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ3)
4781 | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ2)
4782 | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ1)
4783 | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ0)
4784 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ0_TXDLY_DQ3)
4785 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ0_TXDLY_DQ2)
4786 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ0_TXDLY_DQ1)
4787 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ0_TXDLY_DQ0));
4788 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ1, P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM3)
4789 | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM2)
4790 | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM1)
4791 | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM0)
4792 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ1_TXDLY_DQM3)
4793 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ1_TXDLY_DQM2)
4794 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ1_TXDLY_DQM1)
4795 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ1_TXDLY_DQM0));
4796 }
4797 if (vGet_Div_Mode(p) == DIV4_MODE)
4798 {
4799 ucR0TxdlyOendq = 0x2;
4800 ucR0Txdlydq = 0x1;
4801 }
4802 else
4803 {
4804 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
4805 {
4806 ucR0TxdlyOendq = 0x6;
4807 ucR0Txdlydq = 0x1;
4808 }
4809 else
4810 {
4811 ucR0TxdlyOendq = 0x7;
4812 ucR0Txdlydq = 0x1;
4813 }
4814 }
4815 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ2, P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ2_DLY_OEN_DQ3)
4816 | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ2_DLY_OEN_DQ2)
4817 | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ2_DLY_OEN_DQ1)
4818 | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ2_DLY_OEN_DQ0)
4819 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ2_DLY_DQ3)
4820 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ2_DLY_DQ2)
4821 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ2_DLY_DQ1)
4822 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ2_DLY_DQ0));
4823 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ3, P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ3_DLY_OEN_DQM3)
4824 | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ3_DLY_OEN_DQM2)
4825 | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ3_DLY_OEN_DQM1)
4826 | P_Fld(ucR0TxdlyOendq, SHURK0_SELPH_DQ3_DLY_OEN_DQM0)
4827 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ3_DLY_DQM3)
4828 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ3_DLY_DQM2)
4829 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ3_DLY_DQM1)
4830 | P_Fld(ucR0Txdlydq, SHURK0_SELPH_DQ3_DLY_DQM0));
4831 }
4832 else
4833 {
4834 if (vGet_Div_Mode(p) == DIV4_MODE)
4835 {
4836 ucR1TxdlyOendq = 0x3;
4837 ucR1Txdlydq = 0x4;
4838 }
4839 else
4840 {
4841 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
4842 {
4843 ucR1TxdlyOendq = 0x1;
4844 ucR1Txdlydq = 0x2;
4845 }
4846 else
4847 {
4848 ucR1TxdlyOendq = 0x1;
4849 ucR1Txdlydq = 0x2;
4850 }
4851 }
4852 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
4853 {
4854 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ0, P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ3)
4855 | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ2)
4856 | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ1)
4857 | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ0)
4858 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ0_TX_DLY_R1DQ3)
4859 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ0_TX_DLY_R1DQ2)
4860 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ0_TX_DLY_R1DQ1)
4861 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ0_TX_DLY_R1DQ0));
4862 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ1, P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM3)
4863 | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM2)
4864 | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM1)
4865 | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM0)
4866 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ1_TX_DLY_R1DQM3)
4867 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ1_TX_DLY_R1DQM2)
4868 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ1_TX_DLY_R1DQM1)
4869 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ1_TX_DLY_R1DQM0));
4870 }
4871 else
4872 {
4873 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ0, P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ3)
4874 | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ2)
4875 | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ1)
4876 | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ0)
4877 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ0_TX_DLY_R1DQ3)
4878 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ0_TX_DLY_R1DQ2)
4879 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ0_TX_DLY_R1DQ1)
4880 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ0_TX_DLY_R1DQ0));
4881 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ1, P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM3)
4882 | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM2)
4883 | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM1)
4884 | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM0)
4885 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ1_TX_DLY_R1DQM3)
4886 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ1_TX_DLY_R1DQM2)
4887 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ1_TX_DLY_R1DQM1)
4888 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ1_TX_DLY_R1DQM0));
4889 }
4890 if (vGet_Div_Mode(p) == DIV4_MODE)
4891 {
4892 ucR1TxdlyOendq = 0x3;
4893 ucR1Txdlydq = 0x2;
4894 }
4895 else
4896 {
4897 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
4898 {
4899 ucR1TxdlyOendq = 0x7;
4900 ucR1Txdlydq = 0x2;
4901 }
4902 else
4903 {
4904 ucR1TxdlyOendq = 0x7;
4905 ucR1Txdlydq = 0x1;
4906 }
4907 }
4908 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ2, P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ3)
4909 | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ2)
4910 | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ1)
4911 | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ0)
4912 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ2_DLY_R1DQ3)
4913 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ2_DLY_R1DQ2)
4914 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ2_DLY_R1DQ1)
4915 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ2_DLY_R1DQ0));
4916 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ3, P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM3)
4917 | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM2)
4918 | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM1)
4919 | P_Fld(ucR1TxdlyOendq, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM0)
4920 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ3_DLY_R1DQM3)
4921 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ3_DLY_R1DQM2)
4922 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ3_DLY_R1DQM1)
4923 | P_Fld(ucR1Txdlydq, SHURK1_SELPH_DQ3_DLY_R1DQM0));
4924 }
4925
4926 if (eRank == RANK_0)
4927 {
4928 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
4929 {
4930
4931 u1R0B0Pi = 0x1e;
4932 u1R0B1Pi = 0x1e;
4933 }
4934 else
4935 {
4936
4937 u1R0B0Pi = 0x1a;
4938 u1R0B1Pi = 0x1a;
4939 }
4940 vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ7, P_Fld(u1R0B0Pi, SHU_R0_B0_DQ7_RK0_ARPI_DQM_B0)
4941 | P_Fld(u1R0B0Pi, SHU_R0_B0_DQ7_RK0_ARPI_DQ_B0));
4942 vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ7, P_Fld(u1R0B1Pi, SHU_R0_B1_DQ7_RK0_ARPI_DQM_B1)
4943 | P_Fld(u1R0B1Pi, SHU_R0_B1_DQ7_RK0_ARPI_DQ_B1));
4944 }
4945 else
4946 {
4947
4948 if (vGet_Div_Mode(p) == DIV4_MODE)
4949 {
4950
4951 u1R1B0Pi = 0x1b;
4952 u1R1B1Pi = 0x1b;
4953 }
4954 else
4955 {
4956 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
4957 {
4958
4959 u1R1B0Pi = 0x13;
4960 u1R1B1Pi = 0x12;
4961 }
4962 else
4963 {
4964
4965 u1R1B0Pi = 0x26;
4966 u1R1B1Pi = 0x26;
4967 }
4968 }
4969 vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ7, P_Fld(u1R1B0Pi, SHU_R1_B0_DQ7_RK1_ARPI_DQM_B0)
4970 | P_Fld(u1R1B0Pi, SHU_R1_B0_DQ7_RK1_ARPI_DQ_B0));
4971 vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ7, P_Fld(u1R1B1Pi, SHU_R1_B1_DQ7_RK1_ARPI_DQM_B1)
4972 | P_Fld(u1R1B1Pi, SHU_R1_B1_DQ7_RK1_ARPI_DQ_B1));
4973
4974 }
4975 }
4976
DramcSetting_LP4_TX_Delay_DDR800(DRAMC_CTX_T * p,DRAM_RANK_T eRank)4977 static void DramcSetting_LP4_TX_Delay_DDR800(DRAMC_CTX_T *p, DRAM_RANK_T eRank)
4978 {
4979 if (eRank == RANK_0)
4980 {
4981 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
4982 {
4983 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ0, P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ3)
4984 | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ2)
4985 | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ1)
4986 | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ0)
4987 | P_Fld(0x4, SHURK0_SELPH_DQ0_TXDLY_DQ3)
4988 | P_Fld(0x4, SHURK0_SELPH_DQ0_TXDLY_DQ2)
4989 | P_Fld(0x4, SHURK0_SELPH_DQ0_TXDLY_DQ1)
4990 | P_Fld(0x4, SHURK0_SELPH_DQ0_TXDLY_DQ0));
4991 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ1, P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM3)
4992 | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM2)
4993 | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM1)
4994 | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM0)
4995 | P_Fld(0x4, SHURK0_SELPH_DQ1_TXDLY_DQM3)
4996 | P_Fld(0x4, SHURK0_SELPH_DQ1_TXDLY_DQM2)
4997 | P_Fld(0x4, SHURK0_SELPH_DQ1_TXDLY_DQM1)
4998 | P_Fld(0x4, SHURK0_SELPH_DQ1_TXDLY_DQM0));
4999 }
5000 else
5001 {
5002 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ0, P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ3)
5003 | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ2)
5004 | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ1)
5005 | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ0)
5006 | P_Fld(0x4, SHURK0_SELPH_DQ0_TXDLY_DQ3)
5007 | P_Fld(0x4, SHURK0_SELPH_DQ0_TXDLY_DQ2)
5008 | P_Fld(0x4, SHURK0_SELPH_DQ0_TXDLY_DQ1)
5009 | P_Fld(0x4, SHURK0_SELPH_DQ0_TXDLY_DQ0));
5010 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ1, P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM3)
5011 | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM2)
5012 | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM1)
5013 | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM0)
5014 | P_Fld(0x4, SHURK0_SELPH_DQ1_TXDLY_DQM3)
5015 | P_Fld(0x4, SHURK0_SELPH_DQ1_TXDLY_DQM2)
5016 | P_Fld(0x4, SHURK0_SELPH_DQ1_TXDLY_DQM1)
5017 | P_Fld(0x4, SHURK0_SELPH_DQ1_TXDLY_DQM0));
5018 }
5019
5020 if (vGet_DDR800_Mode(p) == DDR800_CLOSE_LOOP)
5021 {
5022
5023 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ2, P_Fld(0x2, SHURK0_SELPH_DQ2_DLY_OEN_DQ3)
5024 | P_Fld(0x2, SHURK0_SELPH_DQ2_DLY_OEN_DQ2)
5025 | P_Fld(0x2, SHURK0_SELPH_DQ2_DLY_OEN_DQ1)
5026 | P_Fld(0x2, SHURK0_SELPH_DQ2_DLY_OEN_DQ0)
5027 | P_Fld(0x1, SHURK0_SELPH_DQ2_DLY_DQ3)
5028 | P_Fld(0x1, SHURK0_SELPH_DQ2_DLY_DQ2)
5029 | P_Fld(0x1, SHURK0_SELPH_DQ2_DLY_DQ1)
5030 | P_Fld(0x1, SHURK0_SELPH_DQ2_DLY_DQ0));
5031 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ3, P_Fld(0x2, SHURK0_SELPH_DQ3_DLY_OEN_DQM3)
5032 | P_Fld(0x2, SHURK0_SELPH_DQ3_DLY_OEN_DQM2)
5033 | P_Fld(0x2, SHURK0_SELPH_DQ3_DLY_OEN_DQM1)
5034 | P_Fld(0x2, SHURK0_SELPH_DQ3_DLY_OEN_DQM0)
5035 | P_Fld(0x1, SHURK0_SELPH_DQ3_DLY_DQM3)
5036 | P_Fld(0x1, SHURK0_SELPH_DQ3_DLY_DQM2)
5037 | P_Fld(0x1, SHURK0_SELPH_DQ3_DLY_DQM1)
5038 | P_Fld(0x1, SHURK0_SELPH_DQ3_DLY_DQM0));
5039 }
5040 else
5041 {
5042
5043 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ2, P_Fld(0x3, SHURK0_SELPH_DQ2_DLY_OEN_DQ3)
5044 | P_Fld(0x3, SHURK0_SELPH_DQ2_DLY_OEN_DQ2)
5045 | P_Fld(0x3, SHURK0_SELPH_DQ2_DLY_OEN_DQ1)
5046 | P_Fld(0x3, SHURK0_SELPH_DQ2_DLY_OEN_DQ0)
5047 | P_Fld(0x2, SHURK0_SELPH_DQ2_DLY_DQ3)
5048 | P_Fld(0x2, SHURK0_SELPH_DQ2_DLY_DQ2)
5049 | P_Fld(0x2, SHURK0_SELPH_DQ2_DLY_DQ1)
5050 | P_Fld(0x2, SHURK0_SELPH_DQ2_DLY_DQ0));
5051 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ3, P_Fld(0x3, SHURK0_SELPH_DQ3_DLY_OEN_DQM3)
5052 | P_Fld(0x3, SHURK0_SELPH_DQ3_DLY_OEN_DQM2)
5053 | P_Fld(0x3, SHURK0_SELPH_DQ3_DLY_OEN_DQM1)
5054 | P_Fld(0x3, SHURK0_SELPH_DQ3_DLY_OEN_DQM0)
5055 | P_Fld(0x2, SHURK0_SELPH_DQ3_DLY_DQM3)
5056 | P_Fld(0x2, SHURK0_SELPH_DQ3_DLY_DQM2)
5057 | P_Fld(0x2, SHURK0_SELPH_DQ3_DLY_DQM1)
5058 | P_Fld(0x2, SHURK0_SELPH_DQ3_DLY_DQM0));
5059 }
5060 }
5061 else
5062 {
5063 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
5064 {
5065 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ0, P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ3)
5066 | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ2)
5067 | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ1)
5068 | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ0)
5069 | P_Fld(0x4, SHURK1_SELPH_DQ0_TX_DLY_R1DQ3)
5070 | P_Fld(0x4, SHURK1_SELPH_DQ0_TX_DLY_R1DQ2)
5071 | P_Fld(0x4, SHURK1_SELPH_DQ0_TX_DLY_R1DQ1)
5072 | P_Fld(0x4, SHURK1_SELPH_DQ0_TX_DLY_R1DQ0));
5073 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ1, P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM3)
5074 | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM2)
5075 | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM1)
5076 | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM0)
5077 | P_Fld(0x4, SHURK1_SELPH_DQ1_TX_DLY_R1DQM3)
5078 | P_Fld(0x4, SHURK1_SELPH_DQ1_TX_DLY_R1DQM2)
5079 | P_Fld(0x4, SHURK1_SELPH_DQ1_TX_DLY_R1DQM1)
5080 | P_Fld(0x4, SHURK1_SELPH_DQ1_TX_DLY_R1DQM0));
5081 }
5082 else
5083 {
5084 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ0, P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ3)
5085 | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ2)
5086 | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ1)
5087 | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ0)
5088 | P_Fld(0x4, SHURK1_SELPH_DQ0_TX_DLY_R1DQ3)
5089 | P_Fld(0x4, SHURK1_SELPH_DQ0_TX_DLY_R1DQ2)
5090 | P_Fld(0x4, SHURK1_SELPH_DQ0_TX_DLY_R1DQ1)
5091 | P_Fld(0x4, SHURK1_SELPH_DQ0_TX_DLY_R1DQ0));
5092 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ1, P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM3)
5093 | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM2)
5094 | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM1)
5095 | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM0)
5096 | P_Fld(0x4, SHURK1_SELPH_DQ1_TX_DLY_R1DQM3)
5097 | P_Fld(0x4, SHURK1_SELPH_DQ1_TX_DLY_R1DQM2)
5098 | P_Fld(0x4, SHURK1_SELPH_DQ1_TX_DLY_R1DQM1)
5099 | P_Fld(0x4, SHURK1_SELPH_DQ1_TX_DLY_R1DQM0));
5100 }
5101
5102 if (vGet_DDR800_Mode(p) == DDR800_CLOSE_LOOP)
5103 {
5104
5105 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ2, P_Fld(0x2, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ3)
5106 | P_Fld(0x2, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ2)
5107 | P_Fld(0x2, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ1)
5108 | P_Fld(0x2, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ0)
5109 | P_Fld(0x1, SHURK1_SELPH_DQ2_DLY_R1DQ3)
5110 | P_Fld(0x1, SHURK1_SELPH_DQ2_DLY_R1DQ2)
5111 | P_Fld(0x1, SHURK1_SELPH_DQ2_DLY_R1DQ1)
5112 | P_Fld(0x1, SHURK1_SELPH_DQ2_DLY_R1DQ0));
5113 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ3, P_Fld(0x2, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM3)
5114 | P_Fld(0x2, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM2)
5115 | P_Fld(0x2, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM1)
5116 | P_Fld(0x2, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM0)
5117 | P_Fld(0x1, SHURK1_SELPH_DQ3_DLY_R1DQM3)
5118 | P_Fld(0x1, SHURK1_SELPH_DQ3_DLY_R1DQM2)
5119 | P_Fld(0x1, SHURK1_SELPH_DQ3_DLY_R1DQM1)
5120 | P_Fld(0x1, SHURK1_SELPH_DQ3_DLY_R1DQM0));
5121 }
5122 else
5123 {
5124
5125 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ2, P_Fld(0x3, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ3)
5126 | P_Fld(0x3, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ2)
5127 | P_Fld(0x3, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ1)
5128 | P_Fld(0x3, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ0)
5129 | P_Fld(0x2, SHURK1_SELPH_DQ2_DLY_R1DQ3)
5130 | P_Fld(0x2, SHURK1_SELPH_DQ2_DLY_R1DQ2)
5131 | P_Fld(0x2, SHURK1_SELPH_DQ2_DLY_R1DQ1)
5132 | P_Fld(0x2, SHURK1_SELPH_DQ2_DLY_R1DQ0));
5133 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ3, P_Fld(0x3, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM3)
5134 | P_Fld(0x3, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM2)
5135 | P_Fld(0x3, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM1)
5136 | P_Fld(0x3, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM0)
5137 | P_Fld(0x2, SHURK1_SELPH_DQ3_DLY_R1DQM3)
5138 | P_Fld(0x2, SHURK1_SELPH_DQ3_DLY_R1DQM2)
5139 | P_Fld(0x2, SHURK1_SELPH_DQ3_DLY_R1DQM1)
5140 | P_Fld(0x2, SHURK1_SELPH_DQ3_DLY_R1DQM0));
5141 }
5142 }
5143
5144 if (vGet_DDR800_Mode(p) == DDR800_CLOSE_LOOP)
5145 {
5146
5147 vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ7, P_Fld(0x1a, SHU_R0_B0_DQ7_RK0_ARPI_DQM_B0)
5148 | P_Fld(0x1a, SHU_R0_B0_DQ7_RK0_ARPI_DQ_B0));
5149 vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ7, P_Fld(0x1a, SHU_R0_B1_DQ7_RK0_ARPI_DQM_B1)
5150 | P_Fld(0x1a, SHU_R0_B1_DQ7_RK0_ARPI_DQ_B1));
5151 vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ7, P_Fld(0x25, SHU_R1_B0_DQ7_RK1_ARPI_DQM_B0)
5152 | P_Fld(0x25, SHU_R1_B0_DQ7_RK1_ARPI_DQ_B0));
5153 vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ7, P_Fld(0x25, SHU_R1_B1_DQ7_RK1_ARPI_DQM_B1)
5154 | P_Fld(0x25, SHU_R1_B1_DQ7_RK1_ARPI_DQ_B1));
5155 }
5156 else
5157 {
5158
5159 vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ7, P_Fld(0x0, SHU_R0_B0_DQ7_RK0_ARPI_DQM_B0)
5160 | P_Fld(0x0, SHU_R0_B0_DQ7_RK0_ARPI_DQ_B0));
5161 vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ7, P_Fld(0x0, SHU_R0_B1_DQ7_RK0_ARPI_DQM_B1)
5162 | P_Fld(0x0, SHU_R0_B1_DQ7_RK0_ARPI_DQ_B1));
5163 vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ7, P_Fld(0x0, SHU_R1_B0_DQ7_RK1_ARPI_DQM_B0)
5164 | P_Fld(0x0, SHU_R1_B0_DQ7_RK1_ARPI_DQ_B0));
5165 vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ7, P_Fld(0x0, SHU_R1_B1_DQ7_RK1_ARPI_DQM_B1)
5166 | P_Fld(0x0, SHU_R1_B1_DQ7_RK1_ARPI_DQ_B1));
5167 }
5168 }
5169
DramcSetting_Olympus_LP4_ByteMode_DDR1600(DRAMC_CTX_T * p)5170 static void DramcSetting_Olympus_LP4_ByteMode_DDR1600(DRAMC_CTX_T *p)
5171 {
5172 U8 ucMCKTxdlyOendqs = 0, ucMCKTxdlydqs = 0;
5173 U8 ucUITxdlyOendqs = 0, ucUITxdlydqs = 0;
5174
5175
5176 #if LEGACY_TDQSCK_PRECAL
5177 LegacyPreCalLP4_DDR1600(p);
5178 #endif
5179 #if LEGACY_TX_TRACK
5180 LegacyTxTrackLP4_DDR1600(p);
5181 #endif
5182
5183 //vIO32WriteFldAlign(DRAMC_REG_SHU_CONF2, 0x32, SHU_CONF2_FSPCHG_PRDCNT); //ACTiming related -> set in UpdateACTiming_Reg()
5184 //vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL, P_Fld(0x0, SHU_CKECTRL_TCKESRX)); //from CF review, only work for DDR3/4 (Darren)
5185 //| P_Fld(0x2, SHU_CKECTRL_CKEPRD));
5186 vIO32WriteFldMulti(DRAMC_REG_SHU_ODTCTRL, P_Fld(0x0, SHU_ODTCTRL_RODTE)
5187 | P_Fld(0x0, SHU_ODTCTRL_RODTE2)
5188 //| P_Fld(0x2, SHU_ODTCTRL_RODT) //Set in UpdateACTimingReg()
5189 #ifdef LOOPBACK_TEST
5190 | P_Fld(0x1, SHU_ODTCTRL_ROEN));
5191 #else
5192 | P_Fld(0x0, SHU_ODTCTRL_ROEN));
5193 #endif
5194 vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ7, 0x0, SHU_B0_DQ7_R_DMRODTEN_B0);
5195 vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ7, 0x0, SHU_B1_DQ7_R_DMRODTEN_B1);
5196
5197 if (vGet_Div_Mode(p) == DIV4_MODE)
5198 {
5199 ucMCKTxdlyOendqs = 0x3;
5200 ucMCKTxdlydqs = 0x4;
5201 ucUITxdlyOendqs = 0x2;
5202 ucUITxdlydqs = 0x1;
5203 }
5204 else
5205 {
5206 ucMCKTxdlyOendqs = 0x1;
5207 ucMCKTxdlydqs = 0x2;
5208 ucUITxdlyOendqs = 0x6;
5209 ucUITxdlydqs = 0x1;
5210 }
5211
5212
5213 vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(ucMCKTxdlyOendqs, SHU_SELPH_DQS0_TXDLY_OEN_DQS3)
5214 | P_Fld(ucMCKTxdlyOendqs, SHU_SELPH_DQS0_TXDLY_OEN_DQS2)
5215 | P_Fld(ucMCKTxdlyOendqs, SHU_SELPH_DQS0_TXDLY_OEN_DQS1)
5216 | P_Fld(ucMCKTxdlyOendqs, SHU_SELPH_DQS0_TXDLY_OEN_DQS0)
5217 | P_Fld(ucMCKTxdlydqs, SHU_SELPH_DQS0_TXDLY_DQS3)
5218 | P_Fld(ucMCKTxdlydqs, SHU_SELPH_DQS0_TXDLY_DQS2)
5219 | P_Fld(ucMCKTxdlydqs, SHU_SELPH_DQS0_TXDLY_DQS1)
5220 | P_Fld(ucMCKTxdlydqs, SHU_SELPH_DQS0_TXDLY_DQS0));
5221
5222 vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(ucUITxdlyOendqs, SHU_SELPH_DQS1_DLY_OEN_DQS3)
5223 | P_Fld(ucUITxdlyOendqs, SHU_SELPH_DQS1_DLY_OEN_DQS2)
5224 | P_Fld(ucUITxdlyOendqs, SHU_SELPH_DQS1_DLY_OEN_DQS1)
5225 | P_Fld(ucUITxdlyOendqs, SHU_SELPH_DQS1_DLY_OEN_DQS0)
5226 | P_Fld(ucUITxdlydqs, SHU_SELPH_DQS1_DLY_DQS3)
5227 | P_Fld(ucUITxdlydqs, SHU_SELPH_DQS1_DLY_DQS2)
5228 | P_Fld(ucUITxdlydqs, SHU_SELPH_DQS1_DLY_DQS1)
5229 | P_Fld(ucUITxdlydqs, SHU_SELPH_DQS1_DLY_DQS0));
5230
5231 vIO32WriteFldAlign(DRAMC_REG_SHU_DQS2DQ_TX, 0x4, SHU_DQS2DQ_TX_OE2DQ_OFFSET);
5232
5233 vIO32WriteFldMulti(DRAMC_REG_SHURK0_PI, P_Fld(0x1a, SHURK0_PI_RK0_ARPI_DQM_B1)
5234 | P_Fld(0x1a, SHURK0_PI_RK0_ARPI_DQM_B0)
5235 | P_Fld(0x1a, SHURK0_PI_RK0_ARPI_DQ_B1)
5236 | P_Fld(0x1a, SHURK0_PI_RK0_ARPI_DQ_B0));
5237
5238 if (p->freqGroup == 400)
5239 {
5240 DramcSetting_LP4_TX_Delay_DDR800(p, RANK_0);
5241 DramcSetting_LP4_TX_Delay_DDR800(p, RANK_1);
5242 }
5243 else
5244 {
5245 DramcSetting_LP4_TX_Delay_DDR1600(p, RANK_0);
5246 DramcSetting_LP4_TX_Delay_DDR1600(p, RANK_1);
5247 }
5248
5249 vIO32WriteFldMulti(DRAMC_REG_SHURK1_PI, P_Fld(0x1e, SHURK1_PI_RK1_ARPI_DQM_B1)
5250 | P_Fld(0x1e, SHURK1_PI_RK1_ARPI_DQM_B0)
5251 | P_Fld(0x1e, SHURK1_PI_RK1_ARPI_DQ_B1)
5252 | P_Fld(0x1e, SHURK1_PI_RK1_ARPI_DQ_B0));
5253
5254 #if LEGACY_GATING_DLY
5255 if (p->freqGroup == 400)
5256 LegacyGatingDlyLP4_DDR800(p);
5257 else
5258 LegacyGatingDlyLP4_DDR1600(p);
5259 #endif
5260
5261 vIO32WriteFldMulti(DRAMC_REG_SHU_DQSG_RETRY, P_Fld(0x3, SHU_DQSG_RETRY_R_DQSIENLAT)
5262 | P_Fld(0x0, SHU_DQSG_RETRY_R_DDR1866_PLUS));
5263
5264
5265 vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ5, 0x5, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0);
5266 //vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ6, P_Fld(0x1, SHU_B0_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B0)
5267 // | P_Fld(0x0, SHU_B0_DQ6_RG_ARPI_MIDPI_EN_B0));
5268 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
5269 {
5270 vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ7, P_Fld(0x1, SHU_B0_DQ7_MIDPI_DIV4_ENABLE)
5271 | P_Fld(0x0, SHU_B0_DQ7_MIDPI_ENABLE));
5272 }
5273 else
5274 {
5275 vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0)
5276 | P_Fld(0x0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0)
5277 | P_Fld(0x1, SHU_B0_DQ7_MIDPI_DIV4_ENABLE)
5278 | P_Fld(0x0, SHU_B0_DQ7_MIDPI_ENABLE));
5279 }
5280 vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ5, 0x5, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1);
5281 //vIO32WriteFldMulti(DDRPHY_SHU_B1_DQ6, P_Fld(0x1, SHU_B1_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B1)
5282 // | P_Fld(0x0, SHU_B1_DQ6_RG_ARPI_MIDPI_EN_B1));
5283 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
5284 {}
5285 else
5286 {
5287 vIO32WriteFldMulti(DDRPHY_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1)
5288 | P_Fld(0x0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1));
5289 }
5290
5291 #if LEGACY_RX_DLY
5292 if (p->freqGroup == 400)
5293 LegacyRxDly_LP4_DDR800(p);
5294 else
5295 LegacyRxDly_LP4_DDR1600(p);
5296 #endif
5297 #if LEGACY_DELAY_CELL
5298 LegacyDlyCellInitLP4_DDR1600(p);
5299 #endif
5300
5301 if (vGet_Div_Mode(p) == DIV4_MODE)
5302 {
5303 #if 0
5304 if (p->freqGroup == 400)
5305 {
5306 vIO32WriteFldMulti(DRAMC_REG_SHU_RANKCTL, P_Fld(0x6, SHU_RANKCTL_RANKINCTL_PHY)
5307 | P_Fld(0x4, SHU_RANKCTL_RANKINCTL_ROOT1)
5308 | P_Fld(0x4, SHU_RANKCTL_RANKINCTL));
5309 }
5310 else
5311 {
5312 vIO32WriteFldMulti(DRAMC_REG_SHU_RANKCTL, P_Fld(0x6, SHU_RANKCTL_RANKINCTL_PHY)
5313 | P_Fld(0x4, SHU_RANKCTL_RANKINCTL_ROOT1)
5314 | P_Fld(0x4, SHU_RANKCTL_RANKINCTL));
5315 }
5316 #endif
5317
5318 vIO32WriteFldMulti(DRAMC_REG_SHU_CONF0, P_Fld(0x0, SHU_CONF0_DM64BITEN)
5319 | P_Fld(0x1, SHU_CONF0_FDIV2)
5320 | P_Fld(0x0, SHU_CONF0_FREQDIV4)
5321 | P_Fld(0x0, SHU_CONF0_DUALSCHEN)
5322 | P_Fld(0x1, SHU_CONF0_WDATRGO));
5323 #if 0
5324 vIO32WriteFldMulti(DRAMC_REG_SHU_CONF0, P_Fld(0x1, SHU_CONF0_DM64BITEN)
5325 | P_Fld(0x0, SHU_CONF0_FDIV2)
5326 | P_Fld(0x1, SHU_CONF0_FREQDIV4)
5327 | P_Fld(0x1, SHU_CONF0_DUALSCHEN)
5328 | P_Fld(0x0, SHU_CONF0_WDATRGO));
5329 #endif
5330
5331 #if (!CMD_CKE_WORKAROUND_FIX)
5332 vIO32WriteFldAlign(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, 0x7, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_DYN_GATING_SEL);
5333 vIO32WriteFldAlign(DRAMC_REG_SHU_SELPH_CA1, 0x1, SHU_SELPH_CA1_TXDLY_CKE);
5334 vIO32WriteFldAlign(DRAMC_REG_SHU_SELPH_CA2, 0x1, SHU_SELPH_CA2_TXDLY_CKE1);
5335 #endif
5336
5337 vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ7, P_Fld(0x1, SHU_B0_DQ7_R_DMRDSEL_DIV2_OPT)
5338 | P_Fld(0x1, SHU_B0_DQ7_R_DMRDSEL_LOBYTE_OPT)
5339 | P_Fld(0x0, SHU_B0_DQ7_R_DMRDSEL_HIBYTE_OPT));
5340
5341 vIO32WriteFldMulti(DRAMC_REG_SHU_PIPE, P_Fld(0x1, SHU_PIPE_READ_START_EXTEND1)
5342 | P_Fld(0x1, SHU_PIPE_DLE_LAST_EXTEND1)
5343 | P_Fld(0x1, SHU_PIPE_READ_START_EXTEND2)
5344 | P_Fld(0x1, SHU_PIPE_DLE_LAST_EXTEND2)
5345 | P_Fld(0x0, SHU_PIPE_READ_START_EXTEND3)
5346 | P_Fld(0x0, SHU_PIPE_DLE_LAST_EXTEND3));
5347 }
5348 #if 0
5349 else
5350 {
5351
5352 vIO32WriteFldMulti(DRAMC_REG_SHU_RANKCTL, P_Fld(0x2, SHU_RANKCTL_RANKINCTL_PHY)
5353 | P_Fld(0x0, SHU_RANKCTL_RANKINCTL_ROOT1)
5354 | P_Fld(0x0, SHU_RANKCTL_RANKINCTL));
5355 }
5356 #endif
5357 }
5358
5359
5360
DramcSetting_Olympus_LP4_ByteMode(DRAMC_CTX_T * p)5361 void DramcSetting_Olympus_LP4_ByteMode(DRAMC_CTX_T *p)
5362 {
5363
5364 U8 u1CAP_SEL;
5365 U8 u1MIDPICAP_SEL;
5366 //U16 u2SDM_PCW = 0;
5367 U8 u1TXDLY_CMD;
5368 U8 u1TAIL_LAT;
5369
5370 AutoRefreshCKEOff(p);
5371
5372 DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
5373
5374 vIO32WriteFldMulti_All(DDRPHY_CKMUX_SEL, P_Fld(0x1, CKMUX_SEL_R_PHYCTRLMUX)
5375 | P_Fld(0x1, CKMUX_SEL_R_PHYCTRLDCM));
5376 DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
5377
5378
5379 vIO32WriteFldAlign(DDRPHY_MISC_CG_CTRL0, 0x1, MISC_CG_CTRL0_W_CHG_MEM);
5380
5381 vIO32WriteFldAlign(DDRPHY_MISC_CG_CTRL0, 0x0, MISC_CG_CTRL0_CLK_MEM_SEL);
5382
5383 vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRDSEL_DIV2_OPT)
5384 | P_Fld(0x0, SHU_B0_DQ7_R_DMRDSEL_LOBYTE_OPT)
5385 | P_Fld(0x0, SHU_B0_DQ7_R_DMRDSEL_HIBYTE_OPT));
5386
5387
5388 #if APOLLO_SPECIFIC
5389 vIO32WriteFldAlign(DRAMC_REG_RKCFG, 1, RKCFG_CS1FORCE0);
5390 #endif
5391
5392 vIO32WriteFldMulti(DDRPHY_MISC_SPM_CTRL1, P_Fld(0x0, MISC_SPM_CTRL1_RG_ARDMSUS_10) | P_Fld(0x0, MISC_SPM_CTRL1_RG_ARDMSUS_10_B0)
5393 | P_Fld(0x0, MISC_SPM_CTRL1_RG_ARDMSUS_10_B1) | P_Fld(0x0, MISC_SPM_CTRL1_RG_ARDMSUS_10_CA));
5394
5395 vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL2, 0x0, MISC_SPM_CTRL2_PHY_SPM_CTL2);
5396 vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL0, 0x0, MISC_SPM_CTRL0_PHY_SPM_CTL0);
5397 vIO32WriteFldAlign(DDRPHY_MISC_CG_CTRL2, 0x6003bf, MISC_CG_CTRL2_RG_MEM_DCM_CTL);
5398 vIO32WriteFldAlign(DDRPHY_MISC_CG_CTRL4, 0x333f3f00, MISC_CG_CTRL4_R_PHY_MCK_CG_CTRL);
5399 vIO32WriteFldMulti(DDRPHY_SHU_PLL1, P_Fld(0x1, SHU_PLL1_R_SHU_AUTO_PLL_MUX)
5400 | P_Fld(0x7, SHU_PLL1_SHU1_PLL1_RFU));
5401 vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ7, P_Fld(0x1, SHU_B0_DQ7_MIDPI_ENABLE)
5402 | P_Fld(0x0, SHU_B0_DQ7_MIDPI_DIV4_ENABLE)
5403 | P_Fld(0, SHU_B0_DQ7_R_DMRANKRXDVS_B0));
5404 vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ7, 0, SHU_B1_DQ7_R_DMRANKRXDVS_B1);
5405 //vIO32WriteFldAlign(DDRPHY_SHU_PLL4, 0xfe, SHU_PLL4_RG_RPHYPLL_RESERVED);
5406 vIO32WriteFldMulti(DDRPHY_SHU_PLL4, P_Fld(0x1, SHU_PLL4_RG_RPHYPLL_IBIAS) | P_Fld(0x1, SHU_PLL4_RG_RPHYPLL_ICHP) | P_Fld(0x1, SHU_PLL4_RG_RPHYPLL_FS));
5407 //vIO32WriteFldAlign(DDRPHY_SHU_PLL6, 0xfe, SHU_PLL6_RG_RCLRPLL_RESERVED);
5408 vIO32WriteFldMulti(DDRPHY_SHU_PLL6, P_Fld(0x1, SHU_PLL6_RG_RCLRPLL_IBIAS) | P_Fld(0x1, SHU_PLL6_RG_RCLRPLL_ICHP) | P_Fld(0x1, SHU_PLL6_RG_RCLRPLL_FS));
5409 vIO32WriteFldAlign(DDRPHY_SHU_PLL14, 0x0, SHU_PLL14_RG_RPHYPLL_SDM_SSC_PH_INIT);
5410 vIO32WriteFldAlign(DDRPHY_SHU_PLL20, 0x0, SHU_PLL20_RG_RCLRPLL_SDM_SSC_PH_INIT);
5411 vIO32WriteFldMulti(DDRPHY_CA_CMD2, P_Fld(0x0, CA_CMD2_RG_TX_ARCMD_OE_DIS)
5412 | P_Fld(0x0, CA_CMD2_RG_TX_ARCMD_ODTEN_DIS)
5413 | P_Fld(0x0, CA_CMD2_RG_TX_ARCLK_OE_DIS)
5414 | P_Fld(0x0, CA_CMD2_RG_TX_ARCLK_ODTEN_DIS));
5415 vIO32WriteFldMulti(DDRPHY_B0_DQ2, P_Fld(0x0, B0_DQ2_RG_TX_ARDQ_OE_DIS_B0)
5416 | P_Fld(0x0, B0_DQ2_RG_TX_ARDQ_ODTEN_DIS_B0)
5417 | P_Fld(0x0, B0_DQ2_RG_TX_ARDQS0_OE_DIS_B0)
5418 | P_Fld(0x0, B0_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B0));
5419 vIO32WriteFldMulti(DDRPHY_B1_DQ2, P_Fld(0x0, B1_DQ2_RG_TX_ARDQ_OE_DIS_B1)
5420 | P_Fld(0x0, B1_DQ2_RG_TX_ARDQ_ODTEN_DIS_B1)
5421 | P_Fld(0x0, B1_DQ2_RG_TX_ARDQS0_OE_DIS_B1)
5422 | P_Fld(0x0, B1_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B1));
5423 #if 0
5424 vIO32WriteFldAlign(DDRPHY_B0_DQ9, 0x0, B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0);
5425 vIO32WriteFldAlign(DDRPHY_B1_DQ9, 0x7, B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1);
5426 vIO32WriteFldAlign(DDRPHY_CA_CMD10, 0x0, CA_CMD10_R_IN_GATE_EN_LOW_OPT_CA);
5427 #endif
5428 vIO32WriteFldAlign(DDRPHY_B0_DQ9, 0x1, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0);
5429 vIO32WriteFldAlign(DDRPHY_B1_DQ9, 0x1, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1);
5430 vIO32WriteFldAlign(DDRPHY_CA_CMD10, 0x0, CA_CMD10_R_DMRXDVS_RDSEL_LAT_CA);
5431
5432 vIO32WriteFldAlign(DDRPHY_B0_RXDVS0, 0x1, B0_RXDVS0_R_RX_DLY_TRACK_CG_EN_B0);
5433 vIO32WriteFldAlign(DDRPHY_B1_RXDVS0, 0x1, B1_RXDVS0_R_RX_DLY_TRACK_CG_EN_B1);
5434 vIO32WriteFldAlign(DDRPHY_B0_RXDVS0, 0x1, B0_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B0);
5435 vIO32WriteFldAlign(DDRPHY_B1_RXDVS0, 0x1, B1_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B1);
5436 vIO32WriteFldAlign(DDRPHY_R0_B0_RXDVS2, 0x1, R0_B0_RXDVS2_R_RK0_DVS_FDLY_MODE_B0);
5437 vIO32WriteFldAlign(DDRPHY_R1_B0_RXDVS2, 0x1, R1_B0_RXDVS2_R_RK1_DVS_FDLY_MODE_B0);
5438 vIO32WriteFldAlign(DDRPHY_R0_B1_RXDVS2, 0x1, R0_B1_RXDVS2_R_RK0_DVS_FDLY_MODE_B1);
5439 vIO32WriteFldAlign(DDRPHY_R1_B1_RXDVS2, 0x1, R1_B1_RXDVS2_R_RK1_DVS_FDLY_MODE_B1);
5440 vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ5, 0x3, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0);
5441 vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ5, 0x3, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1);
5442 #if LEGACY_RX_DLY
5443 LegacyRxDly_LP4_DDR3200(p);
5444 #endif
5445 vIO32WriteFldMulti(DDRPHY_R0_B0_RXDVS1, P_Fld(0x2, R0_B0_RXDVS1_R_RK0_B0_DVS_TH_LEAD)
5446 | P_Fld(0x2, R0_B0_RXDVS1_R_RK0_B0_DVS_TH_LAG));
5447 vIO32WriteFldMulti(DDRPHY_R1_B0_RXDVS1, P_Fld(0x2, R1_B0_RXDVS1_R_RK1_B0_DVS_TH_LEAD)
5448 | P_Fld(0x2, R1_B0_RXDVS1_R_RK1_B0_DVS_TH_LAG));
5449 vIO32WriteFldMulti(DDRPHY_R0_B1_RXDVS1, P_Fld(0x2, R0_B1_RXDVS1_R_RK0_B1_DVS_TH_LEAD)
5450 | P_Fld(0x2, R0_B1_RXDVS1_R_RK0_B1_DVS_TH_LAG));
5451 vIO32WriteFldMulti(DDRPHY_R1_B1_RXDVS1, P_Fld(0x2, R1_B1_RXDVS1_R_RK1_B1_DVS_TH_LEAD)
5452 | P_Fld(0x2, R1_B1_RXDVS1_R_RK1_B1_DVS_TH_LAG));
5453
5454 vIO32WriteFldMulti(DDRPHY_R0_B0_RXDVS2, P_Fld(0x2, R0_B0_RXDVS2_R_RK0_DVS_MODE_B0)
5455 | P_Fld(0x1, R0_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0)
5456 | P_Fld(0x1, R0_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0));
5457 vIO32WriteFldMulti(DDRPHY_R1_B0_RXDVS2, P_Fld(0x2, R1_B0_RXDVS2_R_RK1_DVS_MODE_B0)
5458 | P_Fld(0x1, R1_B0_RXDVS2_R_RK1_RX_DLY_RIS_TRACK_GATE_ENA_B0)
5459 | P_Fld(0x1, R1_B0_RXDVS2_R_RK1_RX_DLY_FAL_TRACK_GATE_ENA_B0));
5460 vIO32WriteFldMulti(DDRPHY_R0_B1_RXDVS2, P_Fld(0x2, R0_B1_RXDVS2_R_RK0_DVS_MODE_B1)
5461 | P_Fld(0x1, R0_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1)
5462 | P_Fld(0x1, R0_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1));
5463 vIO32WriteFldMulti(DDRPHY_R1_B1_RXDVS2, P_Fld(0x2, R1_B1_RXDVS2_R_RK1_DVS_MODE_B1)
5464 | P_Fld(0x1, R1_B1_RXDVS2_R_RK1_RX_DLY_RIS_TRACK_GATE_ENA_B1)
5465 | P_Fld(0x1, R1_B1_RXDVS2_R_RK1_RX_DLY_FAL_TRACK_GATE_ENA_B1));
5466
5467 vIO32WriteFldAlign(DDRPHY_B0_RXDVS0, 0x0, B0_RXDVS0_R_RX_DLY_TRACK_CG_EN_B0);
5468 vIO32WriteFldAlign(DDRPHY_B1_RXDVS0, 0x0, B1_RXDVS0_R_RX_DLY_TRACK_CG_EN_B1);
5469 vIO32WriteFldAlign(DDRPHY_B0_DQ9, 0x1, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0);
5470 vIO32WriteFldAlign(DDRPHY_B1_DQ9, 0x1, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1);
5471 #if LEGACY_DELAY_CELL
5472 LegacyDlyCellInitLP4_DDR3200(p);
5473 #endif
5474 vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ7, P_Fld(0x1f, SHU_R0_B0_DQ7_RK0_ARPI_DQM_B0)
5475 | P_Fld(0x1f, SHU_R0_B0_DQ7_RK0_ARPI_DQ_B0));
5476 vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ7, P_Fld(0x1f, SHU_R0_B1_DQ7_RK0_ARPI_DQM_B1)
5477 | P_Fld(0x1f, SHU_R0_B1_DQ7_RK0_ARPI_DQ_B1));
5478 vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ7, P_Fld(0x1f, SHU_R1_B0_DQ7_RK1_ARPI_DQM_B0)
5479 | P_Fld(0x1f, SHU_R1_B0_DQ7_RK1_ARPI_DQ_B0));
5480 vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ7, P_Fld(0x1f, SHU_R1_B1_DQ7_RK1_ARPI_DQM_B1)
5481 | P_Fld(0x1f, SHU_R1_B1_DQ7_RK1_ARPI_DQ_B1));
5482 vIO32WriteFldMulti(DDRPHY_B0_DQ4, P_Fld(0x10, B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0)
5483 | P_Fld(0x10, B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0));
5484 vIO32WriteFldMulti(DDRPHY_B0_DQ5, P_Fld(0x0, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0)
5485 | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0)
5486 | P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0)
5487 | P_Fld(0xe, B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0)
5488 | P_Fld(0x10, B0_DQ5_B0_DQ5_RFU));
5489 vIO32WriteFldMulti(DDRPHY_B0_DQ6, P_Fld(0x1, B0_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B0)
5490 | P_Fld(0x0, B0_DQ6_RG_TX_ARDQ_DDR3_SEL_B0)
5491 | P_Fld(0x0, B0_DQ6_RG_RX_ARDQ_DDR3_SEL_B0)
5492 | P_Fld(0x1, B0_DQ6_RG_TX_ARDQ_DDR4_SEL_B0)
5493 | P_Fld(0x1, B0_DQ6_RG_RX_ARDQ_DDR4_SEL_B0)
5494 | P_Fld(0x0, B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0)
5495 | P_Fld(0x1, B0_DQ6_RG_RX_ARDQ_BIAS_EN_B0)
5496 | P_Fld(0x1, B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0));
5497 vIO32WriteFldMulti(DDRPHY_B0_DQ5, P_Fld(0x1, B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0)
5498 | P_Fld(0x0, B0_DQ5_B0_DQ5_RFU));
5499 vIO32WriteFldMulti(DDRPHY_B1_DQ4, P_Fld(0x10, B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1)
5500 | P_Fld(0x10, B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1));
5501 vIO32WriteFldMulti(DDRPHY_B1_DQ5, P_Fld(0x0, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1)
5502 | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1)
5503 | P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1)
5504 | P_Fld(0xe, B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1)
5505 | P_Fld(0x10, B1_DQ5_B1_DQ5_RFU));
5506 vIO32WriteFldMulti(DDRPHY_B1_DQ6, P_Fld(0x1, B1_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B1)
5507 | P_Fld(0x0, B1_DQ6_RG_TX_ARDQ_DDR3_SEL_B1)
5508 | P_Fld(0x0, B1_DQ6_RG_RX_ARDQ_DDR3_SEL_B1)
5509 | P_Fld(0x1, B1_DQ6_RG_TX_ARDQ_DDR4_SEL_B1)
5510 | P_Fld(0x1, B1_DQ6_RG_RX_ARDQ_DDR4_SEL_B1)
5511 | P_Fld(0x0, B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1)
5512 | P_Fld(0x1, B1_DQ6_RG_RX_ARDQ_BIAS_EN_B1)
5513 | P_Fld(0x1, B1_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B1));
5514 vIO32WriteFldMulti(DDRPHY_B1_DQ5, P_Fld(0x1, B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1)
5515 | P_Fld(0x0, B1_DQ5_B1_DQ5_RFU));
5516 vIO32WriteFldMulti(DDRPHY_CA_CMD3, P_Fld(0x1, CA_CMD3_RG_RX_ARCMD_IN_BUFF_EN)
5517 | P_Fld(0x1, CA_CMD3_RG_ARCMD_RESETB)
5518 | P_Fld(0x1, CA_CMD3_RG_TX_ARCMD_EN));
5519 vIO32WriteFldMulti(DDRPHY_CA_CMD6, P_Fld(0x0, CA_CMD6_RG_RX_ARCMD_DDR4_SEL)
5520 | P_Fld(0x0, CA_CMD6_RG_RX_ARCMD_BIAS_VREF_SEL)
5521 | P_Fld(0x0, CA_CMD6_RG_RX_ARCMD_RES_BIAS_EN));
5522 /*
5523 vIO32WriteFldMulti(DDRPHY_SHU_CA_CMD1, P_Fld(0x1, SHU_CA_CMD1_RG_TX_ARCMD_DRVN)
5524 | P_Fld(0x1, SHU_CA_CMD1_RG_TX_ARCMD_DRVP));
5525 vIO32WriteFldMulti(DDRPHY_SHU_CA_CMD2, P_Fld(0x1, SHU_CA_CMD2_RG_TX_ARCLK_DRVN)
5526 | P_Fld(0x1, SHU_CA_CMD2_RG_TX_ARCLK_DRVP));
5527 */
5528 //vIO32WriteFldMulti(DDRPHY_SHU2_CA_CMD1, P_Fld(0x1, SHU2_CA_CMD1_RG_TX_ARCMD_DRVN)
5529 // | P_Fld(0x1, SHU2_CA_CMD1_RG_TX_ARCMD_DRVP));
5530 //vIO32WriteFldMulti(DDRPHY_SHU2_CA_CMD2, P_Fld(0x1, SHU2_CA_CMD2_RG_TX_ARCLK_DRVN)
5531 // | P_Fld(0x1, SHU2_CA_CMD2_RG_TX_ARCLK_DRVP));
5532 vIO32WriteFldMulti(DDRPHY_PLL3, P_Fld(0x0, PLL3_RG_RPHYPLL_TSTOP_EN) | P_Fld(0x0, PLL3_RG_RPHYPLL_TST_EN));
5533 vIO32WriteFldAlign(DDRPHY_MISC_VREF_CTRL, 0x0, MISC_VREF_CTRL_RG_RVREF_VREF_EN);
5534
5535 vIO32WriteFldAlign(DDRPHY_B0_DQ3, 0x1, B0_DQ3_RG_ARDQ_RESETB_B0);
5536 vIO32WriteFldAlign(DDRPHY_B1_DQ3, 0x1, B1_DQ3_RG_ARDQ_RESETB_B1);
5537
5538 mcDELAY_US(1);
5539
5540
5541 vIO32WriteFldMulti(DDRPHY_SHU_PLL8, P_Fld(0x0, SHU_PLL8_RG_RPHYPLL_POSDIV) | P_Fld(0x1, SHU_PLL8_RG_RPHYPLL_PREDIV));
5542 //vIO32WriteFldAlign(DDRPHY_SHU2_PLL8, 0x0, SHU2_PLL8_RG_RPHYPLL_POSDIV);
5543 //vIO32WriteFldAlign(DDRPHY_SHU3_PLL8, 0x0, SHU3_PLL8_RG_RPHYPLL_POSDIV);
5544 //vIO32WriteFldAlign(DDRPHY_SHU4_PLL8, 0x0, SHU4_PLL8_RG_RPHYPLL_POSDIV);
5545
5546 mcDELAY_US(1);
5547
5548 vIO32WriteFldMulti(DDRPHY_SHU_PLL9, P_Fld(0x0, SHU_PLL9_RG_RPHYPLL_MONCK_EN)
5549 | P_Fld(0x0, SHU_PLL9_RG_RPHYPLL_MONVC_EN)
5550 | P_Fld(0x0, SHU_PLL9_RG_RPHYPLL_LVROD_EN)
5551 | P_Fld(0x1, SHU_PLL9_RG_RPHYPLL_RST_DLY));
5552 vIO32WriteFldMulti(DDRPHY_SHU_PLL11, P_Fld(0x0, SHU_PLL11_RG_RCLRPLL_MONCK_EN)
5553 | P_Fld(0x0, SHU_PLL11_RG_RCLRPLL_MONVC_EN)
5554 | P_Fld(0x0, SHU_PLL11_RG_RCLRPLL_LVROD_EN)
5555 | P_Fld(0x1, SHU_PLL11_RG_RCLRPLL_RST_DLY));
5556
5557 mcDELAY_US(1);
5558
5559
5560 vIO32WriteFldMulti(DDRPHY_SHU_PLL10, P_Fld(0x0, SHU_PLL10_RG_RCLRPLL_POSDIV) | P_Fld(0x1, SHU_PLL10_RG_RCLRPLL_PREDIV));
5561 //vIO32WriteFldAlign(DDRPHY_SHU2_PLL10, 0x0, SHU2_PLL10_RG_RCLRPLL_POSDIV);
5562 //vIO32WriteFldAlign(DDRPHY_SHU3_PLL10, 0x0, SHU3_PLL10_RG_RCLRPLL_POSDIV);
5563 //vIO32WriteFldAlign(DDRPHY_SHU4_PLL10, 0x0, SHU4_PLL10_RG_RCLRPLL_POSDIV);
5564
5565 mcDELAY_US(1);
5566
5567
5568
5569 vIO32WriteFldMulti(DDRPHY_PLL4, P_Fld(0x0, PLL4_RG_RPHYPLL_AD_MCK8X_EN)
5570 | P_Fld(0x1, PLL4_PLL4_RFU)
5571 | P_Fld(0x1, PLL4_RG_RPHYPLL_MCK8X_SEL));
5572
5573
5574 mcDELAY_US(1);
5575
5576
5577 vIO32WriteFldMulti(DDRPHY_SHU_PLL0, P_Fld(0x1, SHU_PLL0_ADA_MCK8X_CHB_EN)
5578 | P_Fld(0x1, SHU_PLL0_ADA_MCK8X_CHA_EN)); //@Darren+
5579 //vIO32WriteFldAlign(DDRPHY_SHU2_PLL0, 0x3, SHU2_PLL0_RG_RPHYPLL_TOP_REV);
5580 //vIO32WriteFldAlign(DDRPHY_SHU3_PLL0, 0x3, SHU3_PLL0_RG_RPHYPLL_TOP_REV);
5581 //vIO32WriteFldAlign(DDRPHY_SHU4_PLL0, 0x3, SHU4_PLL0_RG_RPHYPLL_TOP_REV);
5582
5583 mcDELAY_US(1);
5584
5585
5586 vIO32WriteFldAlign(DDRPHY_CA_DLL_ARPI1, 0x1, CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA);
5587 vIO32WriteFldMulti(DDRPHY_B0_DQ3, P_Fld(0x1, B0_DQ3_RG_RX_ARDQ_STBENCMP_EN_B0)
5588 | P_Fld(0x1, B0_DQ3_RG_TX_ARDQ_EN_B0)
5589 | P_Fld(0x1, B0_DQ3_RG_RX_ARDQ_SMT_EN_B0));
5590 vIO32WriteFldMulti(DDRPHY_B1_DQ3, P_Fld(0x1, B1_DQ3_RG_RX_ARDQ_STBENCMP_EN_B1)
5591 | P_Fld(0x1, B1_DQ3_RG_TX_ARDQ_EN_B1)
5592 | P_Fld(0x1, B1_DQ3_RG_RX_ARDQ_SMT_EN_B1));
5593
5594
5595
5596 #if (fcFOR_CHIP_ID == fcLafite)
5597 DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
5598 vIO32WriteFldAlign(DDRPHY_SHU_CA_DLL0, 0x1, SHU_CA_DLL0_RG_ARPISM_MCK_SEL_CA_SHU);
5599 vIO32WriteFldAlign(DDRPHY_SHU_CA_DLL0 + SHIFT_TO_CHB_ADDR, 0x1, SHU_CA_DLL0_RG_ARPISM_MCK_SEL_CA_SHU);
5600 DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
5601 #endif
5602
5603 vIO32WriteFldMulti(DDRPHY_SHU_B0_DLL0, P_Fld(0x1, SHU_B0_DLL0_RG_ARDLL_PHDET_IN_SWAP_B0)
5604 | P_Fld(0x7, SHU_B0_DLL0_RG_ARDLL_GAIN_B0)
5605 | P_Fld(0x7, SHU_B0_DLL0_RG_ARDLL_IDLECNT_B0)
5606 | P_Fld(0x8, SHU_B0_DLL0_RG_ARDLL_P_GAIN_B0)
5607 | P_Fld(0x1, SHU_B0_DLL0_RG_ARDLL_PHJUMP_EN_B0)
5608 | P_Fld(0x1, SHU_B0_DLL0_RG_ARDLL_PHDIV_B0)
5609 | P_Fld(0x0, SHU_B0_DLL0_RG_ARDLL_FAST_PSJP_B0));
5610 vIO32WriteFldMulti(DDRPHY_SHU_B1_DLL0, P_Fld(0x1, SHU_B1_DLL0_RG_ARDLL_PHDET_IN_SWAP_B1)
5611 | P_Fld(0x7, SHU_B1_DLL0_RG_ARDLL_GAIN_B1)
5612 | P_Fld(0x7, SHU_B1_DLL0_RG_ARDLL_IDLECNT_B1)
5613 | P_Fld(0x8, SHU_B1_DLL0_RG_ARDLL_P_GAIN_B1)
5614 | P_Fld(0x1, SHU_B1_DLL0_RG_ARDLL_PHJUMP_EN_B1)
5615 | P_Fld(0x1, SHU_B1_DLL0_RG_ARDLL_PHDIV_B1)
5616 | P_Fld(0x0, SHU_B1_DLL0_RG_ARDLL_FAST_PSJP_B1));
5617
5618 vIO32WriteFldAlign(DDRPHY_SHU_CA_CMD5, 0x29, SHU_CA_CMD5_RG_RX_ARCMD_VREF_SEL);
5619 //vIO32WriteFldAlign(DDRPHY_SHU2_CA_CMD5, 0x0, SHU2_CA_CMD5_RG_RX_ARCMD_VREF_SEL);
5620 //vIO32WriteFldAlign(DDRPHY_SHU3_CA_CMD5, 0x0, SHU3_CA_CMD5_RG_RX_ARCMD_VREF_SEL);
5621 //vIO32WriteFldAlign(DDRPHY_SHU4_CA_CMD5, 0x0, SHU4_CA_CMD5_RG_RX_ARCMD_VREF_SEL);
5622 vIO32WriteFldMulti(DDRPHY_SHU_CA_CMD0, P_Fld(0x1, SHU_CA_CMD0_RG_TX_ARCMD_PRE_EN)
5623 | P_Fld(0x4, SHU_CA_CMD0_RG_TX_ARCLK_DRVN_PRE)
5624 | P_Fld(0x1, SHU_CA_CMD0_RG_TX_ARCLK_PRE_EN));
5625 //vIO32WriteFldMulti(DDRPHY_SHU2_CA_CMD0, P_Fld(0x1, SHU2_CA_CMD0_RG_TX_ARCMD_PRE_EN)
5626 // | P_Fld(0x4, SHU2_CA_CMD0_RG_TX_ARCLK_DRVN_PRE)
5627 // | P_Fld(0x1, SHU2_CA_CMD0_RG_TX_ARCLK_PRE_EN));
5628 //vIO32WriteFldMulti(DDRPHY_SHU3_CA_CMD0, P_Fld(0x1, SHU3_CA_CMD0_RG_TX_ARCMD_PRE_EN)
5629 // | P_Fld(0x4, SHU3_CA_CMD0_RG_TX_ARCLK_DRVN_PRE)
5630 // | P_Fld(0x1, SHU3_CA_CMD0_RG_TX_ARCLK_PRE_EN));
5631 //vIO32WriteFldMulti(DDRPHY_SHU4_CA_CMD0, P_Fld(0x1, SHU4_CA_CMD0_RG_TX_ARCMD_PRE_EN)
5632 // | P_Fld(0x4, SHU4_CA_CMD0_RG_TX_ARCLK_DRVN_PRE)
5633 // | P_Fld(0x1, SHU4_CA_CMD0_RG_TX_ARCLK_PRE_EN));
5634 #if (fcFOR_CHIP_ID == fcLafite)
5635 DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
5636 vIO32WriteFldAlign_All(DDRPHY_SHU_CA_CMD6, 0x0, SHU_CA_CMD6_RG_TX_ARCMD_SER_MODE);
5637 DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
5638 #endif
5639 //vIO32WriteFldAlign(DDRPHY_SHU2_CA_CMD6, 0x3, SHU2_CA_CMD6_RG_ARPI_RESERVE_CA);
5640 //vIO32WriteFldAlign(DDRPHY_SHU3_CA_CMD6, 0x3, SHU3_CA_CMD6_RG_ARPI_RESERVE_CA);
5641 //vIO32WriteFldAlign(DDRPHY_SHU4_CA_CMD6, 0x3, SHU4_CA_CMD6_RG_ARPI_RESERVE_CA);
5642 //vIO32WriteFldAlign(DDRPHY_SHU_CA_CMD3, 0x4e1, SHU_CA_CMD3_RG_ARCMD_REV);
5643 //vIO32WriteFldAlign(DDRPHY_SHU2_CA_CMD7, 0x4e1, SHU2_CA_CMD7_RG_ARCMD_REV);
5644 //vIO32WriteFldAlign(DDRPHY_SHU3_CA_CMD7, 0x4e1, SHU3_CA_CMD7_RG_ARCMD_REV);
5645 //vIO32WriteFldAlign(DDRPHY_SHU4_CA_CMD7, 0x4e1, SHU4_CA_CMD7_RG_ARCMD_REV);
5646 //vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ7, P_Fld(0x00, SHU_B0_DQ7_RG_ARDQ_REV_B0)
5647 // | P_Fld(0x0, SHU_B0_DQ7_DQ_REV_B0_BIT_05));
5648 //vIO32WriteFldAlign(DDRPHY_SHU2_B0_DQ7, 0x20, SHU2_B0_DQ7_RG_ARDQ_REV_B0);
5649 //vIO32WriteFldAlign(DDRPHY_SHU3_B0_DQ7, 0x20, SHU3_B0_DQ7_RG_ARDQ_REV_B0);
5650 //vIO32WriteFldAlign(DDRPHY_SHU4_B0_DQ7, 0x20, SHU4_B0_DQ7_RG_ARDQ_REV_B0);
5651 //vIO32WriteFldMulti(DDRPHY_SHU_B1_DQ7, P_Fld(0x00, SHU_B1_DQ7_RG_ARDQ_REV_B1)
5652 // | P_Fld(0x0, SHU_B1_DQ7_DQ_REV_B1_BIT_05));
5653
5654
5655 //vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ7, 0x0, SHU_B0_DQ7_RG_ARDQ_REV_B0);
5656 //vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ7, 0x0, SHU_B1_DQ7_RG_ARDQ_REV_B1);
5657 //
5658 //vIO32WriteFldAlign(DDRPHY_SHU2_B1_DQ7, 0x20, SHU2_B1_DQ7_RG_ARDQ_REV_B1);
5659 //vIO32WriteFldAlign(DDRPHY_SHU3_B1_DQ7, 0x20, SHU3_B1_DQ7_RG_ARDQ_REV_B1);
5660 //vIO32WriteFldAlign(DDRPHY_SHU4_B1_DQ7, 0x20, SHU4_B1_DQ7_RG_ARDQ_REV_B1);
5661 vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ6, 0x0, SHU_B0_DQ6_RG_TX_ARDQ_SER_MODE_B0);
5662 //vIO32WriteFldAlign(DDRPHY_SHU2_B0_DQ6, 0x1, SHU2_B0_DQ6_RG_ARPI_RESERVE_B0);
5663 //vIO32WriteFldAlign(DDRPHY_SHU3_B0_DQ6, 0x1, SHU3_B0_DQ6_RG_ARPI_RESERVE_B0);
5664 //vIO32WriteFldAlign(DDRPHY_SHU4_B0_DQ6, 0x1, SHU4_B0_DQ6_RG_ARPI_RESERVE_B0);
5665 vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ6, 0x0, SHU_B1_DQ6_RG_TX_ARDQ_SER_MODE_B1);
5666 //vIO32WriteFldAlign(DDRPHY_SHU2_B1_DQ6, 0x1, SHU2_B1_DQ6_RG_ARPI_RESERVE_B1);
5667 //vIO32WriteFldAlign(DDRPHY_SHU3_B1_DQ6, 0x1, SHU3_B1_DQ6_RG_ARPI_RESERVE_B1);
5668 //vIO32WriteFldAlign(DDRPHY_SHU4_B1_DQ6, 0x1, SHU4_B1_DQ6_RG_ARPI_RESERVE_B1);
5669 DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
5670 vIO32WriteFldMulti(DDRPHY_MISC_SHU_OPT, P_Fld(0x1, MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN)
5671 | P_Fld(0x1, MISC_SHU_OPT_R_CA_SHU_PHY_GATING_RESETB_SPM_EN)
5672 | P_Fld(0x2, MISC_SHU_OPT_R_DQB1_SHU_PHDET_SPM_EN)
5673 | P_Fld(0x1, MISC_SHU_OPT_R_DQB1_SHU_PHY_GATING_RESETB_SPM_EN)
5674 | P_Fld(0x2, MISC_SHU_OPT_R_DQB0_SHU_PHDET_SPM_EN)
5675 | P_Fld(0x1, MISC_SHU_OPT_R_DQB0_SHU_PHY_GATING_RESETB_SPM_EN));
5676 vIO32WriteFldMulti(DDRPHY_MISC_SHU_OPT + SHIFT_TO_CHB_ADDR, P_Fld(0x2, MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN)
5677 | P_Fld(0x1, MISC_SHU_OPT_R_CA_SHU_PHY_GATING_RESETB_SPM_EN)
5678 | P_Fld(0x2, MISC_SHU_OPT_R_DQB1_SHU_PHDET_SPM_EN)
5679 | P_Fld(0x1, MISC_SHU_OPT_R_DQB1_SHU_PHY_GATING_RESETB_SPM_EN)
5680 | P_Fld(0x2, MISC_SHU_OPT_R_DQB0_SHU_PHDET_SPM_EN)
5681 | P_Fld(0x1, MISC_SHU_OPT_R_DQB0_SHU_PHY_GATING_RESETB_SPM_EN));
5682 DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
5683
5684 mcDELAY_US(9);
5685
5686 #if (fcFOR_CHIP_ID == fcLafite)
5687 DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
5688 vIO32WriteFldMulti(DDRPHY_SHU_CA_DLL1, P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA) | P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_FASTPJ_CK_SEL_CA));
5689 vIO32WriteFldMulti(DDRPHY_SHU_CA_DLL1 + SHIFT_TO_CHB_ADDR, P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA)
5690 | P_Fld(0x1, SHU_CA_DLL1_RG_ARDLL_FASTPJ_CK_SEL_CA));
5691 DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
5692 #endif
5693 vIO32WriteFldMulti(DDRPHY_SHU_B0_DLL1, P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0) | P_Fld(0x1, SHU_B0_DLL1_RG_ARDLL_FASTPJ_CK_SEL_B0));
5694 vIO32WriteFldMulti(DDRPHY_SHU_B1_DLL1, P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1) | P_Fld(0x1, SHU_B1_DLL1_RG_ARDLL_FASTPJ_CK_SEL_B1));
5695
5696 mcDELAY_US(1);
5697
5698 vIO32WriteFldAlign(DDRPHY_PLL2, 0x0, PLL2_RG_RCLRPLL_EN);
5699 //vIO32WriteFldAlign(DDRPHY_SHU_PLL4, 0xff, SHU_PLL4_RG_RPHYPLL_RESERVED);
5700 //vIO32WriteFldAlign(DDRPHY_SHU_PLL6, 0xff, SHU_PLL6_RG_RCLRPLL_RESERVED);
5701 vIO32WriteFldAlign(DDRPHY_MISC_CG_CTRL0, 0xf, MISC_CG_CTRL0_CLK_MEM_DFS_CFG);
5702
5703 mcDELAY_US(1);
5704
5705 DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
5706 DDRPhyPLLSetting(p);
5707 DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
5708
5709
5710 #if ENABLE_TMRRI_NEW_MODE
5711
5712 vIO32WriteFldAlign(DRAMC_REG_RKCFG, 0, RKCFG_TXRANK);
5713 vIO32WriteFldAlign(DRAMC_REG_RKCFG, 1, RKCFG_TXRANKFIX);
5714 vIO32WriteFldAlign(DRAMC_REG_DRSCTRL, 0x0, DRSCTRL_RK_SCINPUT_OPT);
5715 vIO32WriteFldMulti(DRAMC_REG_DRAMCTRL, P_Fld(0x0, DRAMCTRL_MRRIOPT) | P_Fld(0x0, DRAMCTRL_TMRRIBYRK_DIS) | P_Fld(0x1, DRAMCTRL_TMRRICHKDIS));
5716 vIO32WriteFldAlign(DRAMC_REG_SPCMDCTRL, 0x1, SPCMDCTRL_SC_PG_UPD_OPT);
5717 vIO32WriteFldMulti(DRAMC_REG_SPCMDCTRL, P_Fld(0x0, SPCMDCTRL_SC_PG_MPRW_DIS) | P_Fld(0x0, SPCMDCTRL_SC_PG_STCMD_AREF_DIS)
5718 | P_Fld(0x0, SPCMDCTRL_SC_PG_OPT2_DIS) | P_Fld(0x0, SPCMDCTRL_SC_PG_MAN_DIS));
5719 vIO32WriteFldMulti(DRAMC_REG_MPC_OPTION, P_Fld(0x1, MPC_OPTION_ZQ_BLOCKALE_OPT) | P_Fld(0x1, MPC_OPTION_MPC_BLOCKALE_OPT2) |
5720 P_Fld(0x1, MPC_OPTION_MPC_BLOCKALE_OPT1) | P_Fld(0x1, MPC_OPTION_MPC_BLOCKALE_OPT));
5721
5722 vIO32WriteFldAlign(DRAMC_REG_RKCFG, 0, RKCFG_TXRANK);
5723 vIO32WriteFldAlign(DRAMC_REG_RKCFG, 0, RKCFG_TXRANKFIX);
5724 #else
5725 vIO32WriteFldAlign(DRAMC_REG_DRSCTRL, 0x1, DRSCTRL_RK_SCINPUT_OPT);
5726 vIO32WriteFldMulti(DRAMC_REG_DRAMCTRL, P_Fld(0x1, DRAMCTRL_MRRIOPT) | P_Fld(0x1, DRAMCTRL_TMRRIBYRK_DIS) | P_Fld(0x0, DRAMCTRL_TMRRICHKDIS));
5727 vIO32WriteFldAlign(DRAMC_REG_SPCMDCTRL, 0x0, SPCMDCTRL_SC_PG_UPD_OPT);
5728 vIO32WriteFldMulti(DRAMC_REG_SPCMDCTRL, P_Fld(0x1, SPCMDCTRL_SC_PG_MPRW_DIS) | P_Fld(0x1, SPCMDCTRL_SC_PG_STCMD_AREF_DIS)
5729 | P_Fld(0x1, SPCMDCTRL_SC_PG_OPT2_DIS) | P_Fld(0x1, SPCMDCTRL_SC_PG_MAN_DIS));
5730 #endif
5731 vIO32WriteFldAlign(DRAMC_REG_CKECTRL, 0x1, CKECTRL_RUNTIMEMRRCKEFIX);
5732 vIO32WriteFldAlign(DRAMC_REG_CKECTRL, 0x0, CKECTRL_RUNTIMEMRRMIODIS);
5733
5734 vIO32WriteFldAlign(DDRPHY_B0_DQ9, 0x1, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0);
5735 vIO32WriteFldAlign(DDRPHY_B1_DQ9, 0x1, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1);
5736 vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQSIEN, P_Fld(0xf, SHURK1_DQSIEN_R1DQS3IEN)
5737 | P_Fld(0xf, SHURK1_DQSIEN_R1DQS2IEN)
5738 | P_Fld(0xf, SHURK1_DQSIEN_R1DQS1IEN)
5739 | P_Fld(0xf, SHURK1_DQSIEN_R1DQS0IEN));
5740 vIO32WriteFldMulti(DRAMC_REG_STBCAL1, P_Fld(0x0, STBCAL1_DLLFRZ_MON_PBREF_OPT)
5741 | P_Fld(0x1, STBCAL1_STB_FLAGCLR)
5742 | P_Fld(0x1, STBCAL1_STBCNT_SHU_RST_EN)
5743 | P_Fld(0x1, STBCAL1_STBCNT_MODESEL));
5744 /*
5745 vIO32WriteFldMulti(DRAMC_REG_SHU_DQSG_RETRY, P_Fld(0x1, SHU_DQSG_RETRY_R_RETRY_USE_BURST_MDOE)
5746 | P_Fld(0x1, SHU_DQSG_RETRY_R_RDY_SEL_DLE)
5747 | P_Fld(0x6, SHU_DQSG_RETRY_R_DQSIENLAT)
5748 | P_Fld(0x1, SHU_DQSG_RETRY_R_RETRY_ONCE));
5749 */
5750 vIO32WriteFldMulti(DRAMC_REG_SHU_DRVING1, P_Fld(0xa, SHU_DRVING1_DQSDRVP2) | P_Fld(0xa, SHU_DRVING1_DQSDRVN2)
5751 | P_Fld(0xa, SHU_DRVING1_DQSDRVP1) | P_Fld(0xa, SHU_DRVING1_DQSDRVN1)
5752 | P_Fld(0xa, SHU_DRVING1_DQDRVP2) | P_Fld(0xa, SHU_DRVING1_DQDRVN2));
5753 vIO32WriteFldMulti(DRAMC_REG_SHU_DRVING2, P_Fld(0xa, SHU_DRVING2_DQDRVP1) | P_Fld(0xa, SHU_DRVING2_DQDRVN1)
5754 | P_Fld(0xa, SHU_DRVING2_CMDDRVP2) | P_Fld(0xa, SHU_DRVING2_CMDDRVN2)
5755 | P_Fld(0xa, SHU_DRVING2_CMDDRVP1) | P_Fld(0xa, SHU_DRVING2_CMDDRVN1));
5756 vIO32WriteFldMulti(DRAMC_REG_SHU_DRVING3, P_Fld(0xa, SHU_DRVING3_DQSODTP2) | P_Fld(0xa, SHU_DRVING3_DQSODTN2)
5757 | P_Fld(0xa, SHU_DRVING3_DQSODTP) | P_Fld(0xa, SHU_DRVING3_DQSODTN)
5758 | P_Fld(0xa, SHU_DRVING3_DQODTP2) | P_Fld(0xa, SHU_DRVING3_DQODTN2));
5759 vIO32WriteFldMulti(DRAMC_REG_SHU_DRVING4, P_Fld(0xa, SHU_DRVING4_DQODTP1) | P_Fld(0xa, SHU_DRVING4_DQODTN1)
5760 | P_Fld(0xa, SHU_DRVING4_CMDODTP2) | P_Fld(0xa, SHU_DRVING4_CMDODTN2)
5761 | P_Fld(0xa, SHU_DRVING4_CMDODTP1) | P_Fld(0xa, SHU_DRVING4_CMDODTN1));
5762 /*
5763 vIO32WriteFldMulti(DRAMC_REG_SHU2_DRVING1, P_Fld(0x14a, SHU2_DRVING1_DQSDRV2)
5764 | P_Fld(0x14a, SHU2_DRVING1_DQSDRV1)
5765 | P_Fld(0x14a, SHU2_DRVING1_DQDRV2));
5766 vIO32WriteFldMulti(DRAMC_REG_SHU2_DRVING2, P_Fld(0x14a, SHU2_DRVING2_DQDRV1)
5767 | P_Fld(0x14a, SHU2_DRVING2_CMDDRV2)
5768 | P_Fld(0x14a, SHU2_DRVING2_CMDDRV1));
5769 vIO32WriteFldMulti(DRAMC_REG_SHU2_DRVING3, P_Fld(0x14a, SHU2_DRVING3_DQSODT2)
5770 | P_Fld(0x14a, SHU2_DRVING3_DQSODT1)
5771 | P_Fld(0x14a, SHU2_DRVING3_DQODT2));
5772 vIO32WriteFldMulti(DRAMC_REG_SHU2_DRVING4, P_Fld(0x14a, SHU2_DRVING4_DQODT1)
5773 | P_Fld(0x14a, SHU2_DRVING4_CMDODT2)
5774 | P_Fld(0x14a, SHU2_DRVING4_CMDODT1));
5775 vIO32WriteFldMulti(DRAMC_REG_SHU3_DRVING1, P_Fld(0x14a, SHU3_DRVING1_DQSDRV2)
5776 | P_Fld(0x14a, SHU3_DRVING1_DQSDRV1)
5777 | P_Fld(0x14a, SHU3_DRVING1_DQDRV2));
5778 vIO32WriteFldMulti(DRAMC_REG_SHU3_DRVING2, P_Fld(0x14a, SHU3_DRVING2_DQDRV1)
5779 | P_Fld(0x14a, SHU3_DRVING2_CMDDRV2)
5780 | P_Fld(0x14a, SHU3_DRVING2_CMDDRV1));
5781 vIO32WriteFldMulti(DRAMC_REG_SHU3_DRVING3, P_Fld(0x14a, SHU3_DRVING3_DQSODT2)
5782 | P_Fld(0x14a, SHU3_DRVING3_DQSODT1)
5783 | P_Fld(0x14a, SHU3_DRVING3_DQODT2));
5784 vIO32WriteFldMulti(DRAMC_REG_SHU3_DRVING4, P_Fld(0x14a, SHU3_DRVING4_DQODT1)
5785 | P_Fld(0x14a, SHU3_DRVING4_CMDODT2)
5786 | P_Fld(0x14a, SHU3_DRVING4_CMDODT1));
5787 vIO32WriteFldMulti(DRAMC_REG_SHU4_DRVING1, P_Fld(0x14a, SHU4_DRVING1_DQSDRV2)
5788 | P_Fld(0x14a, SHU4_DRVING1_DQSDRV1)
5789 | P_Fld(0x14a, SHU4_DRVING1_DQDRV2));
5790 vIO32WriteFldMulti(DRAMC_REG_SHU4_DRVING2, P_Fld(0x14a, SHU4_DRVING2_DQDRV1)
5791 | P_Fld(0x14a, SHU4_DRVING2_CMDDRV2)
5792 | P_Fld(0x14a, SHU4_DRVING2_CMDDRV1));
5793 */
5794 // *((UINT32P)(DRAMC1_AO_BASE + 0x08a8)) = 0x14a5294a;
5795 // *((UINT32P)(DRAMC1_AO_BASE + 0x08ac)) = 0x14a5294a;
5796 // *((UINT32P)(DRAMC1_AO_BASE + 0x08b0)) = 0x14a5294a;
5797 // *((UINT32P)(DRAMC1_AO_BASE + 0x08b4)) = 0x14a5294a;
5798 // *((UINT32P)(DRAMC1_AO_BASE + 0x0ea8)) = 0x14a5294a;
5799 // *((UINT32P)(DRAMC1_AO_BASE + 0x0eac)) = 0x14a5294a;
5800 // *((UINT32P)(DRAMC1_AO_BASE + 0x0eb0)) = 0x14a5294a;
5801 // *((UINT32P)(DRAMC1_AO_BASE + 0x0eb4)) = 0x14a5294a;
5802 // *((UINT32P)(DRAMC1_AO_BASE + 0x14a8)) = 0x14a5294a;
5803 // *((UINT32P)(DRAMC1_AO_BASE + 0x14ac)) = 0x14a5294a;
5804 // *((UINT32P)(DRAMC1_AO_BASE + 0x14b0)) = 0x14a5294a;
5805 // *((UINT32P)(DRAMC1_AO_BASE + 0x14b4)) = 0x14a5294a;
5806 // *((UINT32P)(DRAMC1_AO_BASE + 0x1aa8)) = 0x14a5294a;
5807 // *((UINT32P)(DRAMC1_AO_BASE + 0x1aac)) = 0x14a5294a;
5808 vIO32WriteFldMulti(DRAMC_REG_SHUCTRL2, P_Fld(0x0, SHUCTRL2_HWSET_WLRL)
5809 | P_Fld(0x1, SHUCTRL2_SHU_PERIOD_GO_ZERO_CNT)
5810 | P_Fld(0x1, SHUCTRL2_R_DVFS_OPTION)
5811 | P_Fld(0x1, SHUCTRL2_R_DVFS_PARK_N)
5812 | P_Fld(0x1, SHUCTRL2_R_DVFS_DLL_CHA)
5813 | P_Fld(0xa, SHUCTRL2_R_DLL_IDLE));
5814 vIO32WriteFldAlign(DRAMC_REG_DVFSDLL, 0x1, DVFSDLL_DLL_LOCK_SHU_EN);
5815 vIO32WriteFldMulti(DRAMC_REG_DDRCONF0, P_Fld(0x1, DDRCONF0_LPDDR4EN)
5816 | P_Fld(0x1, DDRCONF0_BC4OTF)
5817 | P_Fld(0x1, DDRCONF0_BK8EN));
5818 vIO32WriteFldMulti(DRAMC_REG_STBCAL2, P_Fld(0x1, STBCAL2_STB_GERR_B01)
5819 | P_Fld(0x1, STBCAL2_STB_GERRSTOP)
5820 | P_Fld(0x1, EYESCAN_EYESCAN_RD_SEL_OPT));
5821 vIO32WriteFldAlign(DRAMC_REG_STBCAL2, 0x1, STBCAL2_STB_GERR_RST);
5822 vIO32WriteFldAlign(DRAMC_REG_STBCAL2, 0x0, STBCAL2_STB_GERR_RST);
5823 vIO32WriteFldAlign(DRAMC_REG_CLKAR, 0x1, CLKAR_PSELAR);
5824 vIO32WriteFldAlign(DDRPHY_B0_DQ9, 0x1, B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0);
5825 vIO32WriteFldAlign(DDRPHY_B1_DQ9, 0x1, B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1);
5826 vIO32WriteFldAlign(DDRPHY_CA_CMD10, 0x0, CA_CMD10_R_DMDQSIEN_RDSEL_LAT_CA);
5827 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
5828 {
5829 vIO32WriteFldMulti(DDRPHY_MISC_CTRL0, P_Fld(0x1, MISC_CTRL0_R_STBENCMP_DIV4CK_EN)
5830 | P_Fld(0x1, MISC_CTRL0_R_DMDQSIEN_FIFO_EN)
5831 | P_Fld(0x1, MISC_CTRL0_R_DMSTBEN_OUTSEL)
5832 | P_Fld(0xf, MISC_CTRL0_R_DMDQSIEN_SYNCOPT));
5833 }
5834 else
5835 {
5836 vIO32WriteFldMulti(DDRPHY_MISC_CTRL0, P_Fld(0x1, MISC_CTRL0_R_STBENCMP_DIV4CK_EN)
5837 | P_Fld(0x1, MISC_CTRL0_R_DMDQSIEN_FIFO_EN)
5838 | P_Fld(0x1, MISC_CTRL0_R_DMSTBEN_OUTSEL)
5839 | P_Fld(0xf, MISC_CTRL0_R_DMDQSIEN_SYNCOPT));
5840 }
5841 //vIO32WriteFldMulti(DDRPHY_MISC_CTRL1, P_Fld(0x1, MISC_CTRL1_R_DMDA_RRESETB_E)
5842 vIO32WriteFldMulti(DDRPHY_MISC_CTRL1, P_Fld(0x1, MISC_CTRL1_R_DMDQSIENCG_EN)
5843 | P_Fld(0x1, MISC_CTRL1_R_DM_TX_ARCMD_OE)
5844 #if ENABLE_PINMUX_FOR_RANK_SWAP
5845 | P_Fld(0x1, MISC_CTRL1_R_RK_PINMUXSWAP_EN)
5846 #endif
5847 | P_Fld(0x1, MISC_CTRL1_R_DM_TX_ARCLK_OE));
5848 vIO32WriteFldAlign(DDRPHY_B0_RXDVS0, 1, B0_RXDVS0_R_HWSAVE_MODE_ENA_B0);
5849 vIO32WriteFldAlign(DDRPHY_B1_RXDVS0, 1, B1_RXDVS0_R_HWSAVE_MODE_ENA_B1);
5850 vIO32WriteFldAlign(DDRPHY_CA_RXDVS0, 0, CA_RXDVS0_R_HWSAVE_MODE_ENA_CA);
5851
5852 vIO32WriteFldAlign(DDRPHY_CA_CMD7, 0x0, CA_CMD7_RG_TX_ARCMD_PULL_DN);
5853 vIO32WriteFldAlign(DDRPHY_CA_CMD7, 0x0, CA_CMD7_RG_TX_ARCS_PULL_DN);
5854 vIO32WriteFldAlign(DDRPHY_B0_DQ7, 0x0, B0_DQ7_RG_TX_ARDQ_PULL_DN_B0);
5855 vIO32WriteFldAlign(DDRPHY_B1_DQ7, 0x0, B1_DQ7_RG_TX_ARDQ_PULL_DN_B1);
5856 //vIO32WriteFldAlign(DDRPHY_CA_CMD8, 0x0, CA_CMD8_RG_TX_RRESETB_PULL_DN);
5857
5858
5859 vIO32WriteFldMulti(DRAMC_REG_SHU_CONF0, P_Fld(0x1, SHU_CONF0_DM64BITEN)
5860 | P_Fld(0x0, SHU_CONF0_FDIV2)
5861 | P_Fld(0x1, SHU_CONF0_FREQDIV4)
5862 | P_Fld(0x1, SHU_CONF0_DUALSCHEN)
5863 | P_Fld(0x0, SHU_CONF0_WDATRGO)
5864 | P_Fld(u1MaType, SHU_CONF0_MATYPE)
5865 | P_Fld(0x1, SHU_CONF0_BL4)
5866 | P_Fld(0x1, SHU_CONF0_REFTHD)
5867 | P_Fld(0x1, SHU_CONF0_ADVPREEN)
5868 | P_Fld(0x3f, SHU_CONF0_DMPGTIM));
5869
5870 vIO32WriteFldAlign(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, 0x5, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_DYN_GATING_SEL);
5871 vIO32WriteFldAlign(DRAMC_REG_SHU_SELPH_CA1, 0x0, SHU_SELPH_CA1_TXDLY_CKE);
5872 vIO32WriteFldAlign(DRAMC_REG_SHU_SELPH_CA2, 0x0, SHU_SELPH_CA2_TXDLY_CKE1);
5873
5874 #if (fcFOR_CHIP_ID == fcLafite)
5875 if (vGet_Div_Mode(p) == DIV4_MODE)
5876 {
5877 u1TAIL_LAT = 1;
5878 }
5879 else
5880
5881 {
5882 u1TAIL_LAT = 0;
5883 }
5884
5885
5886 vIO32WriteFldMulti(DRAMC_REG_SHU_APHY_TX_PICG_CTRL, P_Fld(0x0, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK0_SEL_P0)
5887 | P_Fld(0x0, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK0_SEL_P1)
5888 | P_Fld(0x0, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT));
5889
5890
5891 vIO32WriteFldMulti(DRAMC_REG_SHU_STBCAL, P_Fld(u1TAIL_LAT, SHU_STBCAL_R1_DQSIEN_PICG_TAIL_EXT_LAT)
5892 | P_Fld(u1TAIL_LAT, SHU_STBCAL_R0_DQSIEN_PICG_TAIL_EXT_LAT)
5893 | P_Fld(u1TAIL_LAT, SHU_STBCAL_DQSIEN_RX_SELPH_OPT));
5894
5895
5896 vIO32WriteFldMulti(DRAMC_REG_SHU_PHY_RX_CTRL, P_Fld(0x0, SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL)
5897 | P_Fld(0x0, SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD));
5898 #endif
5899
5900
5901 vIO32WriteFldMulti(DRAMC_REG_SHU_ODTCTRL, P_Fld(0x1, SHU_ODTCTRL_RODTE)
5902 | P_Fld(0x1, SHU_ODTCTRL_RODTE2)
5903 | P_Fld(0x1, SHU_ODTCTRL_TWODT)
5904 //| P_Fld(0x5, SHU_ODTCTRL_RODT) //Set in UpdateACTimingReg()
5905 | P_Fld(0x1, SHU_ODTCTRL_WOEN)
5906 | P_Fld(0x1, SHU_ODTCTRL_ROEN));
5907 vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ7, 0x1, SHU_B0_DQ7_R_DMRODTEN_B0);
5908 vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ7, 0x1, SHU_B1_DQ7_R_DMRODTEN_B1);
5909 vIO32WriteFldAlign(DRAMC_REG_REFCTRL0, 0x5, REFCTRL0_REF_PREGATE_CNT);
5910 vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA1, P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS1)
5911 | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RAS)
5912 | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CAS)
5913 | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_WE)
5914 | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_RESET)
5915 | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_ODT)
5916 | P_Fld(0x0, SHU_SELPH_CA1_TXDLY_CS));
5917
5918 if (p->frequency < 1333)
5919 u1TXDLY_CMD = 0x7;
5920 else if (p->frequency < 1600)
5921 u1TXDLY_CMD = 0x8;
5922 else if (p->frequency < 1866)
5923 u1TXDLY_CMD = 0x9;
5924 else if (p->frequency < 2133)
5925 u1TXDLY_CMD = 0xA;
5926 else
5927 u1TXDLY_CMD = 0xB;
5928
5929 vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA2, P_Fld(u1TXDLY_CMD, SHU_SELPH_CA2_TXDLY_CMD)
5930 | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA2)
5931 | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA1)
5932 | P_Fld(0x0, SHU_SELPH_CA2_TXDLY_BA0));
5933 vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA3, P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA7)
5934 | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA6)
5935 | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA5)
5936 | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA4)
5937 | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA3)
5938 | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA2)
5939 | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA1)
5940 | P_Fld(0x0, SHU_SELPH_CA3_TXDLY_RA0));
5941 vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_CA4, P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA15)
5942 | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA14)
5943 | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA13)
5944 | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA12)
5945 | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA11)
5946 | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA10)
5947 | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA9)
5948 | P_Fld(0x0, SHU_SELPH_CA4_TXDLY_RA8));
5949 vIO32WriteFldAlign(DRAMC_REG_SHU_SELPH_CA5, 0x0, SHU_SELPH_CA5_DLY_ODT);
5950 vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS0, P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS3)
5951 | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS2)
5952 | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS1)
5953 | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_OEN_DQS0)
5954 | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_DQS3)
5955 | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_DQS2)
5956 | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_DQS1)
5957 | P_Fld(0x3, SHU_SELPH_DQS0_TXDLY_DQS0));
5958 vIO32WriteFldMulti(DRAMC_REG_SHU_SELPH_DQS1, P_Fld(0x2, SHU_SELPH_DQS1_DLY_OEN_DQS3)
5959 | P_Fld(0x2, SHU_SELPH_DQS1_DLY_OEN_DQS2)
5960 | P_Fld(0x2, SHU_SELPH_DQS1_DLY_OEN_DQS1)
5961 | P_Fld(0x2, SHU_SELPH_DQS1_DLY_OEN_DQS0)
5962 | P_Fld(0x5, SHU_SELPH_DQS1_DLY_DQS3)
5963 | P_Fld(0x5, SHU_SELPH_DQS1_DLY_DQS2)
5964 | P_Fld(0x5, SHU_SELPH_DQS1_DLY_DQS1)
5965 | P_Fld(0x5, SHU_SELPH_DQS1_DLY_DQS0));
5966 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ0, P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ3)
5967 | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ2)
5968 | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ1)
5969 | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_OEN_DQ0)
5970 | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_DQ3)
5971 | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_DQ2)
5972 | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_DQ1)
5973 | P_Fld(0x3, SHURK0_SELPH_DQ0_TXDLY_DQ0));
5974 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ1, P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM3)
5975 | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM2)
5976 | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM1)
5977 | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_OEN_DQM0)
5978 | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_DQM3)
5979 | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_DQM2)
5980 | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_DQM1)
5981 | P_Fld(0x3, SHURK0_SELPH_DQ1_TXDLY_DQM0));
5982 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ2, P_Fld(0x2, SHURK0_SELPH_DQ2_DLY_OEN_DQ3)
5983 | P_Fld(0x2, SHURK0_SELPH_DQ2_DLY_OEN_DQ2)
5984 | P_Fld(0x2, SHURK0_SELPH_DQ2_DLY_OEN_DQ1)
5985 | P_Fld(0x2, SHURK0_SELPH_DQ2_DLY_OEN_DQ0)
5986 | P_Fld(0x6, SHURK0_SELPH_DQ2_DLY_DQ3)
5987 | P_Fld(0x6, SHURK0_SELPH_DQ2_DLY_DQ2)
5988 | P_Fld(0x6, SHURK0_SELPH_DQ2_DLY_DQ1)
5989 | P_Fld(0x6, SHURK0_SELPH_DQ2_DLY_DQ0));
5990 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ3, P_Fld(0x2, SHURK0_SELPH_DQ3_DLY_OEN_DQM3)
5991 | P_Fld(0x2, SHURK0_SELPH_DQ3_DLY_OEN_DQM2)
5992 | P_Fld(0x2, SHURK0_SELPH_DQ3_DLY_OEN_DQM1)
5993 | P_Fld(0x2, SHURK0_SELPH_DQ3_DLY_OEN_DQM0)
5994 | P_Fld(0x6, SHURK0_SELPH_DQ3_DLY_DQM3)
5995 | P_Fld(0x6, SHURK0_SELPH_DQ3_DLY_DQM2)
5996 | P_Fld(0x6, SHURK0_SELPH_DQ3_DLY_DQM1)
5997 | P_Fld(0x6, SHURK0_SELPH_DQ3_DLY_DQM0));
5998 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ0, P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ3)
5999 | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ2)
6000 | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ1)
6001 | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ0)
6002 | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1DQ3)
6003 | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1DQ2)
6004 | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1DQ1)
6005 | P_Fld(0x3, SHURK1_SELPH_DQ0_TX_DLY_R1DQ0));
6006 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ1, P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM3)
6007 | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM2)
6008 | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM1)
6009 | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM0)
6010 | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1DQM3)
6011 | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1DQM2)
6012 | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1DQM1)
6013 | P_Fld(0x3, SHURK1_SELPH_DQ1_TX_DLY_R1DQM0));
6014 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ2, P_Fld(0x2, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ3)
6015 | P_Fld(0x2, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ2)
6016 | P_Fld(0x2, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ1)
6017 | P_Fld(0x2, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ0)
6018 | P_Fld(0x6, SHURK1_SELPH_DQ2_DLY_R1DQ3)
6019 | P_Fld(0x6, SHURK1_SELPH_DQ2_DLY_R1DQ2)
6020 | P_Fld(0x6, SHURK1_SELPH_DQ2_DLY_R1DQ1)
6021 | P_Fld(0x6, SHURK1_SELPH_DQ2_DLY_R1DQ0));
6022 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ3, P_Fld(0x2, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM3)
6023 | P_Fld(0x2, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM2)
6024 | P_Fld(0x2, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM1)
6025 | P_Fld(0x2, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM0)
6026 | P_Fld(0x6, SHURK1_SELPH_DQ3_DLY_R1DQM3)
6027 | P_Fld(0x6, SHURK1_SELPH_DQ3_DLY_R1DQM2)
6028 | P_Fld(0x6, SHURK1_SELPH_DQ3_DLY_R1DQM1)
6029 | P_Fld(0x6, SHURK1_SELPH_DQ3_DLY_R1DQM0));
6030 vIO32WriteFldMulti(DDRPHY_SHU_R0_B1_DQ7, P_Fld(0x1a, SHU_R0_B1_DQ7_RK0_ARPI_DQM_B1)
6031 | P_Fld(0x1a, SHU_R0_B1_DQ7_RK0_ARPI_DQ_B1));
6032 vIO32WriteFldMulti(DDRPHY_SHU_R0_B0_DQ7, P_Fld(0x1a, SHU_R0_B0_DQ7_RK0_ARPI_DQM_B0)
6033 | P_Fld(0x1a, SHU_R0_B0_DQ7_RK0_ARPI_DQ_B0));
6034 vIO32WriteFldMulti(DDRPHY_SHU_R1_B1_DQ7, P_Fld(0x14, SHU_R1_B1_DQ7_RK1_ARPI_DQM_B1)
6035 | P_Fld(0x14, SHU_R1_B1_DQ7_RK1_ARPI_DQ_B1));
6036 vIO32WriteFldMulti(DDRPHY_SHU_R1_B0_DQ7, P_Fld(0x14, SHU_R1_B0_DQ7_RK1_ARPI_DQM_B0)
6037 | P_Fld(0x14, SHU_R1_B0_DQ7_RK1_ARPI_DQ_B0));
6038
6039 mcDELAY_US(1);
6040
6041 vIO32WriteFldAlign(DDRPHY_B1_DQ9, 0x1, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1);
6042 vIO32WriteFldAlign(DDRPHY_B0_DQ9, 0x1, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0);
6043 vIO32WriteFldAlign(DDRPHY_B0_DQ6, 0x2, B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0);
6044 vIO32WriteFldAlign(DDRPHY_B1_DQ6, 0x2, B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1);
6045 vIO32WriteFldAlign(DRAMC_REG_STBCAL, 0x1, STBCAL_DQSIENMODE);
6046 vIO32WriteFldMulti(DRAMC_REG_SREFCTRL, P_Fld(0x0, SREFCTRL_SREF_HW_EN)
6047 | P_Fld(0x8, SREFCTRL_SREFDLY));
6048 vIO32WriteFldMulti(DRAMC_REG_SHU_CKECTRL, P_Fld(0x3, SHU_CKECTRL_SREF_CK_DLY)
6049 | P_Fld(0x3, SHU_CKECTRL_TCKESRX));
6050 //| P_Fld(0x3, SHU_CKECTRL_CKEPRD));
6051 vIO32WriteFldMulti(DRAMC_REG_SHU_PIPE, P_Fld(0x1, SHU_PIPE_READ_START_EXTEND1)
6052 | P_Fld(0x1, SHU_PIPE_DLE_LAST_EXTEND1));
6053 vIO32WriteFldMulti(DRAMC_REG_CKECTRL, P_Fld(0x1, CKECTRL_CKEON)
6054 | P_Fld(0x1, CKECTRL_CKETIMER_SEL));
6055 vIO32WriteFldMulti(DRAMC_REG_RKCFG, P_Fld(0x1, RKCFG_CKE2RANK)
6056 | P_Fld(0x1, RKCFG_CKE2RANK_OPT2));
6057 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
6058 {
6059 vIO32WriteFldMulti(DRAMC_REG_SHU_CONF2, P_Fld(0x1, SHU_CONF2_WPRE2T)
6060 | P_Fld(0x7, SHU_CONF2_DCMDLYREF));
6061 //| P_Fld(0x64, SHU_CONF2_FSPCHG_PRDCNT));
6062 vIO32WriteFldAlign(DRAMC_REG_SPCMDCTRL, 0x1, SPCMDCTRL_CLR_EN);
6063 //vIO32WriteFldAlign(DRAMC_REG_SHU_SCINTV, 0xf, SHU_SCINTV_MRW_INTV);
6064 vIO32WriteFldAlign(DRAMC_REG_SHUCTRL1, 0x40, SHUCTRL1_FC_PRDCNT);
6065 }
6066 else
6067 {
6068 vIO32WriteFldMulti(DRAMC_REG_SHU_CONF2, P_Fld(0x1, SHU_CONF2_WPRE2T)
6069 | P_Fld(0x7, SHU_CONF2_DCMDLYREF));
6070 //| P_Fld(0x64, SHU_CONF2_FSPCHG_PRDCNT));
6071 vIO32WriteFldAlign(DRAMC_REG_SPCMDCTRL, 0x1, SPCMDCTRL_CLR_EN);
6072 //vIO32WriteFldAlign(DRAMC_REG_SHU_SCINTV, 0xf, SHU_SCINTV_MRW_INTV);
6073 vIO32WriteFldAlign(DRAMC_REG_SHUCTRL1, 0x40, SHUCTRL1_FC_PRDCNT);
6074 }
6075 vIO32WriteFldAlign(DRAMC_REG_SHUCTRL, 0x1, SHUCTRL_LPSM_BYPASS_B);
6076 vIO32WriteFldMulti(DRAMC_REG_REFCTRL1, P_Fld(0x0, REFCTRL1_SREF_PRD_OPT) | P_Fld(0x0, REFCTRL1_PSEL_OPT1) | P_Fld(0x0, REFCTRL1_PSEL_OPT2) | P_Fld(0x0, REFCTRL1_PSEL_OPT3));
6077 //vIO32WriteFldAlign(DDRPHY_SHU_PLL4, 0xfe, SHU_PLL4_RG_RPHYPLL_RESERVED);
6078 //vIO32WriteFldAlign(DDRPHY_SHU_PLL6, 0xfe, SHU_PLL6_RG_RCLRPLL_RESERVED);
6079 vIO32WriteFldMulti(DRAMC_REG_REFRATRE_FILTER, P_Fld(0x1, REFRATRE_FILTER_PB2AB_OPT) | P_Fld(0x0, REFRATRE_FILTER_PB2AB_OPT1));
6080
6081 #if !APPLY_LP4_POWER_INIT_SEQUENCE
6082 vIO32WriteFldAlign(DDRPHY_MISC_CTRL1, 0x1, MISC_CTRL1_R_DMDA_RRESETB_I);
6083 #endif
6084 vIO32WriteFldAlign(DRAMC_REG_DRAMCTRL, 0x0, DRAMCTRL_CLKWITRFC);
6085 vIO32WriteFldMulti(DRAMC_REG_MISCTL0, P_Fld(0x1, MISCTL0_REFP_ARB_EN2)
6086 | P_Fld(0x1, MISCTL0_PRE_DLE_VLD_OPT)
6087 | P_Fld(0x1, MISCTL0_PBC_ARB_EN)
6088 | P_Fld(0x1, MISCTL0_REFA_ARB_EN2));
6089 vIO32WriteFldMulti(DRAMC_REG_PERFCTL0, P_Fld(0x1, PERFCTL0_MWHPRIEN)
6090 //| P_Fld(0x1, PERFCTL0_RWSPLIT)
6091 | P_Fld(0x1, PERFCTL0_WFLUSHEN)
6092 | P_Fld(0x1, PERFCTL0_EMILLATEN)
6093 | P_Fld(0x1, PERFCTL0_RWAGEEN)
6094 | P_Fld(0x1, PERFCTL0_RWLLATEN)
6095 | P_Fld(0x1, PERFCTL0_RWHPRIEN)
6096 | P_Fld(0x1, PERFCTL0_RWOFOEN)
6097 | P_Fld(0x1, PERFCTL0_DISRDPHASE1));
6098 vIO32WriteFldAlign(DRAMC_REG_ARBCTL, 0x80, ARBCTL_MAXPENDCNT);
6099 vIO32WriteFldMulti(DRAMC_REG_PADCTRL, P_Fld(0x1, PADCTRL_DQIENLATEBEGIN)
6100 | P_Fld(0x1, PADCTRL_DQIENQKEND));
6101 vIO32WriteFldAlign(DRAMC_REG_DRAMC_PD_CTRL, 0x1, DRAMC_PD_CTRL_DCMREF_OPT);
6102 vIO32WriteFldMulti(DRAMC_REG_CLKCTRL, P_Fld(0x1, CLKCTRL_CLK_EN_1)
6103 | P_Fld(0x1, CLKCTRL_CLK_EN_0));
6104 vIO32WriteFldMulti(DRAMC_REG_REFCTRL0, P_Fld(0x4, REFCTRL0_DISBYREFNUM)
6105 | P_Fld(0x1, REFCTRL0_DLLFRZ));
6106 #if 0
6107 vIO32WriteFldMulti(DRAMC_REG_CATRAINING1, P_Fld(0xff, CATRAINING1_CATRAIN_INTV)
6108 | P_Fld(0x0, CATRAINING1_CATRAINLAT));
6109 #endif
6110 #if 0
6111 vIO32WriteFldMulti(DRAMC_REG_SHU_RANKCTL, P_Fld(0x6, SHU_RANKCTL_RANKINCTL_PHY)
6112 | P_Fld(0x4, SHU_RANKCTL_RANKINCTL_ROOT1)
6113 | P_Fld(0x4, SHU_RANKCTL_RANKINCTL));
6114 #endif
6115
6116 //vIO32WriteFldAlign(DRAMC_REG_SHU_STBCAL, 0x1, SHU_STBCAL_DMSTBLAT);
6117 //vIO32WriteFldAlign(DRAMC_REG_SHURK0_DQSCTL, 0x5, SHURK0_DQSCTL_DQSINCTL); //DQSINCTL: set in UpdateACTimingReg()
6118 //vIO32WriteFldAlign(DRAMC_REG_SHURK1_DQSCTL, 0x5, SHURK1_DQSCTL_R1DQSINCTL); //Set in UpdateACTimingReg()
6119
6120 mcDELAY_US(2);
6121 #if LEGACY_GATING_DLY
6122 LegacyGatingDlyLP4_DDR3200(p);
6123 #endif
6124 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
6125 {
6126 }
6127 else
6128 {
6129 vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQSIEN, P_Fld(0x19, SHURK0_DQSIEN_R0DQS1IEN)
6130 | P_Fld(0x19, SHURK0_DQSIEN_R0DQS0IEN));
6131 vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQSIEN, P_Fld(0x0, SHURK1_DQSIEN_R1DQS3IEN)
6132 | P_Fld(0x0, SHURK1_DQSIEN_R1DQS2IEN)
6133 | P_Fld(0x1b, SHURK1_DQSIEN_R1DQS1IEN)
6134 | P_Fld(0x1b, SHURK1_DQSIEN_R1DQS0IEN));
6135 }
6136
6137 vIO32WriteFldAlign(DRAMC_REG_DRAMCTRL, 0x1, DRAMCTRL_PREALL_OPTION);
6138 vIO32WriteFldAlign(DRAMC_REG_ZQCS, 0x56, ZQCS_ZQCSOP);
6139
6140 mcDELAY_US(1);
6141
6142 vIO32WriteFldAlign(DRAMC_REG_SHU_CONF1, 0x1, SHU_CONF1_TREFBWIG);
6143 vIO32WriteFldAlign(DRAMC_REG_SHU_CONF3, 0xff, SHU_CONF3_REFRCNT);
6144 vIO32WriteFldAlign(DRAMC_REG_REFCTRL0, 0x1, REFCTRL0_REFFRERUN);
6145 vIO32WriteFldAlign(DRAMC_REG_SREFCTRL, 0x1, SREFCTRL_SREF_HW_EN);
6146 vIO32WriteFldAlign(DRAMC_REG_MPC_OPTION, 0x1, MPC_OPTION_MPCRKEN);
6147 vIO32WriteFldAlign(DRAMC_REG_DRAMC_PD_CTRL, 0x1, DRAMC_PD_CTRL_PHYCLKDYNGEN);
6148 vIO32WriteFldAlign(DRAMC_REG_DRAMC_PD_CTRL, 0x1, DRAMC_PD_CTRL_DCMEN);
6149 vIO32WriteFldMulti(DRAMC_REG_EYESCAN, P_Fld(0x0, EYESCAN_RX_DQ_EYE_SEL)
6150 | P_Fld(0x0, EYESCAN_RG_RX_EYE_SCAN_EN));
6151 vIO32WriteFldMulti(DRAMC_REG_STBCAL1, P_Fld(0x1, STBCAL1_STBCNT_LATCH_EN)
6152 | P_Fld(0x1, STBCAL1_STBENCMPEN));
6153 vIO32WriteFldAlign(DRAMC_REG_TEST2_1, 0x10000, TEST2_1_TEST2_BASE);
6154 #if (FOR_DV_SIMULATION_USED == 1 || SW_CHANGE_FOR_SIMULATION == 1)
6155
6156 vIO32WriteFldAlign(DRAMC_REG_TEST2_2, 0x20, TEST2_2_TEST2_OFF);
6157 #else
6158 vIO32WriteFldAlign(DRAMC_REG_TEST2_2, 0x400, TEST2_2_TEST2_OFF);
6159 #endif
6160 vIO32WriteFldMulti(DRAMC_REG_TEST2_3, P_Fld(0x1, TEST2_3_TEST2WREN2_HW_EN)
6161 | P_Fld(0x1, TEST2_3_TESTAUDPAT));
6162 vIO32WriteFldAlign(DRAMC_REG_RSTMASK, 0x0, RSTMASK_DAT_SYNC_MASK);
6163 vIO32WriteFldAlign(DRAMC_REG_RSTMASK, 0x0, RSTMASK_PHY_SYNC_MASK);
6164
6165 mcDELAY_US(1);
6166
6167 vIO32WriteFldMulti(DRAMC_REG_HW_MRR_FUN, P_Fld(0x0, HW_MRR_FUN_TRPMRR_EN)
6168 | P_Fld(0x0, HW_MRR_FUN_TRCDMRR_EN) | P_Fld(0x0, HW_MRR_FUN_TMRR_ENA)
6169 | P_Fld(0x0, HW_MRR_FUN_MANTMRR_EN));
6170 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
6171 {
6172 vIO32WriteFldAlign(DRAMC_REG_PERFCTL0, 0x1, PERFCTL0_WRFIO_MODE2);
6173 //| P_Fld(0x0, PERFCTL0_RWSPLIT)); //Set in UpdateInitialSettings_LP4()
6174 vIO32WriteFldMulti(DRAMC_REG_PERFCTL0, P_Fld(0x1, PERFCTL0_REORDEREN)
6175 | P_Fld(0x0, PERFCTL0_REORDER_MODE));
6176 vIO32WriteFldAlign(DRAMC_REG_RSTMASK, 0x0, RSTMASK_GT_SYNC_MASK);
6177 vIO32WriteFldAlign(DRAMC_REG_RKCFG, 0x1, RKCFG_DQSOSC2RK);
6178 vIO32WriteFldAlign(DRAMC_REG_SPCMDCTRL, 0x1, SPCMDCTRL_REFR_BLOCKEN);
6179 vIO32WriteFldAlign(DRAMC_REG_EYESCAN, 0x0, EYESCAN_RG_RX_MIOCK_JIT_EN);
6180 }
6181 else
6182 {
6183 vIO32WriteFldAlign(DRAMC_REG_DRAMCTRL, 0x0, DRAMCTRL_CTOREQ_HPRI_OPT);
6184 vIO32WriteFldMulti(DRAMC_REG_PERFCTL0, P_Fld(0x1, PERFCTL0_REORDEREN)
6185 | P_Fld(0x0, PERFCTL0_REORDER_MODE));
6186 vIO32WriteFldAlign(DRAMC_REG_SPCMDCTRL, 0x1, SPCMDCTRL_REFR_BLOCKEN);
6187 vIO32WriteFldAlign(DRAMC_REG_RSTMASK, 0x0, RSTMASK_GT_SYNC_MASK);
6188 vIO32WriteFldAlign(DRAMC_REG_RKCFG, 0x1, RKCFG_DQSOSC2RK);
6189 vIO32WriteFldAlign(DRAMC_REG_MPC_OPTION, 1, MPC_OPTION_MPCRKEN);
6190 vIO32WriteFldAlign(DRAMC_REG_EYESCAN, 0x0, EYESCAN_RG_RX_MIOCK_JIT_EN);
6191 vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ7, 0x1, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0);
6192 vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ7, 0x1, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1);
6193 vIO32WriteFldAlign(DRAMC_REG_SHU_RANKCTL, 0x4, SHU_RANKCTL_RANKINCTL);
6194 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ0, P_Fld(0x2, SHURK0_SELPH_DQ0_TXDLY_DQ1)
6195 | P_Fld(0x2, SHURK0_SELPH_DQ0_TXDLY_DQ0));
6196 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ1, P_Fld(0x2, SHURK0_SELPH_DQ1_TXDLY_DQM1)
6197 | P_Fld(0x2, SHURK0_SELPH_DQ1_TXDLY_DQM0));
6198 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ0, P_Fld(0x2, SHURK1_SELPH_DQ0_TX_DLY_R1DQ1)
6199 | P_Fld(0x2, SHURK1_SELPH_DQ0_TX_DLY_R1DQ0));
6200 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ1, P_Fld(0x2, SHURK1_SELPH_DQ1_TX_DLY_R1DQM1)
6201 | P_Fld(0x2, SHURK1_SELPH_DQ1_TX_DLY_R1DQM0));
6202 }
6203 #if ENABLE_TMRRI_NEW_MODE
6204 vIO32WriteFldAlign(DRAMC_REG_SPCMDCTRL, 0x0, SPCMDCTRL_REFR_BLOCKEN);
6205 vIO32WriteFldAlign(DRAMC_REG_HW_MRR_FUN, 0x1, HW_MRR_FUN_TMRR_ENA);
6206 #endif
6207 mcDELAY_US(5);
6208
6209 vIO32WriteFldAlign(DRAMC_REG_STBCAL1, 0x3, STBCAL1_STBCAL_FILTER);
6210 vIO32WriteFldAlign(DRAMC_REG_STBCAL1, 0x1, STBCAL1_STBCAL_FILTER);
6211 vIO32WriteFldMulti(DRAMC_REG_STBCAL, P_Fld(0x1, STBCAL_STB_DQIEN_IG)
6212 | P_Fld(0x1, STBCAL_PICHGBLOCK_NORD)
6213 | P_Fld(0x0, STBCAL_STBCALEN)
6214 | P_Fld(0x0, STBCAL_STB_SELPHYCALEN)
6215 | P_Fld(0x1, STBCAL_PIMASK_RKCHG_OPT));
6216 vIO32WriteFldAlign(DRAMC_REG_STBCAL1, 0x1, STBCAL1_STB_SHIFT_DTCOUT_IG);
6217 vIO32WriteFldMulti(DRAMC_REG_SHU_DQSG, P_Fld(0x9, SHU_DQSG_STB_UPDMASKCYC)
6218 | P_Fld(0x1, SHU_DQSG_STB_UPDMASK_EN));
6219 vIO32WriteFldAlign(DDRPHY_MISC_CTRL0, 0x0, MISC_CTRL0_R_DMDQSIEN_SYNCOPT);
6220 vIO32WriteFldAlign(DRAMC_REG_SHU_STBCAL, 0x1, SHU_STBCAL_DQSG_MODE);
6221 vIO32WriteFldAlign(DRAMC_REG_STBCAL, 0x1, STBCAL_SREF_DQSGUPD);
6222
6223 #if ENABLE_RX_TRACKING
6224 vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ7, p->DBI_R_onoff[p->dram_fsp], SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0);
6225 vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ7, p->DBI_R_onoff[p->dram_fsp], SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1);
6226 #else
6227 vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ7, 0, SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0);
6228 vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ7, 0, SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1);
6229 #endif
6230
6231 vIO32WriteFldMulti(DRAMC_REG_SHU_STBCAL, P_Fld(0x1, SHU_STBCAL_PICGLAT)
6232 | P_Fld(0x2, SHU_STBCAL_DMSTBLAT));
6233 vIO32WriteFldMulti(DRAMC_REG_REFCTRL1, P_Fld(0x1, REFCTRL1_REF_QUE_AUTOSAVE_EN)
6234 | P_Fld(0x1, REFCTRL1_SLEFREF_AUTOSAVE_EN));
6235 vIO32WriteFldMulti(DRAMC_REG_DQSOSCR, P_Fld(0x1, DQSOSCR_SREF_TXPI_RELOAD_OPT)
6236 | P_Fld(0x1, DQSOSCR_SREF_TXUI_RELOAD_OPT));
6237 vIO32WriteFldMulti(DRAMC_REG_RSTMASK, P_Fld(0x0, RSTMASK_DVFS_SYNC_MASK)
6238 | P_Fld(0x0, RSTMASK_GT_SYNC_MASK_FOR_PHY)
6239 | P_Fld(0x0, RSTMASK_DVFS_SYNC_MASK_FOR_PHY));
6240 vIO32WriteFldAlign(DRAMC_REG_RKCFG, 0x1, RKCFG_RKMODE);
6241
6242 #if !APPLY_LP4_POWER_INIT_SEQUENCE
6243 vIO32WriteFldMulti(DRAMC_REG_CKECTRL, P_Fld(0x1, CKECTRL_CKEFIXON)
6244 | P_Fld(0x1, CKECTRL_CKE1FIXON));
6245 #endif
6246
6247 mcDELAY_US(12);
6248
6249
6250 //if(p->frequency==1600)
6251 {
6252 #if 0
6253
6254 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
6255 {
6256 vIO32WriteFldMulti(DRAMC_REG_SHU_RANKCTL, P_Fld(0x5, SHU_RANKCTL_RANKINCTL_PHY)
6257 | P_Fld(0x3, SHU_RANKCTL_RANKINCTL_ROOT1)
6258 | P_Fld(0x3, SHU_RANKCTL_RANKINCTL));
6259 }
6260 else
6261 {
6262 vIO32WriteFldMulti(DRAMC_REG_SHU_RANKCTL, P_Fld(0x6, SHU_RANKCTL_RANKINCTL_PHY)
6263 | P_Fld(0x4, SHU_RANKCTL_RANKINCTL_ROOT1));
6264 }
6265 #endif
6266 #if LEGACY_TX_TRACK
6267 LegacyTxTrackLP4_DDR3200(p);
6268 #endif
6269
6270 #if ENABLE_WRITE_POST_AMBLE_1_POINT_5_TCK
6271 vIO32WriteFldAlign(DRAMC_REG_SHU_WODT, p->dram_fsp, SHU_WODT_WPST1P5T);
6272 #else
6273 vIO32WriteFldAlign(DRAMC_REG_SHU_WODT, 0x0, SHU_WODT_WPST1P5T);
6274 #endif
6275
6276 //vIO32WriteFldAlign(DRAMC_REG_SHU_HWSET_MR2, 0x2d, SHU_HWSET_MR2_HWSET_MR2_OP);
6277 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
6278 {
6279 vIO32WriteFldMulti(DRAMC_REG_SHURK0_DQSIEN, P_Fld(0x19, SHURK0_DQSIEN_R0DQS1IEN)
6280 | P_Fld(0x19, SHURK0_DQSIEN_R0DQS0IEN));
6281 }
6282 vIO32WriteFldMulti(DRAMC_REG_SHURK0_PI, P_Fld(0x1a, SHURK0_PI_RK0_ARPI_DQM_B1)
6283 | P_Fld(0x1a, SHURK0_PI_RK0_ARPI_DQM_B0)
6284 | P_Fld(0x1a, SHURK0_PI_RK0_ARPI_DQ_B1)
6285 | P_Fld(0x1a, SHURK0_PI_RK0_ARPI_DQ_B0));
6286 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ2, P_Fld(0x4, SHURK0_SELPH_DQ2_DLY_OEN_DQ3)
6287 | P_Fld(0x4, SHURK0_SELPH_DQ2_DLY_OEN_DQ2)
6288 | P_Fld(0x4, SHURK0_SELPH_DQ2_DLY_OEN_DQ1)
6289 | P_Fld(0x4, SHURK0_SELPH_DQ2_DLY_OEN_DQ0));
6290 vIO32WriteFldMulti(DRAMC_REG_SHURK0_SELPH_DQ3, P_Fld(0x4, SHURK0_SELPH_DQ3_DLY_OEN_DQM3)
6291 | P_Fld(0x4, SHURK0_SELPH_DQ3_DLY_OEN_DQM2)
6292 | P_Fld(0x4, SHURK0_SELPH_DQ3_DLY_OEN_DQM1)
6293 | P_Fld(0x4, SHURK0_SELPH_DQ3_DLY_OEN_DQM0));
6294 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
6295 {
6296 vIO32WriteFldMulti(DRAMC_REG_SHURK1_DQSIEN, P_Fld(0x0, SHURK1_DQSIEN_R1DQS3IEN)
6297 | P_Fld(0x0, SHURK1_DQSIEN_R1DQS2IEN)
6298 | P_Fld(0x1b, SHURK1_DQSIEN_R1DQS1IEN)
6299 | P_Fld(0x1b, SHURK1_DQSIEN_R1DQS0IEN));
6300 }
6301 vIO32WriteFldMulti(DRAMC_REG_SHURK1_PI, P_Fld(0x14, SHURK1_PI_RK1_ARPI_DQM_B1)
6302 | P_Fld(0x14, SHURK1_PI_RK1_ARPI_DQM_B0)
6303 | P_Fld(0x14, SHURK1_PI_RK1_ARPI_DQ_B1)
6304 | P_Fld(0x14, SHURK1_PI_RK1_ARPI_DQ_B0));
6305 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ2, P_Fld(0x4, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ3)
6306 | P_Fld(0x4, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ2)
6307 | P_Fld(0x4, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ1)
6308 | P_Fld(0x4, SHURK1_SELPH_DQ2_DLY_R1OEN_DQ0));
6309 vIO32WriteFldMulti(DRAMC_REG_SHURK1_SELPH_DQ3, P_Fld(0x4, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM3)
6310 | P_Fld(0x4, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM2)
6311 | P_Fld(0x4, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM1)
6312 | P_Fld(0x4, SHURK1_SELPH_DQ3_DLY_R1OEN_DQM0));
6313 vIO32WriteFldMulti(DRAMC_REG_SHU_DQSG_RETRY, P_Fld(0x0, SHU_DQSG_RETRY_R_XSR_RETRY_SPM_MODE)
6314 | P_Fld(0x0, SHU_DQSG_RETRY_R_DDR1866_PLUS));
6315 #if LEGACY_TDQSCK_PRECAL
6316 LegacyPreCalLP4_DDR3200(p);
6317 #endif
6318
6319
6320
6321
6322 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
6323 {
6324 vIO32WriteFldAlign(DDRPHY_SHU_B0_DQ7, 0x1, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0);
6325 vIO32WriteFldAlign(DDRPHY_SHU_B1_DQ7, 0x1, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1);
6326 }
6327 else
6328 {
6329 vIO32WriteFldMulti(DDRPHY_SHU_B0_DQ7, P_Fld(0x1, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0)
6330 | P_Fld(0x1, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0));
6331 vIO32WriteFldMulti(DDRPHY_SHU_B1_DQ7, P_Fld(0x1, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1)
6332 | P_Fld(0x1, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1));
6333
6334 }
6335
6336
6337 vIO32WriteFldAlign(DRAMC_REG_SHU_DQS2DQ_TX, 0x0, SHU_DQS2DQ_TX_OE2DQ_OFFSET);
6338 }
6339
6340 if (p->freqGroup == 2133)
6341 {
6342 DramcSetting_Olympus_LP4_ByteMode_DDR4266(p);
6343 }
6344 else if (p->freqGroup == 1866)
6345 {
6346 DramcSetting_Olympus_LP4_ByteMode_DDR3733(p);
6347 }
6348
6349 else if (p->freqGroup == 1333 || p->freqGroup == 1200)
6350 {
6351 DramcSetting_Olympus_LP4_ByteMode_DDR2667(p);
6352 }
6353 else if ((p->freqGroup == 800) || (p->freqGroup == 600) || (p->freqGroup == 400))
6354 {
6355 DramcSetting_Olympus_LP4_ByteMode_DDR1600(p);
6356 }
6357
6358 UpdateInitialSettings_LP4(p);
6359
6360 #if SIMULATION_SW_IMPED
6361 #if FSP1_CLKCA_TERM
6362 U8 u1CASwImpFreqRegion = (p->dram_fsp == FSP_0)? IMP_LOW_FREQ: IMP_HIGH_FREQ;
6363 #else
6364 U8 u1CASwImpFreqRegion = (p->frequency <= 1866)? IMP_LOW_FREQ: IMP_HIGH_FREQ;
6365 #endif
6366 U8 u1DQSwImpFreqRegion = (p->frequency <= 1866)? IMP_LOW_FREQ: IMP_HIGH_FREQ;
6367
6368 if (p->dram_type == TYPE_LPDDR4X)
6369 DramcSwImpedanceSaveRegister(p, u1CASwImpFreqRegion, u1DQSwImpFreqRegion, DRAM_DFS_REG_SHU0);
6370 #endif
6371
6372 #ifndef LOOPBACK_TEST
6373 DDRPhyFreqMeter(p);
6374 #endif
6375
6376 #if 0
6377 vIO32WriteFldMulti(DRAMC_REG_MRS, P_Fld(0x0, MRS_MRSRK)
6378 | P_Fld(0x4, MRS_MRSMA)
6379 | P_Fld(0x0, MRS_MRSOP));
6380 mcDELAY_US(1);
6381 vIO32WriteFldAlign(DRAMC_REG_SPCMD, 0x1, SPCMD_MRREN);
6382 vIO32WriteFldAlign(DRAMC_REG_SPCMD, 0x0, SPCMD_MRREN);
6383 #endif
6384
6385 vIO32WriteFldAlign(DRAMC_REG_TEST2_4, 0x0, TEST2_4_TEST_REQ_LEN1);
6386
6387 vIO32WriteFldAlign(DRAMC_REG_SHU_CONF3, 0x5, SHU_CONF3_ZQCSCNT);
6388
6389 mcDELAY_US(1);
6390
6391 #if !APPLY_LP4_POWER_INIT_SEQUENCE
6392 vIO32WriteFldMulti(DRAMC_REG_CKECTRL, P_Fld(0x0, CKECTRL_CKEFIXON)
6393 | P_Fld(0x0, CKECTRL_CKE1FIXON));
6394 #endif
6395 vIO32WriteFldMulti(DRAMC_REG_REFCTRL0, P_Fld(0x1, REFCTRL0_PBREFEN)
6396 | P_Fld(0x1, REFCTRL0_PBREF_DISBYRATE));
6397 vIO32WriteFldMulti(DRAMC_REG_SHUCTRL2, P_Fld(0x1, SHUCTRL2_MR13_SHU_EN)
6398 | P_Fld(0x1, SHUCTRL2_HWSET_WLRL));
6399 vIO32WriteFldAlign(DRAMC_REG_REFCTRL0, 0x1, REFCTRL0_REFDIS);
6400 //vIO32WriteFldAlign(DRAMC_REG_SPCMDCTRL, 0x0, SPCMDCTRL_REFRDIS);
6401 vIO32WriteFldAlign(DRAMC_REG_DRAMCTRL, 0x1, DRAMCTRL_REQQUE_THD_EN);
6402 //| P_Fld(0x1, DRAMCTRL_DPDRK_OPT));
6403 vIO32WriteFldMulti(DRAMC_REG_DUMMY_RD, P_Fld(0x1, DUMMY_RD_DQSG_DMYRD_EN)
6404 | P_Fld(p->support_rank_num, DUMMY_RD_RANK_NUM)
6405 | P_Fld(0x1, DUMMY_RD_DUMMY_RD_CNT6)
6406 | P_Fld(0x1, DUMMY_RD_DUMMY_RD_CNT5)
6407 | P_Fld(0x1, DUMMY_RD_DUMMY_RD_CNT3)
6408 | P_Fld(0x1, DUMMY_RD_DUMMY_RD_SW));
6409 vIO32WriteFldAlign(DRAMC_REG_TEST2_4, 0x4, TEST2_4_TESTAGENTRKSEL);
6410 vIO32WriteFldAlign(DRAMC_REG_DRAMCTRL, 0x0, DRAMCTRL_CTOREQ_HPRI_OPT);
6411
6412
6413
6414
6415 mcDELAY_US(1);
6416
6417 //*((UINT32P)(DDRPHY0AO_BASE + 0x0000)) = 0x00000000;
6418
6419 mcDELAY_US(1);
6420
6421 DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
6422
6423 vIO32WriteFldMulti(DRAMC_REG_SHUCTRL, P_Fld(0x1, SHUCTRL_R_DRAMC_CHA) | P_Fld(0x0, SHUCTRL_SHU_PHYRST_SEL));
6424 vIO32WriteFldAlign(DRAMC_REG_SHUCTRL2, 0x1, SHUCTRL2_R_DVFS_DLL_CHA);
6425
6426 vIO32WriteFldMulti(DRAMC_REG_SHUCTRL + SHIFT_TO_CHB_ADDR, P_Fld(0x0, SHUCTRL_R_DRAMC_CHA) | P_Fld(0x1, SHUCTRL_SHU_PHYRST_SEL));
6427 vIO32WriteFldAlign(DRAMC_REG_SHUCTRL2 + SHIFT_TO_CHB_ADDR, 0x0, SHUCTRL2_R_DVFS_DLL_CHA);
6428
6429
6430 #ifndef LOOPBACK_TEST
6431 DDRPhyFMeter_Init(p);
6432 #endif
6433
6434 DVFSSettings(p);
6435
6436 }
6437 #endif // __A60868_TO_BE_PORTING__
6438
6439 #if 0
6440 void vApplyConfigAfterCalibration(DRAMC_CTX_T *p)
6441 {
6442 #if __A60868_TO_BE_PORTING__
6443
6444 U8 shu_index;
6445 #if ENABLE_TMRRI_NEW_MODE
6446 U8 u1RankIdx;
6447 #endif
6448
6449
6450 vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL4, 0x11400000, MISC_CG_CTRL4_R_PHY_MCK_CG_CTRL);
6451 vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL1, 0x0, REFCTRL1_SREF_CG_OPT);
6452 vIO32WriteFldAlign_All(DRAMC_REG_SHUCTRL, 0x0, SHUCTRL_DVFS_CG_OPT);
6453
6454
6455
6456 vIO32WriteFldAlign_All(DDRPHY_CA_CMD6, 0x0, CA_CMD6_RG_RX_ARCMD_RES_BIAS_EN);
6457 #if 0
6458 vIO32WriteFldAlign_All(DDRPHY_B0_DQ6, 0x0, B0_DQ6_RG_TX_ARDQ_OE_EXT_DIS_B0);
6459 vIO32WriteFldAlign_All(DDRPHY_B1_DQ6, 0x0, B1_DQ6_RG_TX_ARDQ_OE_EXT_DIS_B1);
6460 vIO32WriteFldAlign_All(DDRPHY_CA_CMD6, 0x0, CA_CMD6_RG_TX_ARCMD_OE_EXT_DIS);
6461 #endif
6462
6463 #if ENABLE_WRITE_DBI
6464 EnableDRAMModeRegWriteDBIAfterCalibration(p);
6465 #endif
6466
6467 #if ENABLE_READ_DBI
6468 EnableDRAMModeRegReadDBIAfterCalibration(p);
6469 #endif
6470
6471
6472 SetMr13VrcgToNormalOperation(p);
6473
6474
6475 vIO32WriteFldAlign_All(DDRPHY_B0_DQ6, 0x0, B0_DQ6_RG_RX_ARDQ_BIAS_PS_B0);
6476 vIO32WriteFldAlign_All(DDRPHY_B1_DQ6, 0x0, B1_DQ6_RG_RX_ARDQ_BIAS_PS_B1);
6477 vIO32WriteFldAlign_All(DDRPHY_CA_CMD6, 0x0, CA_CMD6_RG_RX_ARCMD_BIAS_PS);
6478
6479 vIO32WriteFldAlign_All(DDRPHY_B0_DQ6, 0x1, B0_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B0);
6480 vIO32WriteFldAlign_All(DDRPHY_B1_DQ6, 0x1, B1_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B1);
6481 vIO32WriteFldAlign_All(DDRPHY_CA_CMD6, 0x1, CA_CMD6_RG_RX_ARCMD_RPRE_TOG_EN);
6482
6483
6484 vIO32WriteFldMulti_All(DRAMC_REG_IMPCAL, P_Fld(0, IMPCAL_IMPCAL_IMPPDP) | P_Fld(0, IMPCAL_IMPCAL_IMPPDN));
6485 vIO32WriteFldAlign_All(DDRPHY_MISC_IMP_CTRL0, 0, MISC_IMP_CTRL0_RG_IMP_EN);
6486
6487
6488 vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL0, 0, Fld(4, 0, AC_MSKB0));
6489
6490
6491 vIO32WriteFldAlign_All(DDRPHY_MISC_CTRL0, 0, MISC_CTRL0_R_STBENCMP_DIV4CK_EN);
6492 vIO32WriteFldAlign_All(DDRPHY_MISC_CTRL1, 0, MISC_CTRL1_R_DMSTBENCMP_RK_OPT);
6493
6494
6495 vIO32WriteFldAlign_All(DRAMC_REG_SPCMDCTRL, 0x1, SPCMDCTRL_REFRDIS);
6496
6497 vIO32WriteFldMulti_All(DRAMC_REG_DUMMY_RD, P_Fld(0x0, DUMMY_RD_DUMMY_RD_EN)
6498 | P_Fld(0x0, DUMMY_RD_SREF_DMYRD_EN)
6499 | P_Fld(0x0, DUMMY_RD_DQSG_DMYRD_EN)
6500 | P_Fld(0x0, DUMMY_RD_DMY_RD_DBG));
6501
6502 #if APPLY_LP4_POWER_INIT_SEQUENCE
6503
6504 #if ENABLE_TMRRI_NEW_MODE
6505 CKEFixOnOff(p, TO_ALL_RANK, CKE_DYNAMIC, TO_ALL_CHANNEL);
6506 #else
6507 CKEFixOnOff(p, RANK_0, CKE_DYNAMIC, TO_ALL_CHANNEL);
6508 #endif
6509
6510
6511 DramCLKAlwaysOnOff(p, OFF);
6512 #endif
6513
6514
6515 vIO32WriteFldMulti_All(DRAMC_REG_EYESCAN, P_Fld(0x0, EYESCAN_EYESCAN_DQS_SYNC_EN)
6516 | P_Fld(0x0, EYESCAN_EYESCAN_NEW_DQ_SYNC_EN)
6517 | P_Fld(0x0, EYESCAN_EYESCAN_DQ_SYNC_EN));
6518
6519
6520 vIO32WriteFldAlign_All(DRAMC_REG_TEST2_4, 4, TEST2_4_TESTAGENTRKSEL);
6521 #endif
6522 }
6523 #endif
6524
vReplaceDVInit(DRAMC_CTX_T * p)6525 static void vReplaceDVInit(DRAMC_CTX_T *p)
6526 {
6527 U8 u1RandIdx, backup_rank = 0;
6528
6529 backup_rank = p->rank;
6530
6531
6532 vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5), P_Fld(0, B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1));
6533 vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ5), P_Fld(0, B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0));
6534 vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_RXDVS0), P_Fld(0, B0_RXDVS0_R_RX_DLY_TRACK_ENA_B0)
6535 | P_Fld(0, B0_RXDVS0_R_RX_DLY_TRACK_CG_EN_B0 ));
6536 vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_RXDVS0), P_Fld(0, B1_RXDVS0_R_RX_DLY_TRACK_ENA_B1)
6537 | P_Fld(0, B1_RXDVS0_R_RX_DLY_TRACK_CG_EN_B1 ));
6538
6539 for(u1RandIdx = RANK_0; u1RandIdx < p->support_rank_num; u1RandIdx++)
6540 {
6541 vSetRank(p, u1RandIdx);
6542 vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B0_RXDVS2), P_Fld(0, RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0)
6543 | P_Fld(0, RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0)
6544 | P_Fld(0, RK_B0_RXDVS2_R_RK0_DVS_MODE_B0));
6545 vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B1_RXDVS2), P_Fld(0, RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1)
6546 | P_Fld(0, RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1)
6547 | P_Fld(0, RK_B1_RXDVS2_R_RK0_DVS_MODE_B1));
6548 }
6549 vSetRank(p, backup_rank);
6550
6551 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL1), 0, CBT_WLEV_CTRL1_CATRAINLAT);
6552 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL1), 0, SWCMD_CTRL1_WRFIFO_MODE2);
6553
6554
6555
6556 {
6557 U32 backup_broadcast = GetDramcBroadcast();
6558 DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
6559
6560 U8 u1DQ_HYST_SEL=0x1, u1CA_HYST_SEL=0x1;
6561 U8 u1DQ_CAP_SEL=0x1b, u1CA_CAP_SEL=0x1b;
6562
6563 if(p->frequency<=933)
6564 {
6565 u1DQ_HYST_SEL = 0x1;
6566 u1CA_HYST_SEL = 0x1;
6567 }
6568 else
6569 {
6570 u1DQ_HYST_SEL = 0x0;
6571 u1CA_HYST_SEL = 0x0;
6572 }
6573
6574 if(p->frequency<=400)
6575 {
6576 u1DQ_CAP_SEL= 0xf;
6577 u1CA_CAP_SEL= 0xf;
6578 }
6579 else if(p->frequency<=600)
6580 {
6581 u1DQ_CAP_SEL= 0x1b;
6582 u1CA_CAP_SEL= 0x1b;
6583 }
6584 else if(p->frequency<=1200)
6585 {
6586 u1DQ_CAP_SEL= 0xf;
6587 u1CA_CAP_SEL= 0xf;
6588 }
6589 else if(p->frequency<=1600)
6590 {
6591 u1DQ_CAP_SEL= 0xd;
6592 u1CA_CAP_SEL= 0xd;
6593 }
6594 else if(p->frequency<=2133)
6595 {
6596 u1DQ_CAP_SEL= 0xb;
6597 u1CA_CAP_SEL= 0xb;
6598 }
6599
6600 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ6, P_Fld(u1DQ_HYST_SEL, SHU_B0_DQ6_RG_ARPI_HYST_SEL_B0)
6601 | P_Fld(u1DQ_CAP_SEL, SHU_B0_DQ6_RG_ARPI_CAP_SEL_B0));
6602 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ6, P_Fld(u1DQ_HYST_SEL, SHU_B1_DQ6_RG_ARPI_HYST_SEL_B1)
6603 | P_Fld(u1DQ_CAP_SEL, SHU_B1_DQ6_RG_ARPI_CAP_SEL_B1));
6604 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD6, P_Fld(u1CA_HYST_SEL, SHU_CA_CMD6_RG_ARPI_HYST_SEL_CA)
6605 | P_Fld(u1CA_CAP_SEL, SHU_CA_CMD6_RG_ARPI_CAP_SEL_CA));
6606
6607
6608 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ2,P_Fld((p->frequency>=2133), SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B0)
6609 | P_Fld((p->frequency>=2133), SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B0)
6610 | P_Fld((p->frequency==1200), SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B0)
6611 | P_Fld((p->frequency==1200), SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B0));
6612 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ2,P_Fld((p->frequency>=2133), SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B1)
6613 | P_Fld((p->frequency>=2133), SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B1)
6614 | P_Fld((p->frequency==1200), SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B1)
6615 | P_Fld((p->frequency==1200), SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B1));
6616 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD2,P_Fld((p->frequency>=2133), SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CLK_CA)
6617 | P_Fld((p->frequency>=2133), SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CA_CA)
6618 | P_Fld((p->frequency==1200), SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_FORCE_CLK_CA)
6619 | P_Fld((p->frequency==1200), SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_CA_FORCE_CA));
6620
6621
6622 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL, 0x0, SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN);
6623
6624
6625 vIO32Write4B_All(DDRPHY_REG_MISC_DBG_IRQ_CTRL1, 0x0);
6626 vIO32Write4B_All(DDRPHY_REG_MISC_DBG_IRQ_CTRL4, 0x0);
6627 vIO32Write4B_All(DDRPHY_REG_MISC_DBG_IRQ_CTRL7, 0x0);
6628
6629
6630 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_RX_CG_CTRL, P_Fld(0, MISC_SHU_RX_CG_CTRL_RX_DCM_WAIT_DLE_EXT_DLY)
6631 | P_Fld(2, MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY)
6632 | P_Fld(0, MISC_SHU_RX_CG_CTRL_RX_APHY_CTRL_DCM_OPT)
6633 | P_Fld(0, MISC_SHU_RX_CG_CTRL_RX_DCM_OPT));
6634
6635 vIO32WriteFldAlign_All(DRAMC_REG_HMR4, 0, HMR4_MR4INT_LIMITEN);
6636 vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL1, 0, REFCTRL1_REFPEND_OPT1);
6637 vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL3, 0, REFCTRL3_REF_DERATING_EN);
6638
6639 vIO32WriteFldMulti_All(DRAMC_REG_DRAMC_IRQ_EN, P_Fld(0x3fff, DRAMC_IRQ_EN_DRAMC_IRQ_EN_RSV)
6640 | P_Fld(0x0, DRAMC_IRQ_EN_MR4INT_EN));
6641 vIO32WriteFldAlign_All(DRAMC_REG_SHU_CONF0, 0, SHU_CONF0_PBREFEN);
6642
6643
6644
6645 vIO32WriteFldAlign_All(DDRPHY_REG_CA_TX_MCK, 0x1, CA_TX_MCK_R_DMRESET_FRPHY_OPT);
6646 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFSCTL2, 0x1, MISC_DVFSCTL2_RG_ADA_MCK8X_EN_SHUFFLE);
6647 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_IMPCAL, 0x1, MISC_IMPCAL_IMPBINARY);
6648
6649 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ10, P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B0)
6650 | P_Fld(0x1, SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B0));
6651 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ10, P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B1)
6652 | P_Fld(0x1, SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B1));
6653 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD10, P_Fld(0x1, SHU_CA_CMD10_RG_RX_ARCLK_DQSSTB_RPST_HS_EN_CA)
6654 | P_Fld(0x1, SHU_CA_CMD10_RG_RX_ARCLK_DQSSTB_CG_EN_CA));
6655
6656 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ8, P_Fld(1, SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0)
6657 | P_Fld(1, SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0)
6658 | P_Fld(1, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0)
6659 | P_Fld(1, SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0)
6660 | P_Fld(1, SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0)
6661 | P_Fld(1, SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0)
6662 | P_Fld(1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0)
6663 | P_Fld(1, SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0)
6664 | P_Fld(1, SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0)
6665 | P_Fld(1, SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0)
6666 | P_Fld(1, SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0));
6667 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ8, P_Fld(1, SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1)
6668 | P_Fld(1, SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1)
6669 | P_Fld(1, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1)
6670 | P_Fld(1, SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1)
6671 | P_Fld(1, SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1)
6672 | P_Fld(1, SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1)
6673 | P_Fld(1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1)
6674 | P_Fld(1, SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1)
6675 | P_Fld(1, SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1)
6676 | P_Fld(1, SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1)
6677 | P_Fld(1, SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1));
6678
6679 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DLL2, 0x1, SHU_B0_DLL2_RG_ARDQ_REV_B0);
6680 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DLL2, 0x1, SHU_B1_DLL2_RG_ARDQ_REV_B1);
6681 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_DLL2, 0x1, SHU_CA_DLL2_RG_ARCMD_REV);
6682
6683 #if 1
6684
6685 //vIO32WriteFldAlign_All(DRAMC_REG_DDRCOMMON0, 1, DDRCOMMON0_DISSTOP26M);
6686 //vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A3, 1, TEST2_A3_TEST_AID_EN);
6687 //vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A4, 0, TEST2_A4_TESTAGENTRKSEL);
6688 vIO32WriteFldAlign_All(DRAMC_REG_DUMMY_RD, 0, DUMMY_RD_DQSG_DMYRD_EN);
6689 vIO32WriteFldAlign_All(DRAMC_REG_DRAMC_DBG_SEL1, 0x1e, DRAMC_DBG_SEL1_DEBUG_SEL_0);
6690 vIO32WriteFldAlign_All(DRAMC_REG_SWCMD_CTRL2, 0x20, SWCMD_CTRL2_RTSWCMD_AGE);
6691 vIO32WriteFldAlign_All(DRAMC_REG_RTMRW_CTRL0, 0x20, RTMRW_CTRL0_RTMRW_AGE);
6692
6693
6694 vIO32WriteFldMulti_All(DRAMC_REG_DLLFRZ_CTRL, P_Fld(0, DLLFRZ_CTRL_DLLFRZ) | P_Fld(0, DLLFRZ_CTRL_DLLFRZ_MON_PBREF_OPT));
6695 vIO32WriteFldMulti_All(DRAMC_REG_MPC_CTRL, P_Fld(1, MPC_CTRL_RTSWCMD_HPRI_EN) | P_Fld(1, MPC_CTRL_RTMRW_HPRI_EN));
6696 vIO32WriteFldMulti_All(DRAMC_REG_HW_MRR_FUN, P_Fld(0, HW_MRR_FUN_R2MRRHPRICTL) | P_Fld(0, HW_MRR_FUN_TR2MRR_ENA));
6697 vIO32WriteFldMulti_All(DRAMC_REG_ACTIMING_CTRL, P_Fld(1, ACTIMING_CTRL_REFNA_OPT) | P_Fld(1, ACTIMING_CTRL_SEQCLKRUN3));
6698 vIO32WriteFldAlign_All(DRAMC_REG_CKECTRL, 1, CKECTRL_RUNTIMEMRRCKEFIX);
6699 vIO32WriteFldMulti_All(DRAMC_REG_DVFS_CTRL0, P_Fld(0, DVFS_CTRL0_DVFS_SYNC_MASK) | P_Fld(1, DVFS_CTRL0_R_DVFS_SREF_OPT));
6700 vIO32WriteFldAlign_All(DRAMC_REG_DVFS_TIMING_CTRL1, 1, DVFS_TIMING_CTRL1_SHU_PERIOD_GO_ZERO_CNT);
6701 vIO32WriteFldMulti_All(DRAMC_REG_HMR4, P_Fld(1, HMR4_REFRCNT_OPT)
6702 | P_Fld(0, HMR4_REFR_PERIOD_OPT)
6703 | P_Fld(1, HMR4_SPDR_MR4_OPT)
6704 | P_Fld(0, HMR4_HMR4_TOG_OPT));
6705 vIO32WriteFldAlign_All(DRAMC_REG_RX_SET0, 0, RX_SET0_SMRR_UPD_OLD);
6706 vIO32WriteFldAlign_All(DRAMC_REG_DRAMCTRL, 1, DRAMCTRL_SHORTQ_OPT);
6707 vIO32WriteFldAlign_All(DRAMC_REG_MISCTL0, 1, MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS);
6708 #if ENABLE_EARLY_BG_CMD==0
6709 vIO32WriteFldAlign_All(DRAMC_REG_PERFCTL0, 0, PERFCTL0_EBG_EN);
6710 #endif
6711 vIO32WriteFldMulti_All(DRAMC_REG_CLKAR, P_Fld(1, CLKAR_REQQUECLKRUN) | P_Fld(0x7fff, CLKAR_REQQUE_PACG_DIS));
6712 vIO32WriteFldMulti_All(DRAMC_REG_REFCTRL0, P_Fld(0, REFCTRL0_PBREF_BK_REFA_ENA) | P_Fld(0, REFCTRL0_PBREF_BK_REFA_NUM));
6713 vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL1, 0, REFCTRL1_REF_OVERHEAD_SLOW_REFPB_ENA);
6714 vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL1, 0, REFCTRL1_REFPB2AB_IGZQCS);
6715 vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL1, 1, REFCTRL1_REFPENDINGINT_OPT1);
6716 vIO32WriteFldAlign_All(DRAMC_REG_REF_BOUNCE1,5, REF_BOUNCE1_REFRATE_DEBOUNCE_TH);
6717 vIO32WriteFldAlign_All(DRAMC_REG_REFPEND2, 8, REFPEND2_MPENDREFCNT_TH8);
6718 vIO32WriteFldAlign_All(DRAMC_REG_SCSMCTRL, 0, SCSMCTRL_SC_PG_MAN_DIS);
6719 vIO32WriteFldMulti_All(DRAMC_REG_SCSMCTRL_CG, P_Fld(1, SCSMCTRL_CG_SCSM_CGAR)
6720 | P_Fld(1, SCSMCTRL_CG_SCARB_SM_CGAR));
6721 vIO32WriteFldAlign_All(DRAMC_REG_RTSWCMD_CNT, 0x30, RTSWCMD_CNT_RTSWCMD_CNT);
6722 vIO32WriteFldAlign_All(DRAMC_REG_DRAMC_IRQ_EN, 0x3fff, DRAMC_IRQ_EN_DRAMC_IRQ_EN_RSV);
6723 vIO32WriteFldAlign_All(DRAMC_REG_SHU_DCM_CTRL0, 1, SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT);
6724 vIO32WriteFldMulti_All(DRAMC_REG_SHU_HMR4_DVFS_CTRL0, P_Fld(0x1ff, SHU_HMR4_DVFS_CTRL0_REFRCNT) | P_Fld(0, SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT));
6725 vIO32WriteFldAlign_All(DRAMC_REG_SHU_HWSET_VRCG, 11, SHU_HWSET_VRCG_VRCGDIS_PRDCNT);
6726 vIO32WriteFldAlign_All(DRAMC_REG_SHU_MISC, 2, SHU_MISC_REQQUE_MAXCNT);
6727 vIO32WriteFldAlign_All(DRAMC_REG_SREF_DPD_CTRL, 0, SREF_DPD_CTRL_DSM_HW_EN);
6728
6729
6730
6731 vIO32WriteFldMulti_All(DDRPHY_REG_B0_DLL_ARPI4, P_Fld(1, B0_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQS_B0) | P_Fld(1, B0_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQ_B0));
6732 vIO32WriteFldMulti_All(DDRPHY_REG_B1_DLL_ARPI4, P_Fld(1, B1_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQS_B1) | P_Fld(1, B1_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQ_B1));
6733 vIO32WriteFldMulti_All(DDRPHY_REG_CA_DLL_ARPI4, P_Fld(1, CA_DLL_ARPI4_RG_ARPI_BYPASS_SR_CLK_CA) | P_Fld(1, CA_DLL_ARPI4_RG_ARPI_BYPASS_SR_CA_CA));
6734 vIO32WriteFldMulti_All(DDRPHY_REG_CA_CMD11, P_Fld(0xa, CA_CMD11_RG_RRESETB_DRVN) | P_Fld(0xa, CA_CMD11_RG_RRESETB_DRVP));
6735 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL2, 0x1f, MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL);
6736
6737 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQSIEN_CFG, 1, SHU_B0_DQSIEN_CFG_RG_RX_ARDQS_DQSIEN_GLITCH_FREE_EN_B0);
6738 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQSIEN_CFG, 1, SHU_B1_DQSIEN_CFG_RG_RX_ARDQS_DQSIEN_GLITCH_FREE_EN_B1);
6739 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_DQSIEN_CFG, 1, SHU_CA_DQSIEN_CFG_RG_RX_ARCLK_DQSIEN_GLITCH_FREE_EN_C0);
6740
6741
6742 #if (ENABLE_DDR400_OPEN_LOOP_MODE_OPTION == 0)
6743 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL9, P_Fld(0, MISC_CG_CTRL9_RG_MCK4X_O_FB_CK_CG_OFF)
6744 | P_Fld(0, MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_O_OFF)
6745 | P_Fld(0, MISC_CG_CTRL9_RG_MCK4X_O_OPENLOOP_MODE_EN)
6746 | P_Fld(0, MISC_CG_CTRL9_RG_MCK4X_Q_FB_CK_CG_OFF)
6747 | P_Fld(0, MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_Q_OFF)
6748 | P_Fld(0, MISC_CG_CTRL9_RG_MCK4X_Q_OPENLOOP_MODE_EN)
6749 | P_Fld(0, MISC_CG_CTRL9_RG_MCK4X_I_FB_CK_CG_OFF)
6750 | P_Fld(0, MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_I_OFF)
6751 | P_Fld(0, MISC_CG_CTRL9_RG_MCK4X_I_OPENLOOP_MODE_EN)
6752 | P_Fld(0, MISC_CG_CTRL9_RG_M_CK_OPENLOOP_MODE_EN));
6753 #endif
6754 //vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFSCTL, 1, MISC_DVFSCTL_R_SHUFFLE_PI_RESET_ENABLE);
6755 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL2, P_Fld(1, MISC_DVFSCTL2_RG_ADA_MCK8X_EN_SHUFFLE)
6756 | P_Fld(0, MISC_DVFSCTL2_RG_DLL_SHUFFLE));
6757
6758 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL3, P_Fld(0x10, MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_BCLK)
6759 | P_Fld(1, MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_SOURCE)
6760 | P_Fld(3, MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_DESTI)
6761 | P_Fld(1, MISC_DVFSCTL3_RG_PHY_ST_DELAY_BEF_CHG_TO_BCLK)
6762 | P_Fld(1, MISC_DVFSCTL3_RG_PHY_ST_DELAY_AFT_CHG_TO_MCLK));
6763
6764 //vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL);
6765 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DDR_RESERVE, 0xf, MISC_DDR_RESERVE_WDT_CONF_ISO_CNT);
6766 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_IMP_CTRL1, P_Fld(1, MISC_IMP_CTRL1_RG_RIMP_SUS_ECO_OPT) | P_Fld(1, MISC_IMP_CTRL1_IMP_ABN_LAT_CLR));
6767 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_IMPCAL, P_Fld(1, MISC_IMPCAL_IMPCAL_BYPASS_UP_CA_DRV)
6768 | P_Fld(1, MISC_IMPCAL_IMPCAL_DRVUPDOPT)
6769 | P_Fld(1, MISC_IMPCAL_IMPBINARY)
6770 | P_Fld(1, MISC_IMPCAL_DQDRVSWUPD)
6771 | P_Fld(0, MISC_IMPCAL_DRVCGWREF));
6772
6773 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DUTYSCAN1, P_Fld(1, MISC_DUTYSCAN1_EYESCAN_DQS_OPT) | P_Fld(1, MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN));
6774 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFS_EMI_CLK, 0, MISC_DVFS_EMI_CLK_RG_DLL_SHUFFLE_DDRPHY);
6775
6776 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CTRL0, P_Fld(0, MISC_CTRL0_IDLE_DCM_CHB_CDC_ECO_OPT)
6777 | P_Fld(1, MISC_CTRL0_IMPCAL_CDC_ECO_OPT)
6778 | P_Fld(1, MISC_CTRL0_IMPCAL_LP_ECO_OPT));
6779
6780 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CTRL4, P_Fld(0, MISC_CTRL4_R_OPT2_CG_CS)
6781 | P_Fld(0, MISC_CTRL4_R_OPT2_CG_CLK)
6782 | P_Fld(0, MISC_CTRL4_R_OPT2_CG_CMD)
6783 | P_Fld(0, MISC_CTRL4_R_OPT2_CG_DQSIEN)
6784 | P_Fld(0, MISC_CTRL4_R_OPT2_CG_DQ)
6785 | P_Fld(0, MISC_CTRL4_R_OPT2_CG_DQS)
6786 | P_Fld(0, MISC_CTRL4_R_OPT2_CG_DQM)
6787 | P_Fld(0, MISC_CTRL4_R_OPT2_CG_MCK)
6788 | P_Fld(0, MISC_CTRL4_R_OPT2_MPDIV_CG));
6789 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CTRL6, P_Fld(1, MISC_CTRL6_RG_ADA_MCK8X_EN_SHU_OPT) | P_Fld(1, MISC_CTRL6_RG_PHDET_EN_SHU_OPT));
6790
6791 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RX_AUTOK_CFG0, 1, MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN);
6792
6793 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ1, P_Fld(1, SHU_B0_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B0)
6794 | P_Fld(1, SHU_B0_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B0)
6795 | P_Fld(1, SHU_B0_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B0));
6796 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ1, P_Fld(1, SHU_B1_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B1)
6797 | P_Fld(1, SHU_B1_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B1)
6798 | P_Fld(1, SHU_B1_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B1));
6799 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD1, P_Fld(1, SHU_CA_CMD1_RG_ARPI_MIDPI_BYPASS_EN_CA)
6800 | P_Fld(1, SHU_CA_CMD1_RG_ARPI_MIDPI_DUMMY_EN_CA)
6801 | P_Fld(1, SHU_CA_CMD1_RG_ARPI_8PHASE_XLATCH_FORCE_CA));
6802
6803 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ10, 1, SHU_B0_DQ10_RG_RX_ARDQS_BW_SEL_B0);
6804 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ10, 1, SHU_B1_DQ10_RG_RX_ARDQS_BW_SEL_B1);
6805 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD10, 1, SHU_CA_CMD10_RG_RX_ARCLK_BW_SEL_CA);
6806
6807
6808 {
6809 U8 u1DQ_BW_SEL_B0=0, u1DQ_BW_SEL_B1=0, u1CA_BW_SEL_CA=0;
6810
6811 if (p->frequency >= 2133)
6812 {
6813 u1DQ_BW_SEL_B0 = 3;
6814 u1DQ_BW_SEL_B1 = 3;
6815 u1CA_BW_SEL_CA = 3;
6816 }
6817
6818 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ11, u1DQ_BW_SEL_B0, SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0);
6819 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ11, u1DQ_BW_SEL_B1, SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1);
6820 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD11, u1CA_BW_SEL_CA, SHU_CA_CMD11_RG_RX_ARCA_BW_SEL_CA);
6821 }
6822
6823 //vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD1, P_Fld(1, SHU_CA_CMD1_RG_ARPI_MIDPI_BYPASS_EN_CA) | P_Fld(1, SHU_CA_CMD1_RG_ARPI_MIDPI_DUMMY_EN_CA));
6824 //vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD10, 1, SHU_CA_CMD10_RG_RX_ARCLK_DLY_LAT_EN_CA);
6825
6826 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD12, 0, SHU_CA_CMD12_RG_RIMP_REV);
6827
6828
6829 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_IMPEDAMCE_UPD_DIS1, P_Fld(1, MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_ODTN_UPD_DIS)
6830 | P_Fld(1, MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_DRVN_UPD_DIS)
6831 | P_Fld(1, MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_DRVP_UPD_DIS)
6832 | P_Fld(1, MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_ODTN_UPD_DIS)
6833 | P_Fld(1, MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_DRVN_UPD_DIS)
6834 | P_Fld(1, MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_DRVP_UPD_DIS));
6835
6836 //vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_DVFSDLL, P_Fld(67, MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE) | P_Fld(43, MISC_SHU_DVFSDLL_R_DLL_IDLE));
6837
6838 //vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_IMPCAL1, 0, SHU_MISC_IMPCAL1_IMPCALCNT);
6839 //vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_DRVING2, 0, SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN);
6840 //vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_DRVING6, 7, SHU_MISC_DRVING6_IMP_TXDLY_CMD);
6841
6842 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_RX_CG_CTRL, P_Fld(0, MISC_SHU_RX_CG_CTRL_RX_DCM_WAIT_DLE_EXT_DLY)
6843 | P_Fld(2, MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY)
6844 | P_Fld(0, MISC_SHU_RX_CG_CTRL_RX_APHY_CTRL_DCM_OPT)
6845 | P_Fld(0, MISC_SHU_RX_CG_CTRL_RX_DCM_OPT));
6846 #endif
6847 DramcBroadcastOnOff(backup_broadcast);
6848 }
6849 }
6850
6851
vApplyConfigBeforeCalibration(DRAMC_CTX_T * p)6852 void vApplyConfigBeforeCalibration(DRAMC_CTX_T *p)
6853 {
6854 #if __A60868_TO_BE_PORTING__
6855
6856 U8 read_xrtw2w, shu_index;
6857 U8 u1RankIdx, u1RankIdxBak;
6858 u1RankIdxBak = u1GetRank(p);
6859
6860
6861 #if (SW_CHANGE_FOR_SIMULATION == 0)
6862 EnableDramcPhyDCM(p, 0);
6863 #endif
6864
6865
6866 #if (FOR_DV_SIMULATION_USED == 0)
6867
6868 vResetDelayChainBeforeCalibration(p);
6869 #endif
6870
6871
6872 vIO32WriteFldAlign_All(DRAMC_REG_SHU_CONF3, 0x1ff, SHU_CONF3_REFRCNT);
6873
6874
6875 vIO32WriteFldAlign_All(DRAMC_REG_SPCMDCTRL, 1, SPCMDCTRL_SRFMR4_CNTKEEP_B);
6876
6877
6878 vIO32WriteFldAlign_All(DRAMC_REG_SHU_SCINTV, 0x1B, SHU_SCINTV_TZQLAT);
6879 //for(shu_index = SRAM_SHU0; shu_index < DRAM_DFS_SRAM_MAX; shu_index++)
6880 //vIO32WriteFldAlign_All(DRAMC_REG_SHU_CONF3 + SHU_GRP_DRAMC_OFFSET*shu_index, 0x1ff, SHU_CONF3_ZQCSCNT);
6881 vIO32WriteFldAlign_All(DRAMC_REG_SHU_CONF3, 0x1ff, SHU_CONF3_ZQCSCNT);
6882 //vIO32WriteFldAlign_All(DRAMC_REG_SHU2_CONF3, 0x1ff, SHU_CONF3_ZQCSCNT);
6883 //vIO32WriteFldAlign_All(DRAMC_REG_SHU3_CONF3, 0x1ff, SHU_CONF3_ZQCSCNT);
6884 vIO32WriteFldAlign_All(DRAMC_REG_DRAMCTRL, 0, DRAMCTRL_ZQCALL);
6885
6886
6887 if (p->support_channel_num == CHANNEL_SINGLE)
6888 {
6889
6890 vIO32WriteFldMulti(DRAMC_REG_ZQCS, P_Fld(0, ZQCS_ZQCSDUAL) | P_Fld(0x0, ZQCS_ZQCSMASK));
6891 }
6892 else if (p->support_channel_num == CHANNEL_DUAL)
6893 {
6894
6895 #ifdef ZQCS_ENABLE_LP4
6896
6897
6898 vIO32WriteFldMulti_All(DRAMC_REG_ZQCS, P_Fld(1, ZQCS_ZQCSDUAL) | \
6899 P_Fld(0, ZQCS_ZQCSMASK_OPT) | \
6900 P_Fld(0, ZQCS_ZQMASK_CGAR) | \
6901 P_Fld(0, ZQCS_ZQCS_MASK_SEL_CGAR));
6902
6903 vIO32WriteFldAlign(DRAMC_REG_ZQCS + (CHANNEL_A << POS_BANK_NUM), 1, ZQCS_ZQCSMASK);
6904 vIO32WriteFldAlign(DRAMC_REG_ZQCS + SHIFT_TO_CHB_ADDR, 0, ZQCS_ZQCSMASK);
6905
6906
6907 vIO32WriteFldAlign_All(DRAMC_REG_ZQCS, 0, ZQCS_ZQCS_MASK_SEL);
6908 #endif
6909 }
6910
6911
6912 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SPCMDCTRL), 0, SPCMDCTRL_ZQCSDISB);
6913
6914 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SPCMDCTRL), 0, SPCMDCTRL_ZQCALDISB);
6915
6916
6917
6918 DramcWriteDBIOnOff(p, DBI_OFF);
6919
6920 DramcReadDBIOnOff(p, DBI_OFF);
6921
6922 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SPCMDCTRL), 1, SPCMDCTRL_REFRDIS);
6923 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 0x1, DQSOSCR_DQSOSCRDIS);
6924 //for(shu_index = SRAM_SHU0; shu_index < DRAM_DFS_SRAM_MAX; shu_index++)
6925 //vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SHU_SCINTV) + SHU_GRP_DRAMC_OFFSET*shu_index, 0x1, SHU_SCINTV_DQSOSCENDIS);
6926 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SHU_SCINTV), 0x1, SHU_SCINTV_DQSOSCENDIS);
6927 //vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SHU2_SCINTV), 0x1, SHU2_SCINTV_DQSOSCENDIS);
6928 //vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_SHU3_SCINTV), 0x1, SHU3_SCINTV_DQSOSCENDIS);
6929 vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD), P_Fld(0x0, DUMMY_RD_DUMMY_RD_EN)
6930 | P_Fld(0x0, DUMMY_RD_SREF_DMYRD_EN)
6931 | P_Fld(0x0, DUMMY_RD_DQSG_DMYRD_EN)
6932 | P_Fld(0x0, DUMMY_RD_DMY_RD_DBG));
6933
6934
6935 DramcHWGatingOnOff(p, 0);
6936
6937
6938 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_STBCAL2), 0, STBCAL2_STB_GERRSTOP);
6939
6940 for (u1RankIdx = RANK_0; u1RankIdx < RANK_MAX; u1RankIdx++)
6941 {
6942 vSetRank(p, u1RankIdx);
6943
6944
6945 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_R0_B0_RXDVS2), 0x0, R0_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0);
6946 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_R0_B1_RXDVS2), 0x0, R0_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1);
6947
6948 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_R0_B0_RXDVS2), 0x0, R0_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0);
6949 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_R0_B1_RXDVS2), 0x0, R0_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1);
6950
6951
6952 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_R0_B0_RXDVS2), 0x0, R0_B0_RXDVS2_R_RK0_DVS_MODE_B0);
6953 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_R0_B1_RXDVS2), 0x0, R0_B1_RXDVS2_R_RK0_DVS_MODE_B1);
6954 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_R0_CA_RXDVS2), 0x0, R0_CA_RXDVS2_R_RK0_DVS_MODE_CA);
6955 }
6956 vSetRank(p, u1RankIdxBak);
6957
6958
6959 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0), 0, REFCTRL0_PBREFEN);
6960
6961
6962 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_MRS), 0, MRS_MRSRK);
6963 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_MPC_OPTION), 1, MPC_OPTION_MPCRKEN);
6964
6965
6966 vIO32WriteFldAlign_All(DDRPHY_B0_DQ6, 0x1, B0_DQ6_RG_RX_ARDQ_BIAS_PS_B0);
6967 vIO32WriteFldAlign_All(DDRPHY_B1_DQ6, 0x1, B1_DQ6_RG_RX_ARDQ_BIAS_PS_B1);
6968 vIO32WriteFldAlign_All(DDRPHY_CA_CMD6, 0x1, CA_CMD6_RG_RX_ARCMD_BIAS_PS);
6969
6970 #if ENABLE_RX_TRACKING
6971 DramcRxInputDelayTrackingInit_byFreq(p);
6972 #endif
6973
6974 #ifdef LOOPBACK_TEST
6975 #ifdef LPBK_INTERNAL_EN
6976 DramcLoopbackTest_settings(p, 0);
6977 #else
6978 DramcLoopbackTest_settings(p, 1);
6979 #endif
6980 #endif
6981
6982 #if ENABLE_TMRRI_NEW_MODE
6983 SetCKE2RankIndependent(p);
6984 #endif
6985
6986 #ifdef DUMMY_READ_FOR_TRACKING
6987 vIO32WriteFldAlign_All(DRAMC_REG_DUMMY_RD, 1, DUMMY_RD_DMY_RD_RX_TRACK);
6988 #endif
6989
6990 vIO32WriteFldAlign_All(DRAMC_REG_DRSCTRL, 1, DRSCTRL_DRSDIS);
6991
6992 #ifdef IMPEDANCE_TRACKING_ENABLE
6993
6994 U8 u1DisImpHw;
6995 U32 u4TermFreq;
6996
6997 u4TermFreq = LP4_MRFSP_TERM_FREQ;
6998
6999 u1DisImpHw = (p->frequency >= u4TermFreq)? 0: 1;
7000 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_DRVING1, u1DisImpHw, SHU_MISC_DRVING1_DIS_IMPCAL_HW);
7001 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_DRVING1, u1DisImpHw, SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK);
7002 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_DRVING2, u1DisImpHw, SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN);
7003 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD12, u1DisImpHw, SHU_CA_CMD12_RG_RIMP_UNTERM_EN);
7004 #endif
7005
7006
7007 #if SUPPORT_SAVE_TIME_FOR_CALIBRATION && RX_DELAY_PRE_CAL
7008 s2RxDelayPreCal = PASS_RANGE_NA;
7009 #endif
7010 #endif
7011 }
7012
7013
7014
7015
7016 #if 0
7017 static void vDramcInit_PreSettings(DRAMC_CTX_T *p)
7018 {
7019 #if __A60868_TO_BE_PORTING__
7020
7021
7022 vIO32WriteFldMulti(DDRPHY_CA_CMD8, P_Fld(0x0, CA_CMD8_RG_TX_RRESETB_PULL_UP) | P_Fld(0x0, CA_CMD8_RG_TX_RRESETB_PULL_DN)
7023 | P_Fld(0x1, CA_CMD8_RG_TX_RRESETB_DDR3_SEL) | P_Fld(0x0, CA_CMD8_RG_TX_RRESETB_DDR4_SEL)
7024 | P_Fld(0xa, CA_CMD8_RG_RRESETB_DRVP) | P_Fld(0xa, CA_CMD8_RG_RRESETB_DRVN));
7025 vIO32WriteFldAlign(DDRPHY_MISC_CTRL1, 0x1, MISC_CTRL1_R_DMRRESETB_I_OPT);
7026
7027 vIO32WriteFldAlign(DDRPHY_MISC_CTRL1, 0x0, MISC_CTRL1_R_DMDA_RRESETB_I);
7028 vIO32WriteFldAlign(DDRPHY_MISC_CTRL1, 0x1, MISC_CTRL1_R_DMDA_RRESETB_E);
7029 #if __ETT__
7030 if (GetDramcBroadcast() == DRAMC_BROADCAST_OFF)
7031 {
7032 mcSHOW_ERR_MSG(("Err! Broadcast is OFF!\n"));
7033 }
7034 #endif
7035 return;
7036 #endif
7037 }
7038 #endif
DramcInit_DutyCalibration(DRAMC_CTX_T * p)7039 static void DramcInit_DutyCalibration(DRAMC_CTX_T *p)
7040 {
7041 #if ENABLE_DUTY_SCAN_V2
7042 U8 channel_idx, channel_backup = vGetPHY2ChannelMapping(p);
7043 U32 u4backup_broadcast= GetDramcBroadcast();
7044
7045 DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
7046
7047 #ifndef DUMP_INIT_RG_LOG_TO_DE
7048 if (Get_MDL_Used_Flag()==NORMAL_USED)
7049 {
7050 for (channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++)
7051 {
7052 vSetPHY2ChannelMapping(p, channel_idx);
7053 DramcNewDutyCalibration(p);
7054 }
7055 vSetPHY2ChannelMapping(p, channel_backup);
7056 }
7057 #endif
7058
7059 DramcBroadcastOnOff(u4backup_broadcast);
7060
7061 #endif
7062 }
7063
SV_BroadcastOn_DramcInit(DRAMC_CTX_T * p)7064 static void SV_BroadcastOn_DramcInit(DRAMC_CTX_T *p)
7065 {
7066 DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
7067
7068 if(!is_lp5_family(p))
7069 {
7070 if(p->frequency>=2133)
7071 {
7072 mcSHOW_DBG_MSG2(("sv_algorithm_assistance_LP4_4266 \n"));
7073 sv_algorithm_assistance_LP4_4266(p);
7074 }
7075 else if(p->frequency>=1333)
7076 {
7077 mcSHOW_DBG_MSG2(("sv_algorithm_assistance_LP4_3733 \n"));
7078 sv_algorithm_assistance_LP4_3733(p);
7079 }
7080 else if(p->frequency>400)
7081 {
7082 mcSHOW_DBG_MSG2(("sv_algorithm_assistance_LP4_1600 \n"));
7083 sv_algorithm_assistance_LP4_1600(p);
7084 }
7085 else if(p->frequency==400)
7086 {
7087 //mcSHOW_DBG_MSG(("CInit_golden_mini_freq_related_vseq_LP4_1600 \n"));
7088 //CInit_golden_mini_freq_related_vseq_LP4_1600(p);
7089 //CInit_golden_mini_freq_related_vseq_LP4_1600_SHU1(DramcConfig);
7090 mcSHOW_DBG_MSG2(("sv_algorithm_assistance_LP4_800 \n"));
7091 sv_algorithm_assistance_LP4_800(p);
7092 }
7093 else
7094 {
7095 mcSHOW_DBG_MSG(("sv_algorithm_assistance_LP4_400 \n"));
7096 sv_algorithm_assistance_LP4_400(p);
7097 }
7098 }
7099
7100 RESETB_PULL_DN(p);
7101 ANA_init(p);
7102 DIG_STATIC_SETTING(p);
7103 DIG_CONFIG_SHUF(p,0,0);
7104
7105 {
7106 LP4_UpdateInitialSettings(p);
7107 }
7108
7109 DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
7110 }
7111
GetRealFreq_at_Init(DRAMC_CTX_T * p)7112 static void GetRealFreq_at_Init(DRAMC_CTX_T *p){
7113 gddrphyfmeter_value[vGet_Current_SRAMIdx(p)] = DDRPhyFreqMeter(p);
7114 }
7115
DramcInit(DRAMC_CTX_T * p)7116 DRAM_STATUS_T DramcInit(DRAMC_CTX_T *p)
7117 {
7118
7119 #ifdef FOR_HQA_REPORT_USED
7120 if (gHQALog_flag==1)
7121 {
7122 mcSHOW_DBG_MSG(("[HQA] Log parsing, "));
7123 mcSHOW_DBG_MSG(("\tDram Data rate = ")); HQA_LOG_Print_Freq_String(p); mcSHOW_DBG_MSG(("\n"));
7124 }
7125 #endif
7126
7127 //CInit_ConfigFromTBA();
7128 mcSHOW_DBG_MSG(("MEM_TYPE=%d, freq_sel=%d\n", MEM_TYPE, p->freq_sel));
7129
7130 SV_BroadcastOn_DramcInit(p);
7131
7132 #if PRINT_CALIBRATION_SUMMARY
7133
7134 memset(p->aru4CalResultFlag, 0xffff, sizeof(p->aru4CalResultFlag));
7135 memset(p->aru4CalExecuteFlag, 0, sizeof(p->aru4CalExecuteFlag));
7136 #if PRINT_CALIBRATION_SUMMARY_FASTK_CHECK
7137 memset(p->FastKResultFlag, 0xffff, sizeof(p->FastKResultFlag));
7138 memset(p->FastKExecuteFlag, 0, sizeof(p->FastKExecuteFlag));
7139 #endif
7140 #endif
7141
7142 EnableDramcPhyDCM(p, DCM_OFF);
7143 vResetDelayChainBeforeCalibration(p);
7144
7145 DVFSSettings(p);
7146
7147 #if REPLACE_DFS_RG_MODE
7148 DPMInit(p);
7149 #if ENABLE_DFS_RUNTIME_MRW
7150 DFSRuntimeFspMRW(p);
7151 #endif
7152 mcSHOW_DBG_MSG2(("DPMInit(p);done\n"));
7153 #endif
7154
7155 GetRealFreq_at_Init(p);
7156
7157 vSetRank(p, RANK_0);
7158
7159
7160 #ifdef DDR_INIT_TIME_PROFILING
7161 U32 CPU_Cycle;
7162 TimeProfileBegin();
7163 #endif
7164 Dramc8PhaseCal(p);
7165 #ifdef DDR_INIT_TIME_PROFILING
7166 CPU_Cycle=TimeProfileEnd();
7167 mcSHOW_TIME_MSG(("\t8PHaseCal takes %d us\n", CPU_Cycle));
7168 TimeProfileBegin();
7169 #endif
7170 DramcInit_DutyCalibration(p);
7171 #ifdef DDR_INIT_TIME_PROFILING
7172 CPU_Cycle=TimeProfileEnd();
7173 mcSHOW_TIME_MSG(("\tDutyCalibration takes %d us\n", CPU_Cycle));
7174 #endif
7175
7176 {
7177 //LP4_DRAM_INIT(p);
7178 DramcModeRegInit_LP4(p);
7179 }
7180
7181 DdrUpdateACTiming(p);
7182
7183 memset(p->isWLevInitShift, FALSE, sizeof(p->isWLevInitShift));
7184
7185 #if BYPASS_CALIBRATION
7186 if(p->freq_sel==LP4_DDR4266 || p->freq_sel==LP4_DDR3200)
7187 {
7188 Apply_LP4_4266_Calibraton_Result(p);
7189 }
7190
7191 else if(p->freq_sel==LP4_DDR1600)
7192 {
7193 mcSHOW_DBG_MSG(("BYPASS CALIBRATION LP4 1600 \n"));
7194 Apply_LP4_1600_Calibraton_Result(p);
7195 }
7196 #endif
7197
7198 #if 0//__A60868_TO_BE_PORTING__
7199
7200 U32 save_ch, dram_t;
7201 #if (!__ETT__ && !FOR_DV_SIMULATION_USED && SW_CHANGE_FOR_SIMULATION == 0)
7202 EMI_SETTINGS *emi_set;
7203 #endif
7204 U8 dram_cbt_mode;
7205
7206 mcSHOW_DBG_MSG(("\n[DramcInit]\n"));
7207
7208 vSetPHY2ChannelMapping(p, CHANNEL_A);
7209
7210
7211 memset(p->aru4CalResultFlag, 0xffff, sizeof(p->aru4CalResultFlag));
7212 memset(p->aru4CalExecuteFlag, 0, sizeof(p->aru4CalExecuteFlag));
7213
7214 DramcSetting_Olympus_LP4_ByteMode(p);
7215
7216 DramcInit_DutyCalibration(p);
7217
7218 DramcModeRegInit_LP4(p);
7219
7220 //DdrUpdateACTiming(p);
7221
7222 #if 0
7223
7224 vIO32WriteFldAlign_All(DRAMC_REG_DRAMC_PD_CTRL, 0x62, DRAMC_PD_CTRL_REFCNT_FR_CLK);
7225
7226 u4RefreshRate = 38 * p->frequency / 640;
7227 vIO32WriteFldAlign_All(DRAMC_REG_CONF2, u4RefreshRate, CONF2_REFCNT);
7228 #endif
7229
7230 #if (fcFOR_CHIP_ID == fcLafite)
7231
7232 save_ch = vGetPHY2ChannelMapping(p);
7233 vSetPHY2ChannelMapping(p, CHANNEL_A);
7234
7235 switch (p->dram_type)
7236 {
7237 case TYPE_LPDDR4:
7238 dram_t = 2;
7239 break;
7240 case TYPE_LPDDR4X:
7241 dram_t = 3;
7242 break;
7243 case TYPE_LPDDR4P:
7244 dram_t = 4;
7245 break;
7246 default:
7247 dram_t = 0;
7248 mcSHOW_ERR_MSG(("Incorrect DRAM Type!\n"));
7249 break;
7250 }
7251 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_ARBCTL), dram_t, ARBCTL_RSV_DRAM_TYPE);
7252
7253
7254 if ((p->dram_cbt_mode[RANK_0] == CBT_NORMAL_MODE) && (p->dram_cbt_mode[RANK_1] == CBT_NORMAL_MODE))
7255 dram_cbt_mode = CBT_R0_R1_NORMAL;
7256 else if ((p->dram_cbt_mode[RANK_0] == CBT_BYTE_MODE1) && (p->dram_cbt_mode[RANK_1] == CBT_BYTE_MODE1))
7257 dram_cbt_mode = CBT_R0_R1_BYTE;
7258 else if ((p->dram_cbt_mode[RANK_0] == CBT_NORMAL_MODE) && (p->dram_cbt_mode[RANK_1] == CBT_BYTE_MODE1))
7259 dram_cbt_mode = CBT_R0_NORMAL_R1_BYTE;
7260 else if ((p->dram_cbt_mode[RANK_0] == CBT_BYTE_MODE1) && (p->dram_cbt_mode[RANK_1] == CBT_NORMAL_MODE))
7261 dram_cbt_mode = CBT_R0_BYTE_R1_NORMAL;
7262 else
7263 dram_cbt_mode = CBT_R0_R1_NORMAL;
7264
7265 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RSTMASK), dram_cbt_mode, RSTMASK_RSV_DRAM_CBT_MIXED);
7266
7267
7268 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_ARBCTL), (p->dram_cbt_mode[RANK_0] | p->dram_cbt_mode[RANK_1]), ARBCTL_RSV_DRAM_CBT);
7269
7270 vSetPHY2ChannelMapping(p, save_ch);
7271 #endif
7272
7273 mcSHOW_DBG_MSG3(("[DramcInit] Done\n"));
7274 #endif//__A60868_TO_BE_PORTING__
7275 return DRAM_OK;
7276 }
7277
7278 #if 0
7279 static void Switch26MHzDisableDummyReadRefreshAllBank(DRAMC_CTX_T *p)
7280 {
7281 #if __A60868_TO_BE_PORTING__
7282
7283 vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL0, 0, MISC_CG_CTRL0_CLK_MEM_SEL);
7284 vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL0, 1, MISC_CG_CTRL0_W_CHG_MEM);
7285 vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL0, 0, MISC_CG_CTRL0_W_CHG_MEM);
7286
7287 vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL0, 0, REFCTRL0_PBREFEN);
7288
7289 vIO32WriteFldMulti_All(DRAMC_REG_DUMMY_RD, P_Fld(0x0, DUMMY_RD_DQSG_DMYWR_EN)
7290 | P_Fld(0x0, DUMMY_RD_DQSG_DMYRD_EN) | P_Fld(0x0, DUMMY_RD_SREF_DMYRD_EN)
7291 | P_Fld(0x0, DUMMY_RD_DUMMY_RD_EN) | P_Fld(0x0, DUMMY_RD_DMY_RD_DBG)
7292 | P_Fld(0x0, DUMMY_RD_DMY_WR_DBG));
7293 #endif
7294 return;
7295 }
7296 #endif
7297
7298
7299 #if ENABLE_TMRRI_NEW_MODE
SetCKE2RankIndependent(DRAMC_CTX_T * p)7300 void SetCKE2RankIndependent(DRAMC_CTX_T *p)
7301 {
7302 #if ENABLE_TMRRI_NEW_MODE
7303 mcSHOW_DBG_MSG2(("SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON\n"));
7304 vCKERankCtrl(p, CKE_RANK_INDEPENDENT);
7305 #else
7306 mcSHOW_DBG_MSG2(("SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: OFF\n"));
7307 vCKERankCtrl(p, CKE_RANK_DEPENDENT);
7308 #endif
7309 }
7310 #endif
7311
7312
7313 #if ENABLE_WRITE_DBI
EnableDRAMModeRegWriteDBIAfterCalibration(DRAMC_CTX_T * p)7314 void EnableDRAMModeRegWriteDBIAfterCalibration(DRAMC_CTX_T *p)
7315 {
7316 U8 channel_idx, rank_idx;
7317 U8 ch_backup, rank_backup, u1FSPIdx = 0;
7318 //S8 u1ShuffleIdx;
7319
7320 ch_backup = p->channel;
7321 rank_backup = p->rank;
7322
7323 for (channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++)
7324 {
7325 vSetPHY2ChannelMapping(p, channel_idx);
7326 for (rank_idx = RANK_0; rank_idx < p->support_rank_num; rank_idx++)
7327 {
7328 vSetRank(p, rank_idx);
7329 for (u1FSPIdx = FSP_0; u1FSPIdx < p->support_fsp_num; u1FSPIdx++)
7330 {
7331 DramcMRWriteFldAlign(p, 13, u1FSPIdx, MR13_FSP_WR, TO_MR);
7332 SetDramModeRegForWriteDBIOnOff(p, u1FSPIdx, p->DBI_W_onoff[u1FSPIdx]);
7333 }
7334 }
7335 }
7336
7337 vSetRank(p, rank_backup);
7338 vSetPHY2ChannelMapping(p, ch_backup);
7339 }
7340 #endif
7341
7342 #if ENABLE_READ_DBI
EnableDRAMModeRegReadDBIAfterCalibration(DRAMC_CTX_T * p)7343 void EnableDRAMModeRegReadDBIAfterCalibration(DRAMC_CTX_T *p)
7344 {
7345 U8 channel_idx, rank_idx;
7346 U8 ch_backup, rank_backup, u1FSPIdx = 0;
7347 S8 u1ShuffleIdx;
7348
7349 ch_backup = p->channel;
7350 rank_backup = p->rank;
7351
7352 for (channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++)
7353 {
7354 vSetPHY2ChannelMapping(p, channel_idx);
7355 for (rank_idx = RANK_0; rank_idx < p->support_rank_num; rank_idx++)
7356 {
7357 vSetRank(p, rank_idx);
7358 for (u1FSPIdx = FSP_0; u1FSPIdx < p->support_fsp_num; u1FSPIdx++)
7359 {
7360 DramcMRWriteFldAlign(p, 13, u1FSPIdx, MR13_FSP_WR, TO_MR);
7361 SetDramModeRegForReadDBIOnOff(p, u1FSPIdx, p->DBI_R_onoff[u1FSPIdx]);
7362 }
7363 }
7364 }
7365
7366
7367 vIO32WriteFldMulti_All(DRAMC_REG_HW_MRR_FUN, P_Fld(0x1, HW_MRR_FUN_TR2MRR_ENA)
7368 | P_Fld(0x1, HW_MRR_FUN_R2MRRHPRICTL)
7369 | P_Fld(0x1, HW_MRR_FUN_MANTMRR_EN));
7370
7371 vSetRank(p, rank_backup);
7372 vSetPHY2ChannelMapping(p, ch_backup);
7373 }
7374 #endif
7375
7376
SetMr13VrcgToNormalOperationShuffle(DRAMC_CTX_T * p)7377 static void SetMr13VrcgToNormalOperationShuffle(DRAMC_CTX_T *p)
7378 {
7379 U32 u4Value = 0;
7380
7381 u4Value = u4IO32ReadFldAlign(DRAMC_REG_SHU_HWSET_VRCG, SHU_HWSET_VRCG_HWSET_VRCG_OP);
7382 vIO32WriteFldAlign_All(DRAMC_REG_SHU_HWSET_VRCG, u4Value & ~(0x1 << 3), SHU_HWSET_VRCG_HWSET_VRCG_OP);
7383 return;
7384 }
7385
7386 #if ENABLE_LP4Y_DFS
ENABLE_ClkSingleEndRG(DRAMC_CTX_T * p,U8 u1OnOff)7387 void ENABLE_ClkSingleEndRG (DRAMC_CTX_T *p, U8 u1OnOff)
7388 {
7389 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD13, P_Fld( u1OnOff, SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA) \
7390 | P_Fld( u1OnOff, SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA));
7391 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD7, u1OnOff, SHU_CA_CMD7_R_LP4Y_SDN_MODE_CLK);
7392 }
7393
ENABLE_WDQSSingleEndRG(DRAMC_CTX_T * p,U8 u1OnOff)7394 void ENABLE_WDQSSingleEndRG (DRAMC_CTX_T *p, U8 u1OnOff)
7395 {
7396 BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
7397 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ13, P_Fld( !u1OnOff, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0) \
7398 | P_Fld(!u1OnOff, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B0) \
7399 | P_Fld( u1OnOff, SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B0) \
7400 | P_Fld( u1OnOff, SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B0));
7401 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ7, u1OnOff , SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0);
7402
7403 if (isLP4_DSC)
7404 {
7405 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD13, P_Fld(!u1OnOff, SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_EN_CA) \
7406 | P_Fld(!u1OnOff, SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA) \
7407 | P_Fld( u1OnOff, SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA) \
7408 | P_Fld( u1OnOff, SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA));
7409 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD7, u1OnOff , SHU_CA_CMD7_R_LP4Y_SDN_MODE_CLK);
7410 }
7411 else
7412 {
7413 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ13, P_Fld(!u1OnOff, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1) \
7414 | P_Fld(!u1OnOff, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B1) \
7415 | P_Fld( u1OnOff, SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B1) \
7416 | P_Fld( u1OnOff, SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B1));
7417 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ7, u1OnOff , SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1);
7418 }
7419 }
7420
ENABLE_RDQSSingleEndRG(DRAMC_CTX_T * p,U8 u1OnOff)7421 void ENABLE_RDQSSingleEndRG (DRAMC_CTX_T *p, U8 u1OnOff)
7422 {
7423 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ10, u1OnOff, SHU_B0_DQ10_RG_RX_ARDQS_SE_EN_B0);
7424 if (p->DRAMPinmux == PINMUX_DSC)
7425 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD10, u1OnOff, SHU_CA_CMD10_RG_RX_ARCLK_SE_EN_CA);
7426 else
7427 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ10, u1OnOff, SHU_B1_DQ10_RG_RX_ARDQS_SE_EN_B1);
7428 }
7429
ENABLE_SingleEndRGEnable(DRAMC_CTX_T * p,U16 u2Freq)7430 void ENABLE_SingleEndRGEnable (DRAMC_CTX_T *p, U16 u2Freq)
7431 {
7432 if (u2Freq <= 800)
7433 {
7434 ENABLE_ClkSingleEndRG (p, ENABLE);
7435 ENABLE_WDQSSingleEndRG (p, ENABLE);
7436 ENABLE_RDQSSingleEndRG (p, ENABLE);
7437 }
7438 }
7439 #endif
7440
SetMr13VrcgToNormalOperation(DRAMC_CTX_T * p)7441 void SetMr13VrcgToNormalOperation(DRAMC_CTX_T *p)
7442 {
7443 DRAM_CHANNEL_T eOriChannel = vGetPHY2ChannelMapping(p);
7444 DRAM_RANK_T eOriRank = u1GetRank(p);
7445 U8 u1ChIdx = CHANNEL_A;
7446 U8 u1RankIdx = 0;
7447
7448 #if MRW_CHECK_ONLY
7449 mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__));
7450 #endif
7451
7452 for (u1ChIdx = CHANNEL_A; u1ChIdx < p->support_channel_num; u1ChIdx++)
7453 {
7454 vSetPHY2ChannelMapping(p, u1ChIdx);
7455
7456 for (u1RankIdx = 0; u1RankIdx < p->support_rank_num; u1RankIdx++)
7457 {
7458 vSetRank(p, u1RankIdx);
7459 DramcModeRegWriteByRank(p, u1RankIdx, 13, u1MR13Value[u1RankIdx]);
7460 DramcMRWriteFldAlign(p, 13, 0, MR13_VRCG, JUST_TO_GLOBAL_VALUE);
7461 }
7462 }
7463 vSetPHY2ChannelMapping(p, (U8)eOriChannel);
7464 vSetRank(p, (U8)eOriRank);
7465 return;
7466 }
7467
7468
DramcShuTrackingDcmSeEnBySRAM(DRAMC_CTX_T * p)7469 static void DramcShuTrackingDcmSeEnBySRAM(DRAMC_CTX_T *p)
7470 {
7471 #if (fcFOR_CHIP_ID == fcA60868)
7472 U8 u1ShuffleIdx, ShuRGAccessIdxBak;
7473
7474 ShuRGAccessIdxBak = p->ShuRGAccessIdx;
7475 mcSHOW_DBG_MSG2(("\n==[DramcShuTrackingDcmEnBySRAM]==\n"));
7476 for (u1ShuffleIdx = 0; u1ShuffleIdx <= 1; u1ShuffleIdx++)
7477 {
7478
7479 p->ShuRGAccessIdx = u1ShuffleIdx;
7480 #ifdef HW_GATING
7481 //DramcHWGatingOnOff(p, 1, u4DramcShuOffset);
7482 #endif
7483
7484 #if ENABLE_TX_TRACKING
7485 Enable_TX_Tracking(p);
7486 #endif
7487
7488 #if RDSEL_TRACKING_EN
7489 Enable_RDSEL_Tracking(p, u2Freq);
7490 #endif
7491
7492 #ifdef HW_GATING
7493 Enable_Gating_Tracking(p);
7494 #endif
7495 }
7496 p->ShuRGAccessIdx = ShuRGAccessIdxBak;
7497 #else
7498 DRAM_DFS_FREQUENCY_TABLE_T *pFreqTable = p->pDFSTable;
7499 U8 u1ShuffleIdx;
7500 U16 u2Freq = 0;
7501
7502 U32 u4RegBackupAddress[] =
7503 {
7504 (DDRPHY_REG_MISC_SRAM_DMA0),
7505 (DDRPHY_REG_MISC_SRAM_DMA0 + SHIFT_TO_CHB_ADDR),
7506 (DDRPHY_REG_MISC_SRAM_DMA1),
7507 (DDRPHY_REG_MISC_SRAM_DMA1 + SHIFT_TO_CHB_ADDR),
7508 #if (CHANNEL_NUM==4)
7509 (DDRPHY_REG_MISC_SRAM_DMA0 + SHIFT_TO_CHC_ADDR),
7510 (DDRPHY_REG_MISC_SRAM_DMA0 + SHIFT_TO_CHD_ADDR),
7511 (DDRPHY_REG_MISC_SRAM_DMA1 + SHIFT_TO_CHC_ADDR),
7512 (DDRPHY_REG_MISC_SRAM_DMA1 + SHIFT_TO_CHD_ADDR),
7513 #endif
7514 };
7515
7516
7517 DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32));
7518
7519 #if (ENABLE_TX_TRACKING && TX_RETRY_ENABLE)
7520 Enable_and_Trigger_TX_Retry(p);
7521 #endif
7522
7523
7524 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x0, MISC_SRAM_DMA0_APB_SLV_SEL);
7525 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, 0x1, MISC_SRAM_DMA1_R_APB_DMA_DBG_ACCESS);
7526
7527 for (u1ShuffleIdx = 0; u1ShuffleIdx <= DRAM_DFS_SRAM_MAX; u1ShuffleIdx++)
7528 {
7529 if (u1ShuffleIdx == DRAM_DFS_SRAM_MAX)
7530 {
7531
7532 vSetDFSTable(p, pFreqTable);
7533 u2Freq = GetFreqBySel(p, p->pDFSTable->freq_sel);
7534
7535 DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32));
7536 p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;
7537 }
7538 else
7539 {
7540
7541 vSetDFSTable(p, get_FreqTbl_by_SRAMIndex(p, u1ShuffleIdx));
7542 u2Freq = GetFreqBySel(p, p->pDFSTable->freq_sel);
7543 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x0, MISC_SRAM_DMA0_APB_SLV_SEL);
7544 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, u1ShuffleIdx, MISC_SRAM_DMA1_R_APB_DMA_DBG_LEVEL);
7545
7546 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x1, MISC_SRAM_DMA0_APB_SLV_SEL);
7547 p->ShuRGAccessIdx = DRAM_DFS_REG_SHU1;
7548 }
7549
7550 #if ENABLE_TX_TRACKING
7551 Enable_TX_Tracking(p);
7552 #endif
7553 #if RDSEL_TRACKING_EN
7554 Enable_RDSEL_Tracking(p, u2Freq);
7555 #endif
7556 #ifdef HW_GATING
7557 Enable_Gating_Tracking(p);
7558 #endif
7559
7560 #if ENABLE_PER_BANK_REFRESH && (!IMP_TRACKING_PB_TO_AB_REFRESH_WA)
7561 Enable_PerBank_Refresh(p);
7562 #endif
7563
7564 EnableRxDcmDPhy(p, u2Freq);
7565 EnableCmdPicgEffImprove(p);
7566 Enable_ClkTxRxLatchEn(p);
7567 #if ENABLE_TX_WDQS
7568 Enable_TxWDQS(p);
7569 #endif
7570
7571 #if ENABLE_LP4Y_DFS && (LP4Y_BACKUP_SOLUTION == 0)
7572 ENABLE_SingleEndRGEnable (p, u2Freq);
7573 #endif
7574
7575 #if (SW_CHANGE_FOR_SIMULATION == 0)
7576 #if APPLY_LOWPOWER_GOLDEN_SETTINGS
7577 int enable_dcm = (doe_get_config("dramc_dcm")) ? 0 : 1;
7578 EnableDramcPhyDCMShuffle(p, enable_dcm);
7579 #else
7580 EnableDramcPhyDCMShuffle(p, 0);
7581 #endif
7582 #endif
7583 SetMr13VrcgToNormalOperationShuffle(p);
7584
7585 p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;
7586 }
7587 #endif
7588 }
7589
7590 #if ENABLE_PER_BANK_REFRESH
DramcSetPerBankRefreshMode(DRAMC_CTX_T * p)7591 void DramcSetPerBankRefreshMode(DRAMC_CTX_T *p)
7592 {
7593 vIO32WriteFldMulti_All(DRAMC_REG_REFCTRL0, P_Fld(1, REFCTRL0_PBREF_BK_REFA_ENA) | P_Fld(2, REFCTRL0_PBREF_BK_REFA_NUM));
7594
7595 #if PER_BANK_REFRESH_USE_MODE==0
7596 vIO32WriteFldMulti_All(DRAMC_REG_REFCTRL0, P_Fld(0, REFCTRL0_KEEP_PBREF) | P_Fld(0, REFCTRL0_KEEP_PBREF_OPT));
7597 mcSHOW_DBG_MSG(("\tPER_BANK_REFRESH: Original Mode\n"));
7598 #endif
7599
7600 #if PER_BANK_REFRESH_USE_MODE==1
7601 vIO32WriteFldMulti_All(DRAMC_REG_REFCTRL0, P_Fld(0, REFCTRL0_KEEP_PBREF) | P_Fld(1, REFCTRL0_KEEP_PBREF_OPT));
7602 mcSHOW_DBG_MSG(("\tPER_BANK_REFRESH: Hybrid Mode\n"));
7603 #endif
7604
7605 #if PER_BANK_REFRESH_USE_MODE==2
7606 vIO32WriteFldMulti_All(DRAMC_REG_REFCTRL0, P_Fld(1, REFCTRL0_KEEP_PBREF) | P_Fld(0, REFCTRL0_KEEP_PBREF_OPT));
7607 mcSHOW_DBG_MSG(("\tPER_BANK_REFRESH: Always Per-Bank Mode\n"));
7608 #endif
7609
7610 vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL1, 1, REFCTRL1_REFPB2AB_IGZQCS);
7611
7612 }
7613 #endif
7614
7615 #ifdef TEMP_SENSOR_ENABLE
DramcHMR4_Presetting(DRAMC_CTX_T * p)7616 void DramcHMR4_Presetting(DRAMC_CTX_T *p)
7617 {
7618 U8 backup_channel = p->channel;
7619 U8 channelIdx;
7620
7621 for (channelIdx = CHANNEL_A; channelIdx < p->support_channel_num; channelIdx++)
7622 {
7623 vSetPHY2ChannelMapping(p, channelIdx);
7624 // vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL1), Refr_rate_manual_trigger, REFCTRL1_REFRATE_MANUAL_RATE_TRIG);
7625 // vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL1), Refr_rate_manual, REFCTRL1_REFRATE_MANUAL);
7626
7627 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HMR4), 1, HMR4_REFR_PERIOD_OPT);
7628 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HMR4), 0, HMR4_REFRCNT_OPT);
7629 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HMR4_DVFS_CTRL0), 0x80, SHU_HMR4_DVFS_CTRL0_REFRCNT);
7630
7631
7632 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
7633 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HMR4), 1, HMR4_HMR4_BYTEMODE_EN);
7634 else
7635 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HMR4), 0, HMR4_HMR4_BYTEMODE_EN);
7636
7637
7638 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL1), 0, REFCTRL1_REFRATE_MON_CLR);
7639 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL1), 1, REFCTRL1_REFRATE_MON_CLR);
7640 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL1), 0, REFCTRL1_REFRATE_MON_CLR);
7641 }
7642 vSetPHY2ChannelMapping(p, backup_channel);
7643
7644 }
7645 #endif
7646
SwitchHMR4(DRAMC_CTX_T * p,bool en)7647 static void SwitchHMR4(DRAMC_CTX_T *p, bool en)
7648 {
7649
7650 {
7651 vIO32WriteFldAlign_All(DRAMC_REG_REF_BOUNCE2, 5, REF_BOUNCE2_PRE_MR4INT_TH);
7652
7653 vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL2, 5, REFCTRL2_MR4INT_TH);
7654 }
7655
7656
7657 if (en && p->support_rank_num == RANK_DUAL)
7658 vIO32WriteFldAlign_All(DRAMC_REG_HMR4, 1, HMR4_HMR4_TOG_OPT);
7659 else
7660 vIO32WriteFldAlign_All(DRAMC_REG_HMR4, 0, HMR4_HMR4_TOG_OPT);
7661
7662 vIO32WriteFldAlign_All(DRAMC_REG_HMR4, !en, HMR4_REFRDIS);
7663
7664 #if 0
7665 while(1)
7666 {
7667 mcSHOW_DBG_MSG(("@@ --------------------\n"));
7668 mcSHOW_DBG_MSG(("@@ MISC_STATUSA_REFRESH_RATE: %d\n",
7669 u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MISC_STATUSA), MISC_STATUSA_REFRESH_RATE)));
7670 mcSHOW_DBG_MSG(("@@ MIN: %d, MAX: %d\n",
7671 u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON), HW_REFRATE_MON_REFRESH_RATE_MIN_MON),
7672 u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON), HW_REFRATE_MON_REFRESH_RATE_MAX_MON)));
7673
7674
7675 {
7676 mcSHOW_DBG_MSG(("@@ MIN MAX\n"));
7677 mcSHOW_DBG_MSG(("@@ RK0_B0: %d %d\n",
7678 u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON3), HW_REFRATE_MON3_REFRESH_RATE_MIN_MON_RK0_B0),
7679 u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON3), HW_REFRATE_MON3_REFRESH_RATE_MAX_MON_RK0_B0)));
7680 mcSHOW_DBG_MSG(("@@ RK1_B0: %d %d\n",
7681 u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON3), HW_REFRATE_MON3_REFRESH_RATE_MIN_MON_RK1_B0),
7682 u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON3), HW_REFRATE_MON3_REFRESH_RATE_MAX_MON_RK1_B0)));
7683 mcSHOW_DBG_MSG(("@@ RK0_B1: %d %d\n",
7684 u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON2), HW_REFRATE_MON2_REFRESH_RATE_MIN_MON_RK0_B1),
7685 u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON2), HW_REFRATE_MON2_REFRESH_RATE_MAX_MON_RK0_B1)));
7686 mcSHOW_DBG_MSG(("@@ RK1_B1: %d %d\n",
7687 u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON2), HW_REFRATE_MON2_REFRESH_RATE_MIN_MON_RK1_B1),
7688 u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON2), HW_REFRATE_MON2_REFRESH_RATE_MAX_MON_RK1_B1)));
7689 }
7690
7691 mcSHOW_DBG_MSG(("@@ Wait to measure!!\n\n"));
7692 Sleep(500);
7693 }
7694 #endif
7695 }
7696
7697 #if ENABLE_REFRESH_RATE_DEBOUNCE
DramcRefreshRateDeBounceEnable(DRAMC_CTX_T * p)7698 static void DramcRefreshRateDeBounceEnable(DRAMC_CTX_T *p)
7699 {
7700 vIO32WriteFldMulti_All(DRAMC_REG_REF_BOUNCE1, P_Fld(0x4 , REF_BOUNCE1_REFRATE_DEBOUNCE_COUNT) |
7701 P_Fld(5 , REF_BOUNCE1_REFRATE_DEBOUNCE_TH) |
7702 P_Fld(0 , REF_BOUNCE1_REFRATE_DEBOUNCE_OPT) |
7703 P_Fld(0xff1f , REF_BOUNCE1_REFRATE_DEBOUNCE_DIS) );
7704 }
7705 #endif
7706
7707 #if DRAMC_MODIFIED_REFRESH_MODE
DramcModifiedRefreshMode(DRAMC_CTX_T * p)7708 void DramcModifiedRefreshMode(DRAMC_CTX_T *p)
7709 {
7710 vIO32WriteFldMulti_All(DRAMC_REG_REFPEND1, P_Fld(2, REFPEND1_MPENDREFCNT_TH0)
7711 | P_Fld(2, REFPEND1_MPENDREFCNT_TH1)
7712 | P_Fld(4, REFPEND1_MPENDREFCNT_TH2)
7713 | P_Fld(5, REFPEND1_MPENDREFCNT_TH3)
7714 | P_Fld(5, REFPEND1_MPENDREFCNT_TH4)
7715 | P_Fld(3, REFPEND1_MPENDREFCNT_TH5)
7716 | P_Fld(3, REFPEND1_MPENDREFCNT_TH6)
7717 | P_Fld(3, REFPEND1_MPENDREFCNT_TH7));
7718 vIO32WriteFldMulti_All(DRAMC_REG_REFCTRL1, P_Fld(1, REFCTRL1_REFPEND_OPT1) | P_Fld(1, REFCTRL1_REFPEND_OPT2));
7719 vIO32WriteFldAlign_All(DRAMC_REG_SHU_REF0, 4, SHU_REF0_MPENDREF_CNT);
7720 }
7721 #endif
7722
7723 #if DRAMC_CKE_DEBOUNCE
DramcCKEDebounce(DRAMC_CTX_T * p)7724 void DramcCKEDebounce(DRAMC_CTX_T *p)
7725 {
7726 U8 u1CKE_DBECnt = 15;
7727 U8 rank_backup, u1RKIdx=0;
7728 if(p->frequency>=1866)
7729 {
7730 rank_backup = p->rank;
7731 for(u1RKIdx=0; u1RKIdx<p->support_rank_num; u1RKIdx++)
7732 {
7733 vSetRank(p, u1RKIdx);
7734 vIO32WriteFldAlign_All(DRAMC_REG_SHURK_CKE_CTRL, u1CKE_DBECnt, SHURK_CKE_CTRL_CKE_DBE_CNT);
7735 mcSHOW_DBG_MSG2(("CKE Debounce cnt = %d\n", u1CKE_DBECnt));
7736 }
7737 vSetRank(p, rank_backup);
7738 }
7739 }
7740 #endif
7741
7742 #if OPEN_LOOP_MODE_CLK_TOGGLE_WA
ToggleOpenLoopModeClk(DRAMC_CTX_T * p)7743 static void ToggleOpenLoopModeClk(DRAMC_CTX_T *p)
7744 {
7745 U8 u1ChannelMode = (p->support_channel_num == CHANNEL_DUAL)?3:1;
7746
7747 #if defined(DPM_CONTROL_AFTERK) && ((DRAMC_DFS_MODE%2) != 0)
7748 mcSHOW_DBG_MSG(("[WARNING] DDR400 out (DPM RG/PST MODE) Toggle CLK WA\n"));
7749 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1ChannelMode, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN);
7750 mcDELAY_US(1);
7751 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, u1ChannelMode, LPIF_LOW_POWER_CFG_1_DPY_BCLK_ENABLE);
7752 mcDELAY_US(1);
7753 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, u1ChannelMode, LPIF_LOW_POWER_CFG_1_SHU_RESTORE);
7754 mcDELAY_US(1);
7755 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 0, LPIF_LOW_POWER_CFG_1_SHU_RESTORE);
7756 mcDELAY_US(1);
7757 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 0, LPIF_LOW_POWER_CFG_1_DPY_BCLK_ENABLE);
7758 mcDELAY_US(1);
7759 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN);
7760 mcDELAY_US(1);
7761 #else
7762 mcSHOW_DBG_MSG(("[WARNING] DDR400 out (PHY RG MODE) Toggle CLK WA\n"));
7763
7764
7765 vIO32WriteFldMulti(SPM_POWERON_CONFIG_EN, P_Fld(0xB16, POWERON_CONFIG_EN_PROJECT_CODE) | P_Fld(1, POWERON_CONFIG_EN_BCLK_CG_EN));
7766
7767 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN);
7768 mcDELAY_US(1);
7769 vIO32WriteFldAlign(DRAMC_DPY_CLK_SW_CON_0, u1ChannelMode, DRAMC_DPY_CLK_SW_CON_0_SW_DPY_BCLK_ENABLE);
7770 mcDELAY_US(1);
7771 vIO32WriteFldAlign(DRAMC_DPY_CLK_SW_CON_1, u1ChannelMode, DRAMC_DPY_CLK_SW_CON_1_SW_SHU_RESTORE);
7772 mcDELAY_US(1);
7773 vIO32WriteFldAlign(DRAMC_DPY_CLK_SW_CON_1, 0, DRAMC_DPY_CLK_SW_CON_1_SW_SHU_RESTORE);
7774 mcDELAY_US(1);
7775 vIO32WriteFldAlign(DRAMC_DPY_CLK_SW_CON_0, 0, DRAMC_DPY_CLK_SW_CON_0_SW_DPY_BCLK_ENABLE);
7776 mcDELAY_US(1);
7777 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN);
7778 mcDELAY_US(1);
7779
7780
7781 //DramcDFSDirectJump_SRAMShuRGMode(p, SRAM_SHU7);
7782 //DramcDFSDirectJump_SRAMShuRGMode(p, SRAM_SHU7);
7783 #endif
7784 }
7785 #endif
7786
7787
7788 #if 0
7789 static void S0_DCMOffWA(DRAMC_CTX_T *p)
7790 {
7791 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL0,
7792 P_Fld(0x0, MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE) |
7793 P_Fld(0x0, MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE) |
7794 P_Fld(0x0, MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE) |
7795 P_Fld(0x0, MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE) |
7796 P_Fld(0x0, MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE) |
7797 P_Fld(0x0, MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE) |
7798 P_Fld(0x0, MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE) |
7799 P_Fld(0x0, MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE) |
7800 P_Fld(0x0, MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE));
7801 }
7802 #endif
DramcRunTimeConfig(DRAMC_CTX_T * p)7803 void DramcRunTimeConfig(DRAMC_CTX_T *p)
7804 {
7805 #if (fcFOR_CHIP_ID == fcA60868)
7806 u1EnterRuntime = 1;
7807 #endif
7808
7809 mcSHOW_DBG_MSG(("[DramcRunTimeConfig]\n"));
7810
7811 SetDramInfoToConf(p);
7812
7813 #if defined(DPM_CONTROL_AFTERK) && ((DRAMC_DFS_MODE%2) != 0) && (REPLACE_DFS_RG_MODE==0)
7814 DPMInit(p);
7815 mcSHOW_DBG_MSG(("DPM_CONTROL_AFTERK: ON\n"));
7816 #endif
7817
7818 #if ENABLE_PER_BANK_REFRESH
7819 #if IMP_TRACKING_PB_TO_AB_REFRESH_WA
7820
7821 vIO32WriteFldAlign_All(DRAMC_REG_SHU_CONF0, 0x1, SHU_CONF0_PBREFEN);
7822 #endif
7823 mcSHOW_DBG_MSG(("PER_BANK_REFRESH: ON\n"));
7824 #else
7825 mcSHOW_DBG_MSG(("PER_BANK_REFRESH: OFF\n"));
7826 #endif
7827
7828
7829 #if __A60868_TO_BE_PORTING__
7830
7831 #if ENABLE_DDR800_OPEN_LOOP_MODE_OPTION
7832 if (vGet_DDR800_Mode(p) == DDR800_SEMI_LOOP)
7833 {
7834 EnableDllCg(p, ENABLE);
7835 }
7836 #endif
7837
7838 #endif //__A60868_TO_BE_PORTING__
7839
7840 #if REFRESH_OVERHEAD_REDUCTION
7841 vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL1, 0x1, REFCTRL1_REF_OVERHEAD_SLOW_REFPB_ENA);
7842 mcSHOW_DBG_MSG(("REFRESH_OVERHEAD_REDUCTION: ON\n"));
7843 #else
7844 mcSHOW_DBG_MSG(("REFRESH_OVERHEAD_REDUCTION: OFF\n"));
7845 #endif
7846
7847 #if XRTWTW_NEW_CROSS_RK_MODE
7848 if (p->support_rank_num == RANK_DUAL)
7849 {
7850 //ENABLE_XRTWTW_Setting(p);
7851 mcSHOW_DBG_MSG(("XRTWTW_NEW_MODE: ON\n"));
7852 }
7853 #else
7854 mcSHOW_DBG_MSG(("XRTWTW_NEW_MODE: OFF\n"));
7855 #endif
7856
7857 #if XRTRTR_NEW_CROSS_RK_MODE
7858 if (p->support_rank_num == RANK_DUAL)
7859 {
7860 //ENABLE_XRTRTR_Setting(p);
7861 mcSHOW_DBG_MSG(("XRTRTR_NEW_MODE: ON\n"));
7862 }
7863 #else
7864 mcSHOW_DBG_MSG(("XRTRTR_NEW_MODE: OFF\n"));
7865 #endif
7866
7867 #if ENABLE_TX_TRACKING
7868 mcSHOW_DBG_MSG(("TX_TRACKING: ON\n"));
7869 #else
7870 mcSHOW_DBG_MSG(("TX_TRACKING: OFF\n"));
7871 #endif
7872
7873 #if RDSEL_TRACKING_EN
7874 mcSHOW_DBG_MSG(("RDSEL_TRACKING: ON\n"));
7875 #else
7876 mcSHOW_DBG_MSG(("RDSEL_TRACKING: OFF\n"));
7877 #endif
7878
7879 #if TDQSCK_PRECALCULATION_FOR_DVFS
7880 mcSHOW_DBG_MSG(("DQS Precalculation for DVFS: "));
7881
7882 DramcDQSPrecalculation_enable(p);
7883 mcSHOW_DBG_MSG(("ON\n"));
7884 #else
7885 mcSHOW_DBG_MSG(("DQS Precalculation for DVFS: OFF\n"));
7886 #endif
7887
7888 #if ENABLE_RX_TRACKING
7889 DramcRxInputDelayTrackingInit_Common(p);
7890 DramcRxInputDelayTrackingHW(p);
7891 mcSHOW_DBG_MSG(("RX_TRACKING: ON\n"));
7892 #else
7893 mcSHOW_DBG_MSG(("RX_TRACKING: OFF\n"));
7894 #endif
7895
7896 #if (ENABLE_RX_TRACKING && RX_DLY_TRACK_ONLY_FOR_DEBUG && defined(DUMMY_READ_FOR_TRACKING))
7897 mcSHOW_DBG_MSG(("RX_DLY_TRACK_DBG: ON\n"));
7898 DramcRxDlyTrackDebug(p);
7899 #endif
7900
7901
7902 #if (defined(HW_GATING))
7903 mcSHOW_DBG_MSG(("HW_GATING DBG: ON\n"));
7904 DramcHWGatingDebugOnOff(p, ENABLE);
7905 #else
7906 mcSHOW_DBG_MSG(("HW_GATING DBG: OFF\n"));
7907 DramcHWGatingDebugOnOff(p, DISABLE);
7908 #endif
7909
7910 #ifdef ZQCS_ENABLE_LP4
7911
7912 #if (fcFOR_CHIP_ID == fcPetrus)
7913 vIO32WriteFldAlign(DRAMC_REG_ZQ_SET1 + (CHANNEL_A << POS_BANK_NUM), 1, ZQ_SET1_ZQCALDISB);
7914 vIO32WriteFldAlign(DRAMC_REG_ZQ_SET1 + (CHANNEL_D << POS_BANK_NUM), 1, ZQ_SET1_ZQCALDISB);
7915
7916 mcDELAY_US(1);
7917
7918 vIO32WriteFldAlign(DRAMC_REG_ZQ_SET1 + (CHANNEL_B << POS_BANK_NUM), 1, ZQ_SET1_ZQCALDISB);
7919 vIO32WriteFldAlign(DRAMC_REG_ZQ_SET1 + (CHANNEL_C << POS_BANK_NUM), 1, ZQ_SET1_ZQCALDISB);
7920 #elif (fcFOR_CHIP_ID == fc8195)
7921 vIO32WriteFldAlign(DRAMC_REG_ZQ_SET1 + (CHANNEL_A << POS_BANK_NUM), 1, ZQ_SET1_ZQCALDISB);
7922 vIO32WriteFldAlign(DRAMC_REG_ZQ_SET1 + (CHANNEL_C << POS_BANK_NUM), 1, ZQ_SET1_ZQCALDISB);
7923
7924 mcDELAY_US(1);
7925
7926 vIO32WriteFldAlign(DRAMC_REG_ZQ_SET1 + (CHANNEL_B << POS_BANK_NUM), 1, ZQ_SET1_ZQCALDISB);
7927 vIO32WriteFldAlign(DRAMC_REG_ZQ_SET1 + (CHANNEL_D << POS_BANK_NUM), 1, ZQ_SET1_ZQCALDISB);
7928 #endif
7929 mcSHOW_DBG_MSG(("ZQCS_ENABLE_LP4: ON\n"));
7930 #else
7931 vIO32WriteFldAlign_All(DRAMC_REG_ZQ_SET1, 0, ZQ_SET1_ZQCALDISB);
7932 mcSHOW_DBG_MSG(("ZQCS_ENABLE_LP4: OFF\n"));
7933 #if (!__ETT__) && ENABLE_LP4Y_DFS
7934 #error RTMRW DFS must support the SWZQ at DPM!!!
7935 #endif
7936 #endif
7937
7938
7939 #if 0
7940 #ifdef DUMMY_READ_FOR_DQS_GATING_RETRY
7941 DummyReadForDqsGatingRetryNonShuffle(p, 1);
7942 mcSHOW_DBG_MSG(("DUMMY_READ_FOR_DQS_GATING_RETRY: ON\n"));
7943 #else
7944 DummyReadForDqsGatingRetryNonShuffle(p, 0);
7945 mcSHOW_DBG_MSG(("DUMMY_READ_FOR_DQS_GATING_RETRY: OFF\n"));
7946 #endif
7947 #endif
7948
7949 #if RX_PICG_NEW_MODE
7950 mcSHOW_DBG_MSG(("RX_PICG_NEW_MODE: ON\n"));
7951 #else
7952 mcSHOW_DBG_MSG(("RX_PICG_NEW_MODE: OFF\n"));
7953 #endif
7954
7955 #if TX_PICG_NEW_MODE
7956 TXPICGNewModeEnable(p);
7957 mcSHOW_DBG_MSG(("TX_PICG_NEW_MODE: ON\n"));
7958 #else
7959 mcSHOW_DBG_MSG(("TX_PICG_NEW_MODE: OFF\n"));
7960 #endif
7961
7962 #if ENABLE_LP4Y_DFS
7963 mcSHOW_DBG_MSG(("ENABLE_LP4Y_DFS: ON\n"));
7964 #else
7965 mcSHOW_DBG_MSG(("ENABLE_LP4Y_DFS: OFF\n"));
7966 #endif
7967
7968 #if (SW_CHANGE_FOR_SIMULATION == 0)
7969 #if APPLY_LOWPOWER_GOLDEN_SETTINGS
7970 int enable_dcm = (doe_get_config("dramc_dcm"))? 0: 1;
7971 //const char *str = (enable_dcm == 1)? ("ON") : ("OFF");
7972 // EnableDramcPhyDCM(p, enable_dcm);
7973 EnableDramcPhyDCMNonShuffle(p, enable_dcm);
7974 //mcSHOW_DBG_MSG(("LOWPOWER_GOLDEN_SETTINGS(DCM): %s\n", str));
7975
7976 if(enable_dcm == 0)
7977 {
7978 //S0_DCMOffWA(p);
7979 }
7980
7981 #else
7982 // EnableDramcPhyDCM(p, DCM_OFF);
7983 EnableDramcPhyDCMNonShuffle(p, 0);
7984 mcSHOW_DBG_MSG(("LOWPOWER_GOLDEN_SETTINGS(DCM): OFF\n"));
7985
7986 //S0_DCMOffWA(p);
7987 #endif
7988 #endif
7989
7990 //DumpShuRG(p);
7991
7992
7993
7994 #if 1
7995 DramcShuTrackingDcmSeEnBySRAM(p);
7996 #endif
7997
7998
7999
8000 #ifdef DUMMY_READ_FOR_TRACKING
8001 DramcDummyReadForTrackingEnable(p);
8002 #else
8003 mcSHOW_DBG_MSG(("DUMMY_READ_FOR_TRACKING: OFF\n"));
8004 #endif
8005
8006
8007 #ifdef SPM_CONTROL_AFTERK
8008 DVFS_PRE_config(p);
8009 TransferToSPMControl(p);
8010 mcSHOW_DBG_MSG(("SPM_CONTROL_AFTERK: ON\n"));
8011 #else
8012 mcSHOW_DBG_MSG(("!!! SPM_CONTROL_AFTERK: OFF\n"));
8013 mcSHOW_DBG_MSG(("!!! SPM could not control APHY\n"));
8014 #endif
8015
8016
8017 #ifndef DDR_INIT_TIME_PROFILING
8018 #ifdef IMPEDANCE_TRACKING_ENABLE
8019 if (p->dram_type == TYPE_LPDDR4 || p->dram_type == TYPE_LPDDR4X)
8020 {
8021 DramcImpedanceTrackingEnable(p);
8022 mcSHOW_DBG_MSG(("IMPEDANCE_TRACKING: ON\n"));
8023
8024 #ifdef IMPEDANCE_HW_SAVING
8025 DramcImpedanceHWSaving(p);
8026 #endif
8027 }
8028 #else
8029 mcSHOW_DBG_MSG(("IMPEDANCE_TRACKING: OFF\n"));
8030 #endif
8031 #endif
8032
8033
8034 //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSCAL0), 0, DQSCAL0_STBCALEN);
8035
8036 #ifdef TEMP_SENSOR_ENABLE
8037 SwitchHMR4(p, ON);
8038 mcSHOW_DBG_MSG(("TEMP_SENSOR: ON\n"));
8039 #else
8040 SwitchHMR4(p, OFF);
8041 mcSHOW_DBG_MSG(("TEMP_SENSOR: OFF\n"));
8042 #endif
8043
8044 HwSaveForSR(p);
8045
8046 ClkFreeRunForDramcPsel(p);
8047
8048 #if ENABLE_RODT_TRACKING
8049 mcSHOW_DBG_MSG(("Read ODT Tracking: ON\n"));
8050 #else
8051 mcSHOW_DBG_MSG(("Read ODT Tracking: OFF\n"));
8052 #endif
8053
8054 #if ENABLE_REFRESH_RATE_DEBOUNCE
8055 mcSHOW_DBG_MSG(("Refresh Rate DeBounce: ON\n"));
8056 DramcRefreshRateDeBounceEnable(p);
8057 #endif
8058
8059 #if ENABLE_DVFS_BYPASS_MR13_FSP
8060 DFSBypassMR13HwSet(p);
8061 #endif
8062
8063 #if (CHECK_GOLDEN_SETTING == TRUE)
8064 DRAM_STATUS_T stResult = CheckGoldenSetting(p);
8065 mcSHOW_DBG_MSG(("End of run time ==>Golden setting check: %s\n", (stResult == DRAM_OK)? ("OK") : ("NG")));
8066 #endif
8067
8068 #if DFS_NOQUEUE_FLUSH_ENABLE
8069 EnableDFSNoQueueFlush(p);
8070 mcSHOW_DBG_MSG(("DFS_NO_QUEUE_FLUSH: ON\n"));
8071 #else
8072 mcSHOW_DBG_MSG(("DFS_NO_QUEUE_FLUSH: OFF\n"));
8073 #endif
8074
8075 #if DFS_NOQUEUE_FLUSH_LATENCY_CNT
8076 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_FSM_CFG, 1, LPIF_FSM_CFG_DBG_LATENCY_CNT_EN);
8077
8078 vIO32WriteFldMulti_All(DDRPHY_MD32_REG_SSPM_MCLK_DIV, P_Fld(0, SSPM_MCLK_DIV_MCLK_SRC)
8079 | P_Fld(0, SSPM_MCLK_DIV_MCLK_DIV));
8080 mcSHOW_DBG_MSG(("DFS_NO_QUEUE_FLUSH_LATENCY_CNT: ON\n"));
8081 #else
8082 mcSHOW_DBG_MSG(("DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF\n"));
8083 #endif
8084
8085 #if ENABLE_DFS_RUNTIME_MRW
8086 #if (REPLACE_DFS_RG_MODE==0)
8087 DFSRuntimeFspMRW(p);
8088 #endif
8089 mcSHOW_DBG_MSG(("ENABLE_DFS_RUNTIME_MRW: ON\n"));
8090 #else
8091 mcSHOW_DBG_MSG(("ENABLE_DFS_RUNTIME_MRW: OFF\n"));
8092 #endif
8093
8094 //CheckRxPICGNewModeSetting(p);
8095 vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL0, 0x0, REFCTRL0_REFDIS);
8096
8097 #if DDR_RESERVE_NEW_MODE
8098 mcSHOW_DBG_MSG(("DDR_RESERVE_NEW_MODE: ON\n"));
8099 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DDR_RESERVE, P_Fld(1, MISC_DDR_RESERVE_WDT_LITE_EN) | P_Fld(0, MISC_DDR_RESERVE_WDT_SM_CLR));
8100 #else
8101 mcSHOW_DBG_MSG(("DDR_RESERVE_NEW_MODE: OFF\n"));
8102 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DDR_RESERVE, P_Fld(0, MISC_DDR_RESERVE_WDT_LITE_EN) | P_Fld(1, MISC_DDR_RESERVE_WDT_SM_CLR));
8103 #endif
8104
8105 #if MR_CBT_SWITCH_FREQ
8106 mcSHOW_DBG_MSG(("MR_CBT_SWITCH_FREQ: ON\n"));
8107 #else
8108 mcSHOW_DBG_MSG(("MR_CBT_SWITCH_FREQ: OFF\n"));
8109 #endif
8110
8111 #if OPEN_LOOP_MODE_CLK_TOGGLE_WA
8112 if(vGet_DDR_Loop_Mode(p) == OPEN_LOOP_MODE)
8113 {
8114 mcSHOW_DBG_MSG(("OPEN_LOOP_MODE_CLK_TOGGLE_WA: ON\n"));
8115 ToggleOpenLoopModeClk(p);
8116 }
8117 #endif
8118
8119 mcSHOW_DBG_MSG(("=========================\n"));
8120 }
8121
8122 #if 0
8123 void DramcTest_DualSch_stress(DRAMC_CTX_T *p)
8124 {
8125 U32 count = 0;
8126 U16 u2Value = 0;
8127
8128 #if MRW_CHECK_ONLY
8129 mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__));
8130 #endif
8131
8132 //vIO32WriteFldAlign_All(DRAMC_REG_PERFCTL0, 1, PERFCTL0_DUALSCHEN);
8133 vIO32WriteFldAlign_All(DRAMC_REG_SHU_SCHEDULER, 1, SHU_SCHEDULER_DUALSCHEN);
8134
8135 while (count < 10)
8136 {
8137 count++;
8138
8139 u1MR12Value[p->channel][p->rank][p->dram_fsp] = 0x14;
8140 DramcModeRegWriteByRank(p, p->rank, 12, u1MR12Value[p->channel][p->rank][p->dram_fsp]);
8141 DramcModeRegReadByRank(p, p->rank, 12, &u2Value);
8142 //mcSHOW_DBG_MSG(("MR12 = 0x%0X\n", u1Value));
8143 }
8144 }
8145 #endif
8146
8147 #if (ENABLE_TX_TRACKING && TX_RETRY_ENABLE)
SPMTx_Track_Retry_OnOff(DRAMC_CTX_T * p,U8 shu_level,U8 onoff)8148 void SPMTx_Track_Retry_OnOff(DRAMC_CTX_T *p, U8 shu_level, U8 onoff)
8149 {
8150 static U8 gIsddr800TxRetry = 0;
8151
8152
8153 if (shu_level == SRAM_SHU6)
8154 {
8155 gIsddr800TxRetry = 1;
8156 }
8157
8158
8159 if ((gIsddr800TxRetry == 1) && (shu_level != SRAM_SHU6)
8160 #if ENABLE_DDR400_OPEN_LOOP_MODE_OPTION
8161 && (shu_level != SRAM_SHU7))
8162 #else
8163 )
8164 #endif
8165 {
8166 if (onoff == ENABLE)
8167 {
8168 mcSHOW_DBG_MSG2(("TX track retry: ENABLE! (DDR800 to DDR1200)\n"));
8169 vIO32WriteFldAlign_All(DRAMC_REG_TX_RETRY_SET0, 1, TX_RETRY_SET0_XSR_TX_RETRY_BLOCK_ALE_MASK);
8170 mcDELAY_US(1);
8171 #if TX_RETRY_CONTROL_BY_SPM
8172 vIO32WriteFldAlign(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 1, LPIF_LOW_POWER_CFG_1_TX_TRACKING_RETRY_EN);
8173 #else
8174 vIO32WriteFldAlign_All(DRAMC_REG_TX_RETRY_SET0, 1, TX_RETRY_SET0_XSR_TX_RETRY_EN);
8175 #endif
8176 }
8177 else
8178 {
8179 mcSHOW_DBG_MSG2(("TX track retry: DISABLE! (DDR800 to DDR1200)\n"));
8180 #if TX_RETRY_CONTROL_BY_SPM
8181 vIO32WriteFldAlign(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 0, LPIF_LOW_POWER_CFG_1_TX_TRACKING_RETRY_EN);
8182 #else
8183 vIO32WriteFldAlign_All(DRAMC_REG_TX_RETRY_SET0, 0, TX_RETRY_SET0_XSR_TX_RETRY_EN);
8184 #endif
8185 mcDELAY_US(1);
8186 vIO32WriteFldAlign_All(DRAMC_REG_TX_RETRY_SET0, 0, TX_RETRY_SET0_XSR_TX_RETRY_BLOCK_ALE_MASK);
8187 gIsddr800TxRetry = 0;
8188 }
8189 }
8190 }
8191
8192 #if SW_TX_RETRY_ENABLE
8193 #define SW_TX_RETRY_ENABLE_WA 1
SWTx_Track_Retry_OnOff(DRAMC_CTX_T * p)8194 void SWTx_Track_Retry_OnOff(DRAMC_CTX_T *p)
8195 {
8196 U8 u4Response;
8197 U8 u1RegBackup_DQSOSCENDIS;
8198 U8 u1Shu_backup=p->ShuRGAccessIdx;
8199 #if SW_TX_RETRY_ENABLE_WA
8200 U8 u1RegBackup;
8201
8202 u1RegBackup=u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DCM_SUB_CTRL), DCM_SUB_CTRL_SUBCLK_CTRL_TX_TRACKING);
8203 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DCM_SUB_CTRL), 0, DCM_SUB_CTRL_SUBCLK_CTRL_TX_TRACKING);
8204 #endif
8205 p->ShuRGAccessIdx = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_10,LPIF_STATUS_10_DRAMC_DR_SHU_LEVEL)& 0x1;
8206 u1RegBackup_DQSOSCENDIS = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DQSOSC_SET0),SHU_DQSOSC_SET0_DQSOSCENDIS);
8207 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DQSOSC_SET0), 1, SHU_DQSOSC_SET0_DQSOSCENDIS);
8208 mcSHOW_DBG_MSG2(("SW TX track retry!\n"));
8209 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_RETRY_SET0), 0, TX_RETRY_SET0_XSR_TX_RETRY_SW_EN);
8210 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_RETRY_SET0), 1, TX_RETRY_SET0_XSR_TX_RETRY_BLOCK_ALE_MASK);
8211 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_RETRY_SET0), 1, TX_RETRY_SET0_XSR_TX_RETRY_SW_EN);
8212 do
8213 {
8214 u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_TX_RETRY_DONE_RESPONSE);
8215 mcDELAY_US(1);
8216 mcSHOW_DBG_MSG4(("still wait tx retry be done\n", u4Response));
8217 }while (u4Response == 0);
8218 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_RETRY_SET0), 0, TX_RETRY_SET0_XSR_TX_RETRY_SW_EN);
8219 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_RETRY_SET0), 0, TX_RETRY_SET0_XSR_TX_RETRY_BLOCK_ALE_MASK);
8220 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DQSOSC_SET0), u1RegBackup_DQSOSCENDIS, SHU_DQSOSC_SET0_DQSOSCENDIS);
8221 #if SW_TX_RETRY_ENABLE_WA
8222 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DCM_SUB_CTRL), u1RegBackup, DCM_SUB_CTRL_SUBCLK_CTRL_TX_TRACKING);
8223 #endif
8224 p->ShuRGAccessIdx=u1Shu_backup;
8225 }
8226 #endif
8227 #endif
8228
8229
DFSInitForCalibration(DRAMC_CTX_T * p)8230 void DFSInitForCalibration(DRAMC_CTX_T *p)
8231 {
8232 #ifdef DDR_INIT_TIME_PROFILING
8233 U32 CPU_Cycle;
8234 mcSHOW_TIME_MSG(("*** Data rate %d ***\n\n", p->frequency << 1));
8235
8236 TimeProfileBegin();
8237 #endif
8238
8239 u1PrintModeRegWrite = 1;
8240
8241 #if MRW_BACKUP
8242 U8 u1RKIdx;
8243
8244 for(u1RKIdx=0; u1RKIdx<p->support_rank_num; u1RKIdx++)
8245 {
8246 gFSPWR_Flag[u1RKIdx]=p->dram_fsp;
8247 }
8248 #endif
8249
8250 DramcInit(p);
8251 u1PrintModeRegWrite = 0;
8252 vBeforeCalibration(p);
8253
8254 #ifdef DUMP_INIT_RG_LOG_TO_DE
8255 while (1);
8256 #endif
8257
8258 #ifdef DDR_INIT_TIME_PROFILING
8259 CPU_Cycle = TimeProfileEnd();
8260 mcSHOW_TIME_MSG((" DFSInitForCalibration() take %d ms\n\n", CPU_Cycle / 1000));
8261 #endif
8262
8263 #ifndef DUMP_INIT_RG_LOG_TO_DE
8264 #ifdef ENABLE_MIOCK_JMETER
8265 if ((Get_MDL_Used_Flag()==NORMAL_USED) && (p->frequency >= 800))
8266 {
8267 Get_RX_DelayCell(p);
8268 }
8269 #endif
8270 #endif
8271
8272 #ifdef DDR_INIT_TIME_PROFILING
8273 TimeProfileBegin();
8274 #endif
8275
8276 #ifndef DUMP_INIT_RG_LOG_TO_DE
8277 #ifdef ENABLE_MIOCK_JMETER
8278 if (Get_MDL_Used_Flag()==NORMAL_USED)
8279 {
8280 p->u2DelayCellTimex100 = GetVcoreDelayCellTime(p);
8281 }
8282 #endif
8283 #endif
8284
8285 #ifdef DDR_INIT_TIME_PROFILING
8286 CPU_Cycle=TimeProfileEnd();
8287 mcSHOW_TIME_MSG((" (3) JMeter takes %d ms\n\r", CPU_Cycle / 1000));
8288 #endif
8289 }
8290
8291 #if 0
8292 void DramcHWDQSGatingTracking_ModeSetting(DRAMC_CTX_T *p)
8293 {
8294 #ifdef HW_GATING
8295 #if DramcHWDQSGatingTracking_FIFO_MODE
8296
8297 vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL),
8298 P_Fld(1, MISC_STBCAL_STB_DQIEN_IG) |
8299 P_Fld(1, MISC_STBCAL_PICHGBLOCK_NORD) |
8300 P_Fld(0, MISC_STBCAL_REFUICHG) |
8301 P_Fld(0, MISC_STBCAL_PHYVALID_IG) |
8302 P_Fld(0, MISC_STBCAL_STBSTATE_OPT) |
8303 P_Fld(0, MISC_STBCAL_STBDLELAST_FILTER) |
8304 P_Fld(0, MISC_STBCAL_STBDLELAST_PULSE) |
8305 P_Fld(0, MISC_STBCAL_STBDLELAST_OPT) |
8306 P_Fld(1, MISC_STBCAL_PIMASK_RKCHG_OPT));
8307
8308 vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1),
8309 P_Fld(1, MISC_STBCAL1_STBCAL_FILTER) |
8310 //P_Fld(1, MISC_STBCAL1_STB_FLAGCLR) |
8311 P_Fld(1, MISC_STBCAL1_STB_SHIFT_DTCOUT_IG));
8312
8313 vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL0),
8314 P_Fld(1, MISC_CTRL0_R_DMDQSIEN_FIFO_EN) |
8315 P_Fld(0, MISC_CTRL0_R_DMVALID_DLY) |
8316 P_Fld(0, MISC_CTRL0_R_DMVALID_DLY_OPT) |
8317 P_Fld(0, MISC_CTRL0_R_DMVALID_NARROW_IG));
8318 //P_Fld(0, MISC_CTRL0_R_DMDQSIEN_SYNCOPT));
8319
8320 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6),
8321 0, B0_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B0);
8322 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6),
8323 0, B1_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B1);
8324 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD6),
8325 0, CA_CMD6_RG_RX_ARCMD_DMRANK_OUTSEL);
8326
8327 #else
8328
8329 vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL),
8330 P_Fld(1, MISC_STBCAL_STB_DQIEN_IG) |
8331 P_Fld(1, MISC_STBCAL_PICHGBLOCK_NORD) |
8332 P_Fld(0, MISC_STBCAL_REFUICHG) |
8333 P_Fld(0, MISC_STBCAL_PHYVALID_IG) |
8334 P_Fld(0, MISC_STBCAL_STBSTATE_OPT) |
8335 P_Fld(0, MISC_STBCAL_STBDLELAST_FILTER) |
8336 P_Fld(0, MISC_STBCAL_STBDLELAST_PULSE) |
8337 P_Fld(0, MISC_STBCAL_STBDLELAST_OPT) |
8338 P_Fld(1, MISC_STBCAL_PIMASK_RKCHG_OPT));
8339
8340 vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1),
8341 P_Fld(1, MISC_STBCAL1_STBCAL_FILTER) |
8342 //P_Fld(1, MISC_STBCAL1_STB_FLAGCLR) |
8343 P_Fld(0, MISC_STBCAL1_STB_SHIFT_DTCOUT_IG));
8344
8345
8346 vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL0),
8347 P_Fld(0, MISC_CTRL0_R_DMDQSIEN_FIFO_EN) |
8348 P_Fld(3, MISC_CTRL0_R_DMVALID_DLY) |
8349 P_Fld(1, MISC_CTRL0_R_DMVALID_DLY_OPT) |
8350 P_Fld(0, MISC_CTRL0_R_DMVALID_NARROW_IG));
8351 //P_Fld(0xf, MISC_CTRL0_R_DMDQSIEN_SYNCOPT));
8352
8353 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6),
8354 1, B0_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B0);
8355 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6),
8356 1, B1_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B1);
8357 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD6),
8358 1, CA_CMD6_RG_RX_ARCMD_DMRANK_OUTSEL);
8359 #endif
8360 #endif
8361 }
8362 #endif
8363
8364 #if TX_PICG_NEW_MODE
8365 #if 0
8366 void GetTXPICGSetting(DRAMC_CTX_T * p)
8367 {
8368 U32 u4DQS_OEN_final, u4DQ_OEN_final;
8369 U16 u2DQS_OEN_2T[2], u2DQS_OEN_05T[2], u2DQS_OEN_Delay[2];
8370 U16 u2DQ_OEN_2T[2], u2DQ_OEN_05T[2], u2DQ_OEN_Delay[2];
8371 U16 u2COMB_TX_SEL[2];
8372 U16 u2Shift_Div[2];
8373 U16 u2COMB_TX_PICG_CNT;
8374 U8 u1CHIdx, u1RankIdx, u1Rank_bak = u1GetRank(p), u1backup_CH = vGetPHY2ChannelMapping(p), u1Div_ratio;
8375
8376 mcSHOW_DBG_MSG(("****** GetTXPICGSetting DDR[%d] @@@\n", p->frequency * 2));
8377
8378 for (u1CHIdx = 0; u1CHIdx < p->support_channel_num; u1CHIdx++)
8379 {
8380 vSetPHY2ChannelMapping(p, u1CHIdx);
8381
8382 u2DQS_OEN_2T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS0), SHU_SELPH_DQS0_TXDLY_OEN_DQS0);
8383 u2DQS_OEN_05T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS1), SHU_SELPH_DQS1_DLY_OEN_DQS0);
8384
8385 u2DQS_OEN_2T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS0), SHU_SELPH_DQS0_TXDLY_OEN_DQS1);
8386 u2DQS_OEN_05T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS1), SHU_SELPH_DQS1_DLY_OEN_DQS1);
8387
8388 mcSHOW_DBG_MSG(("CH%d\n", u1CHIdx));
8389 mcSHOW_DBG_MSG(("DQS0 m=%d n=%d \n", u2DQS_OEN_2T[0], u2DQS_OEN_05T[0]));
8390 mcSHOW_DBG_MSG(("DQS1 m=%d n=%d \n", u2DQS_OEN_2T[1], u2DQS_OEN_05T[1]));
8391
8392
8393
8394 u2COMB_TX_SEL[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_APHY_TX_PICG_CTRL), SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0);
8395 u2COMB_TX_SEL[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_APHY_TX_PICG_CTRL), SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1);
8396 u2COMB_TX_PICG_CNT = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_APHY_TX_PICG_CTRL), SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT);
8397
8398 mcSHOW_DBG_MSG(("TX_DQS_SEL_P0 %d \n", u2COMB_TX_SEL[0]));
8399 mcSHOW_DBG_MSG(("TX_DQS_SEL_P1 %d \n", u2COMB_TX_SEL[1]));
8400 mcSHOW_DBG_MSG(("COMB_TX_PICG_CNT %d \n", u2COMB_TX_PICG_CNT));
8401
8402
8403 for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
8404 {
8405 mcSHOW_DBG_MSG(("Rank%d\n", u1RankIdx));
8406
8407 vSetRank(p, u1RankIdx);
8408
8409 u2DQ_OEN_2T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_OEN_DQ0);
8410 u2DQ_OEN_05T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), SHURK_SELPH_DQ2_DLY_OEN_DQ0);
8411
8412 u2DQ_OEN_2T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_OEN_DQ1);
8413 u2DQ_OEN_05T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), SHURK_SELPH_DQ2_DLY_OEN_DQ1);
8414
8415 mcSHOW_DBG_MSG(("DQ0 p=%d q=%d \n", u2DQ_OEN_2T[0], u2DQ_OEN_05T[0]));
8416 mcSHOW_DBG_MSG(("DQ1 p=%d q=%d \n", u2DQ_OEN_2T[1], u2DQ_OEN_05T[1]));
8417
8418 u2COMB_TX_SEL[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL), SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0);
8419 u2COMB_TX_SEL[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL), SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1);
8420
8421 mcSHOW_DBG_MSG(("TX_DQ_RK_SEL_P0 %d \n", u2COMB_TX_SEL[0]));
8422 mcSHOW_DBG_MSG(("TX_DQ_RK_SEL_P1 %d \n", u2COMB_TX_SEL[1]));
8423 }
8424 vSetRank(p, u1Rank_bak);
8425 }
8426 vSetPHY2ChannelMapping(p, u1backup_CH);
8427 }
8428 #endif
8429
8430 #define ADD_1UI_TO_APHY 1
TXPICGSetting(DRAMC_CTX_T * p)8431 void TXPICGSetting(DRAMC_CTX_T * p)
8432 {
8433 U32 u4DQS_OEN_final, u4DQ_OEN_final;
8434 U16 u2DQS_OEN_2T[2], u2DQS_OEN_05T[2], u2DQS_OEN_Delay[2];
8435 U16 u2DQ_OEN_2T[2], u2DQ_OEN_05T[2], u2DQ_OEN_Delay[2];
8436 U16 u2COMB_TX_SEL[2];
8437 U16 u2Shift_DQS_Div[2];
8438 U16 u2Shift_DQ_Div[2];
8439 U16 u2COMB_TX_PICG_CNT;
8440 U8 u1CHIdx, u1RankIdx, u1Rank_bak = u1GetRank(p), u1backup_CH = vGetPHY2ChannelMapping(p), u1Div_ratio;
8441
8442 u2COMB_TX_PICG_CNT = 3;
8443 if (vGet_Div_Mode(p) == DIV8_MODE)
8444 {
8445 u2Shift_DQS_Div[0] = 10;
8446 u2Shift_DQS_Div[1] = 6;
8447 u2Shift_DQ_Div[0] = 8;
8448 u2Shift_DQ_Div[1] = 4;
8449 u1Div_ratio = 3;
8450 }
8451 else
8452 {
8453 u2Shift_DQS_Div[0] = 2;
8454 u2Shift_DQS_Div[1] = 0;
8455 u2Shift_DQ_Div[0] = 0;
8456 u2Shift_DQ_Div[1] = 0;
8457 u1Div_ratio = 2;
8458 }
8459
8460 for (u1CHIdx = 0; u1CHIdx < p->support_channel_num; u1CHIdx++)
8461 {
8462 vSetPHY2ChannelMapping(p, u1CHIdx);
8463
8464 u2DQS_OEN_2T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS0), SHU_SELPH_DQS0_TXDLY_OEN_DQS0);
8465 u2DQS_OEN_05T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS1), SHU_SELPH_DQS1_DLY_OEN_DQS0);
8466 u2DQS_OEN_Delay[0] = (u2DQS_OEN_2T[0] << u1Div_ratio) + u2DQS_OEN_05T[0];
8467
8468 u2DQS_OEN_2T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS0), SHU_SELPH_DQS0_TXDLY_OEN_DQS1);
8469 u2DQS_OEN_05T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS1), SHU_SELPH_DQS1_DLY_OEN_DQS1);
8470 u2DQS_OEN_Delay[1] = (u2DQS_OEN_2T[1] << u1Div_ratio) + u2DQS_OEN_05T[1];
8471
8472 u4DQS_OEN_final = (u2DQS_OEN_Delay[0] > u2DQS_OEN_Delay[1])? u2DQS_OEN_Delay[1]: u2DQS_OEN_Delay[0];
8473 u4DQS_OEN_final += ADD_1UI_TO_APHY;
8474
8475
8476 u2COMB_TX_SEL[0] = (u4DQS_OEN_final > u2Shift_DQS_Div[0])? ((u4DQS_OEN_final - u2Shift_DQS_Div[0]) >> u1Div_ratio): 0;
8477
8478 if (vGet_Div_Mode(p) == DIV4_MODE)
8479 u2COMB_TX_SEL[1] = 0;
8480 else
8481 u2COMB_TX_SEL[1] = (u4DQS_OEN_final > u2Shift_DQS_Div[1])? ((u4DQS_OEN_final - u2Shift_DQS_Div[1]) >> u1Div_ratio): 0;
8482
8483 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_APHY_TX_PICG_CTRL), P_Fld(u2COMB_TX_SEL[0], SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0)
8484 | P_Fld(u2COMB_TX_SEL[1], SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1)
8485 | P_Fld(u2COMB_TX_PICG_CNT, SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT));
8486
8487 for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
8488 {
8489 vSetRank(p, u1RankIdx);
8490
8491 u2DQ_OEN_2T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_OEN_DQ0);
8492 u2DQ_OEN_05T[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), SHURK_SELPH_DQ2_DLY_OEN_DQ0);
8493 u2DQ_OEN_Delay[0] = (u2DQ_OEN_2T[0] << u1Div_ratio) + u2DQ_OEN_05T[0];
8494
8495 u2DQ_OEN_2T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_OEN_DQ1);
8496 u2DQ_OEN_05T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), SHURK_SELPH_DQ2_DLY_OEN_DQ1);
8497 u2DQ_OEN_Delay[1] = (u2DQ_OEN_2T[1] << u1Div_ratio) + u2DQ_OEN_05T[1];
8498
8499
8500 u4DQ_OEN_final = (u2DQ_OEN_Delay[0] > u2DQ_OEN_Delay[1])? u2DQ_OEN_Delay[1]: u2DQ_OEN_Delay[0];
8501 u4DQ_OEN_final += ADD_1UI_TO_APHY;
8502
8503 u2COMB_TX_SEL[0] = (u4DQ_OEN_final > u2Shift_DQ_Div[0])? ((u4DQ_OEN_final - u2Shift_DQ_Div[0]) >> u1Div_ratio): 0;
8504
8505 if (vGet_Div_Mode(p) == DIV4_MODE)
8506 u2COMB_TX_SEL[1] = 0;
8507 else
8508 u2COMB_TX_SEL[1] = (u4DQ_OEN_final > u2Shift_DQ_Div[1])? ((u4DQ_OEN_final - u2Shift_DQ_Div[1]) >> u1Div_ratio): 0;
8509
8510 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL), P_Fld(u2COMB_TX_SEL[0], SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0)
8511 | P_Fld(u2COMB_TX_SEL[1], SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1));
8512 }
8513 vSetRank(p, u1Rank_bak);
8514 }
8515 vSetPHY2ChannelMapping(p, u1backup_CH);
8516 }
8517 #endif
8518
8519
8520 #if RX_PICG_NEW_MODE
RXPICGSetting(DRAMC_CTX_T * p)8521 static void RXPICGSetting(DRAMC_CTX_T * p)
8522 {
8523 DRAM_RANK_T bkRank = u1GetRank(p);
8524 U8 u1RankIdx = 0;
8525
8526 vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_STBCAL, 0, MISC_SHU_STBCAL_STBCALEN);
8527 vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_STBCAL, 0, MISC_SHU_STBCAL_STB_SELPHCALEN);
8528
8529
8530 vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL1, 1, MISC_STBCAL1_STBCNT_SHU_RST_EN);
8531 vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL2, 1, MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN);
8532 vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_STBCAL, 1, MISC_SHU_STBCAL_DQSIEN_PICG_MODE);
8533
8534
8535 vIO32WriteFldAlign(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL, 1, MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_OPT);
8536 vIO32WriteFldAlign(DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL, 1, MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_OPT);
8537
8538
8539 {
8540 U8 u1TAIL_LAT = (vGet_Div_Mode(p) == DIV4_MODE) ? 1: 0;
8541 vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL2, 0, MISC_STBCAL2_STB_STBENRST_EARLY_1T_EN);
8542
8543 for (u1RankIdx = 0; u1RankIdx < p->support_rank_num; u1RankIdx++)
8544 {
8545 vSetRank(p, u1RankIdx);
8546 vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RK_DQSIEN_PICG_CTRL, P_Fld(u1TAIL_LAT, MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT)
8547 | P_Fld(0, MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT));
8548 }
8549 vSetRank(p, bkRank);
8550
8551 vIO32WriteFldMulti(DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL, P_Fld(0, MISC_RX_IN_BUFF_EN_CTRL_DIS_IN_BUFF_EN)
8552 | P_Fld(0, MISC_RX_IN_BUFF_EN_CTRL_FIX_IN_BUFF_EN)
8553 | P_Fld(0, MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_4BYTE_EN));
8554
8555 vIO32WriteFldMulti(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL, P_Fld(0, MISC_RX_IN_GATE_EN_CTRL_DIS_IN_GATE_EN)
8556 | P_Fld(0, MISC_RX_IN_GATE_EN_CTRL_FIX_IN_GATE_EN)
8557 | P_Fld(0, MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_4BYTE_EN));
8558
8559 }
8560 #if 0
8561 vIO32WriteFldAlign(DRAMC_REG_STBCAL2, 0, STBCAL2_STB_STBENRST_EARLY_1T_EN);
8562 vIO32WriteFldMulti(DRAMC_REG_SHU_STBCAL, P_Fld(u1TAIL_LAT, SHU_STBCAL_R1_DQSIEN_PICG_TAIL_EXT_LAT)
8563 | P_Fld(0, SHU_STBCAL_R1_DQSIEN_PICG_HEAD_EXT_LAT)
8564 | P_Fld(u1TAIL_LAT, SHU_STBCAL_R0_DQSIEN_PICG_TAIL_EXT_LAT)
8565 | P_Fld(0, SHU_STBCAL_R0_DQSIEN_PICG_HEAD_EXT_LAT));
8566 vIO32WriteFldMulti(DRAMC_REG_PHY_RX_INCTL, P_Fld(0, PHY_RX_INCTL_DIS_IN_BUFF_EN)
8567 | P_Fld(0, PHY_RX_INCTL_FIX_IN_BUFF_EN)
8568 | P_Fld(0, PHY_RX_INCTL_RX_IN_BUFF_EN_4BYTE_EN)
8569 | P_Fld(0, PHY_RX_INCTL_DIS_IN_GATE_EN)
8570 | P_Fld(0, PHY_RX_INCTL_FIX_IN_GATE_EN)
8571 | P_Fld(0, PHY_RX_INCTL_RX_IN_GATE_EN_4BYTE_EN));
8572 #endif
8573 }
8574 #endif
8575
8576 #ifndef DPM_CONTROL_AFTERK
dramc_exit_with_DFS_legacy_mode(DRAMC_CTX_T * p)8577 void dramc_exit_with_DFS_legacy_mode(DRAMC_CTX_T * p)
8578 {
8579 #if !__ETT__
8580
8581 vIO32WriteFldAlign(SPM_POWERON_CONFIG_EN, 1, POWERON_CONFIG_EN_BCLK_CG_EN);
8582 vIO32WriteFldAlign(SPM_DRAMC_DPY_CLK_SW_CON_2, 1, SPM_DRAMC_DPY_CLK_SW_CON_2_SW_PHYPLL_MODE_SW);
8583 vIO32WriteFldAlign(SPM_POWER_ON_VAL0, 1, SPM_POWER_ON_VAL0_SC_PHYPLL_MODE_SW);
8584 #endif
8585
8586 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0x0, MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL);
8587 vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 0x0, PHYPLL0_RG_RPHYPLL_EN);
8588 vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 0x0, CLRPLL0_RG_RCLRPLL_EN);
8589 }
8590 #endif
8591
8592 #if TX_PICG_NEW_MODE
TXPICGNewModeEnable(DRAMC_CTX_T * p)8593 void TXPICGNewModeEnable(DRAMC_CTX_T * p)
8594 {
8595
8596 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CTRL3, P_Fld(0, MISC_CTRL3_ARPI_CG_MCK_DQ_OPT)
8597 | P_Fld(0, MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT)
8598 | P_Fld(0, MISC_CTRL3_ARPI_CG_DQS_OPT)
8599 | P_Fld(0, MISC_CTRL3_ARPI_CG_DQ_OPT));
8600 }
8601 #endif
8602
8603 #if ENABLE_WRITE_DBI_Protect
ApplyWriteDBIProtect(DRAMC_CTX_T * p,U8 onoff)8604 void ApplyWriteDBIProtect(DRAMC_CTX_T *p, U8 onoff)
8605 {
8606 #if __A60868_TO_BE_PORTING__
8607 U8 *uiLPDDR_O1_Mapping;
8608 U16 Temp_PinMux_MaskWrite_WriteDBIOn = 0;
8609 U8 B0_PinMux_MaskWrite_WriteDBIOn = 0, B1_PinMux_MaskWrite_WriteDBIOn = 0;
8610 int DQ_index;
8611
8612 uiLPDDR_O1_Mapping = (U8 *)uiLPDDR4_O1_Mapping_POP[p->channel];
8613
8614
8615 for (DQ_index = 0; DQ_index < 16; DQ_index++)
8616 {
8617 Temp_PinMux_MaskWrite_WriteDBIOn |= ((0x7C7C >> uiLPDDR_O1_Mapping[DQ_index]) & 0x1) << DQ_index;
8618 }
8619 B1_PinMux_MaskWrite_WriteDBIOn = (U8)(Temp_PinMux_MaskWrite_WriteDBIOn >> 8) & 0xff;
8620 B0_PinMux_MaskWrite_WriteDBIOn = (U8) Temp_PinMux_MaskWrite_WriteDBIOn & 0xff;
8621
8622 vIO32WriteFldMulti_All(DRAMC_REG_ARBCTL, P_Fld(B1_PinMux_MaskWrite_WriteDBIOn, ARBCTL_DBIWR_OPT_B1)
8623 | P_Fld(B0_PinMux_MaskWrite_WriteDBIOn, ARBCTL_DBIWR_OPT_B0)
8624 | P_Fld(onoff, ARBCTL_DBIWR_PINMUX_EN)
8625 | P_Fld(onoff, ARBCTL_DBIWR_IMP_EN));
8626 #endif
8627 }
8628 #endif
8629
8630 #if ENABLE_WRITE_DBI
ApplyWriteDBIPowerImprove(DRAMC_CTX_T * p,U8 onoff)8631 void ApplyWriteDBIPowerImprove(DRAMC_CTX_T *p, U8 onoff)
8632 {
8633
8634
8635 vIO32WriteFldMulti_All(DRAMC_REG_DBIWR_PROTECT, P_Fld(0, DBIWR_PROTECT_DBIWR_OPT_B1)
8636 | P_Fld(0, DBIWR_PROTECT_DBIWR_OPT_B0)
8637 | P_Fld(0, DBIWR_PROTECT_DBIWR_PINMUX_EN)
8638 | P_Fld(onoff, DBIWR_PROTECT_DBIWR_IMP_EN));
8639 }
8640
8641 #endif
8642
8643
RODTSettings(DRAMC_CTX_T * p)8644 static void RODTSettings(DRAMC_CTX_T *p)
8645 {
8646 U8 u1VrefSel;
8647 U8 u1RankIdx, u1RankIdxBak;
8648 BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
8649
8650
8651 vIO32WriteFldAlign(DDRPHY_REG_B0_DQ5, 1, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0);
8652 vIO32WriteFldAlign(DDRPHY_REG_B1_DQ5, !isLP4_DSC, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1);
8653 vIO32WriteFldAlign(DDRPHY_REG_CA_CMD5, isLP4_DSC, CA_CMD5_RG_RX_ARCMD_VREF_EN);
8654
8655
8656 vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_VREF, !(p->odt_onoff), SHU_B0_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B0);
8657 if (!isLP4_DSC)
8658 vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_VREF, !(p->odt_onoff), SHU_B1_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B1);
8659 else
8660 vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_VREF, !(p->odt_onoff), SHU_CA_VREF_RG_RX_ARCA_VREF_UNTERM_EN_CA);
8661
8662 if(p->odt_onoff==ODT_ON)
8663 {
8664 u1VrefSel = 0x2c;
8665 }
8666 else
8667 {
8668 u1VrefSel = 0x37;
8669 }
8670
8671 u1RankIdxBak = u1GetRank(p);
8672 for (u1RankIdx = 0; u1RankIdx < (U32)(p->support_rank_num); u1RankIdx++)
8673 {
8674 vSetRank(p, u1RankIdx);
8675 vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_PHY_VREF_SEL,
8676 P_Fld(u1VrefSel, SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B0) |
8677 P_Fld(u1VrefSel, SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_UB_B0));
8678 if (!isLP4_DSC){
8679 vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_PHY_VREF_SEL,
8680 P_Fld(u1VrefSel, SHU_B1_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B1) |
8681 P_Fld(u1VrefSel, SHU_B1_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_UB_B1));
8682 }
8683 else
8684 {
8685 vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_PHY_VREF_SEL,
8686 P_Fld(u1VrefSel, SHU_CA_PHY_VREF_SEL_RG_RX_ARCA_VREF_SEL_LB) |
8687 P_Fld(u1VrefSel, SHU_CA_PHY_VREF_SEL_RG_RX_ARCA_VREF_SEL_UB));
8688 }
8689 }
8690 vSetRank(p, u1RankIdxBak);
8691
8692 vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_VREF, 1, SHU_B0_VREF_RG_RX_ARDQ_VREF_RANK_SEL_EN_B0);
8693 if (!isLP4_DSC)
8694 vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_VREF, 1, SHU_B1_VREF_RG_RX_ARDQ_VREF_RANK_SEL_EN_B1);
8695 else
8696 vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_VREF, 1, SHU_CA_VREF_RG_RX_ARCA_VREF_RANK_SEL_EN_CA);
8697
8698 #if ENABLE_TX_WDQS
8699 vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_ODTCTRL, 1, MISC_SHU_ODTCTRL_RODTEN);
8700 vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DQ7, 1, SHU_B0_DQ7_R_DMRODTEN_B0);
8701 vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DQ7, !isLP4_DSC, SHU_B1_DQ7_R_DMRODTEN_B1);
8702 vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_CMD7, isLP4_DSC, SHU_CA_CMD7_R_DMRODTEN_CA);
8703 #else
8704 vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_ODTCTRL, p->odt_onoff, MISC_SHU_ODTCTRL_RODTEN);
8705 vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DQ7, p->odt_onoff, SHU_B0_DQ7_R_DMRODTEN_B0);
8706 vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DQ7, (p->odt_onoff & !isLP4_DSC), SHU_B1_DQ7_R_DMRODTEN_B1);
8707 vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_CMD7, (p->odt_onoff & isLP4_DSC), SHU_CA_CMD7_R_DMRODTEN_CA);
8708 #endif
8709
8710 #if ENABLE_RODT_TRACKING
8711
8712 vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RODTENSTB, P_Fld(1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN)
8713 | P_Fld(1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL)
8714 | P_Fld(0, MISC_SHU_RODTENSTB_RODTENSTB_SELPH_BY_BITTIME));
8715 #endif
8716
8717
8718 vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DQ13, !(p->odt_onoff), SHU_B0_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B0);
8719 vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DQ13, !(p->odt_onoff), SHU_B1_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B1);
8720 vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_CMD13, !(p->odt_onoff), SHU_CA_CMD13_RG_TX_ARCA_IO_ODT_DIS_CA);
8721
8722
8723 vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ13, P_Fld(0, SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B0)
8724 | P_Fld(0, SHU_B0_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B0));
8725 vIO32WriteFldAlign(DDRPHY_REG_SHU_B0_DQ14, 0, SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B0);
8726
8727 if (!isLP4_DSC)
8728 {
8729 vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ13, P_Fld(0, SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B1)
8730 | P_Fld(0, SHU_B1_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B1));
8731 vIO32WriteFldAlign(DDRPHY_REG_SHU_B1_DQ14, 0, SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B1);
8732 }
8733 else
8734 {
8735 vIO32WriteFldMulti(DDRPHY_REG_SHU_CA_CMD13, P_Fld(0, SHU_CA_CMD13_RG_TX_ARCLK_OE_ODTEN_CG_EN_CA)
8736 | P_Fld(0, SHU_CA_CMD13_RG_TX_ARCS_OE_ODTEN_CG_EN_CA));
8737 vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_CMD14, 0, SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_CG_EN_CA);
8738 }
8739 }
8740
8741
DQSSTBSettings(DRAMC_CTX_T * p)8742 static void DQSSTBSettings(DRAMC_CTX_T *p)
8743 {
8744 unsigned int dqsien_mode = 1;
8745 BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
8746
8747 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL),
8748 dqsien_mode, MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE);
8749 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ10),
8750 dqsien_mode, SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B0);
8751 if(!isLP4_DSC)
8752 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ10),
8753 dqsien_mode, SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B1);
8754 else
8755 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD10),
8756 dqsien_mode, SHU_CA_CMD10_RG_RX_ARCLK_DQSIEN_MODE_CA);
8757 }
8758
SetMck8xLowPwrOption(DRAMC_CTX_T * p)8759 static void SetMck8xLowPwrOption(DRAMC_CTX_T *p)
8760 {
8761 #if ENABLE_REMOVE_MCK8X_UNCERT_LOWPOWER_OPTION
8762 U32 u4Mck8xMode = 1;
8763 #else
8764 U32 u4Mck8xMode = 0;
8765 #endif
8766
8767 vIO32WriteFldMulti(DDRPHY_REG_MISC_LP_CTRL, P_Fld( u4Mck8xMode , MISC_LP_CTRL_RG_SC_ARPI_RESETB_8X_SEQ_LP_SEL ) \
8768 | P_Fld( u4Mck8xMode , MISC_LP_CTRL_RG_ADA_MCK8X_8X_SEQ_LP_SEL ) \
8769 | P_Fld( u4Mck8xMode, MISC_LP_CTRL_RG_AD_MCK8X_8X_SEQ_LP_SEL ) \
8770 | P_Fld( u4Mck8xMode , MISC_LP_CTRL_RG_MIDPI_EN_8X_SEQ_LP_SEL ) \
8771 | P_Fld( u4Mck8xMode , MISC_LP_CTRL_RG_MIDPI_CKDIV4_EN_8X_SEQ_LP_SEL) \
8772 | P_Fld( u4Mck8xMode, MISC_LP_CTRL_RG_MCK8X_CG_SRC_LP_SEL ) \
8773 | P_Fld( u4Mck8xMode , MISC_LP_CTRL_RG_MCK8X_CG_SRC_AND_LP_SEL ));
8774
8775 }
8776
LP4_UpdateInitialSettings(DRAMC_CTX_T * p)8777 void LP4_UpdateInitialSettings(DRAMC_CTX_T *p)
8778 {
8779 U8 u1RankIdx, u1RankIdxBak;
8780
8781 vIO32WriteFldAlign(DDRPHY_REG_MISC_CTRL3, 0, MISC_CTRL3_ARPI_CG_CLK_OPT);
8782 vIO32WriteFldAlign(DDRPHY_REG_MISC_CTRL4, 0, MISC_CTRL4_R_OPT2_CG_CLK);
8783
8784 //vIO32WriteFldMulti_All(DDRPHY_REG_CA_CMD2, P_Fld(1, CA_CMD2_RG_TX_ARCLK_OE_TIE_EN_CA) | P_Fld(0, CA_CMD2_RG_TX_ARCLK_OE_TIE_SEL_CA));
8785 //vIO32WriteFldMulti_All(DDRPHY_REG_CA_CMD2, P_Fld(1, CA_CMD2_RG_TX_ARCLKB_OE_TIE_EN_CA) | P_Fld(0, CA_CMD2_RG_TX_ARCLKB_OE_TIE_SEL_CA));
8786 //Set_MRR_Pinmux_Mapping(p);
8787
8788 vReplaceDVInit(p);
8789
8790
8791 vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_CMD14, 0x0, SHU_CA_CMD14_RG_TX_ARCA_MCKIO_SEL_CA);
8792
8793
8794 vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0)
8795 | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0)
8796 | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0));
8797 vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1)
8798 | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1)
8799 | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1));
8800
8801 #if RX_PICG_NEW_MODE
8802 RXPICGSetting(p);
8803 #endif
8804
8805 #if SIMULATION_SW_IMPED
8806 #if FSP1_CLKCA_TERM
8807 U8 u1CASwImpFreqRegion = (p->dram_fsp == FSP_0)? IMP_LOW_FREQ: IMP_HIGH_FREQ;
8808 #else
8809 U8 u1CASwImpFreqRegion = (p->frequency <= 1866)? IMP_LOW_FREQ: IMP_HIGH_FREQ;
8810 #endif
8811 U8 u1DQSwImpFreqRegion = (p->frequency <= 1866)? IMP_LOW_FREQ: IMP_HIGH_FREQ;
8812
8813 if (p->dram_type == TYPE_LPDDR4X)
8814 DramcSwImpedanceSaveRegister(p, u1CASwImpFreqRegion, u1DQSwImpFreqRegion, DRAM_DFS_REG_SHU0);
8815 #endif
8816
8817 DQSSTBSettings(p);
8818
8819 RODTSettings(p);
8820
8821
8822 vIO32WriteFldAlign(DRAMC_REG_SHU_TX_SET0, 0x0, SHU_TX_SET0_DBIWR);
8823
8824 #if CBT_MOVE_CA_INSTEAD_OF_CLK
8825 U8 u1CaPI = 0, u1CaUI = 0;
8826
8827 u1CaUI = 1;
8828 u1CaPI = 0;
8829
8830
8831 DramcCmdUIDelaySetting(p, u1CaUI);
8832 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA5), P_Fld(0x1, SHU_SELPH_CA5_DLY_CS) | P_Fld(0x1, SHU_SELPH_CA5_DLY_CS1));
8833
8834
8835
8836 u1RankIdxBak = u1GetRank(p);
8837
8838 for (u1RankIdx = 0; u1RankIdx < (U32)(p->support_rank_num); u1RankIdx++)
8839 {
8840 vSetRank(p, u1RankIdx);
8841
8842 CBTDelayCACLK(p, u1CaPI);
8843 }
8844
8845 vSetRank(p, u1RankIdxBak);
8846 #endif
8847
8848 #if ENABLE_TPBR2PBR_REFRESH_TIMING
8849 vIO32WriteFldAlign(DRAMC_REG_REFCTRL1, 0x1, REFCTRL1_REF_OVERHEAD_PBR2PB_ENA);
8850 vIO32WriteFldAlign(DRAMC_REG_MISCTL0, 0x1, MISCTL0_REFP_ARBMASK_PBR2PBR_ENA);
8851 vIO32WriteFldAlign(DRAMC_REG_SCHEDULER_COM, 0x1, SCHEDULER_COM_PBR2PBR_OPT);
8852 #endif
8853
8854 #if RDSEL_TRACKING_EN
8855 vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, 0, SHU_MISC_RDSEL_TRACK_DMDATLAT_I);
8856 #endif
8857
8858 #if ENABLE_WRITE_POST_AMBLE_1_POINT_5_TCK
8859 vIO32WriteFldAlign(DRAMC_REG_SHU_TX_SET0, p->dram_fsp, SHU_TX_SET0_WPST1P5T);
8860 #else
8861 vIO32WriteFldAlign(DRAMC_REG_SHU_TX_SET0, 0x0, SHU_TX_SET0_WPST1P5T);
8862 #endif
8863
8864 #if (!XRTRTR_NEW_CROSS_RK_MODE)
8865 vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, 0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN);
8866 #endif
8867
8868 #if (fcFOR_CHIP_ID == fc8195)
8869 if(p->support_rank_num== RANK_SINGLE)
8870 vIO32WriteFldAlign(DRAMC_REG_CMD_DEC_CTRL0, 1, CMD_DEC_CTRL0_CS1FIXOFF);
8871
8872 //vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_EMI_CTRL, 0x26, SHU_MISC_EMI_CTRL_DR_EMI_RESERVE);
8873 #endif
8874
8875
8876 vIO32WriteFldMulti(DRAMC_REG_DUMMY_RD, P_Fld(0x1, DUMMY_RD_DMYRD_REORDER_DIS) | P_Fld(0x1, DUMMY_RD_SREF_DMYRD_EN));
8877
8878 vIO32WriteFldMulti(DRAMC_REG_DRAMCTRL, P_Fld(0x0, DRAMCTRL_ALL_BLOCK_CTO_ALE_DBG_EN)
8879 | P_Fld(0x1, DRAMCTRL_DVFS_BLOCK_CTO_ALE_DBG_EN)
8880 | P_Fld(0x1, DRAMCTRL_SELFREF_BLOCK_CTO_ALE_DBG_EN));
8881 vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL2, 1, MISC_STBCAL2_DQSGCNT_BYP_REF);
8882
8883 if(p->frequency<=800)
8884 vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, 0, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD);
8885 else if(p->frequency<=1200)
8886 vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, 1, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD);
8887 else
8888 vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_PHY_RX_CTRL, 2, MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD);
8889
8890
8891 vIO32WriteFldAlign(DDRPHY_REG_MISC_CTRL1, 1, MISC_CTRL1_R_DMARPIDQ_SW);
8892
8893
8894 vIO32WriteFldMulti(DDRPHY_REG_CA_TX_MCK, P_Fld(0xa, CA_TX_MCK_R_DMRESETB_DRVP_FRPHY) | P_Fld(0xa, CA_TX_MCK_R_DMRESETB_DRVN_FRPHY));
8895
8896
8897 vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_RANK_SEL_LAT, P_Fld(0x3, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0) |
8898 P_Fld(0x3, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1) | P_Fld(0x3, MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA));
8899
8900 SetMck8xLowPwrOption(p);
8901 }
8902
8903 #define CKGEN_FMETER 0x0
8904 #define ABIST_FMETER 0x1
8905
FMeter(unsigned char u1CLKMeterSel,unsigned char u1CLKMuxSel)8906 static unsigned int FMeter(unsigned char u1CLKMeterSel, unsigned char u1CLKMuxSel)
8907 {
8908 #if (FOR_DV_SIMULATION_USED==0)
8909 unsigned int tmp, u4CalCnt;
8910
8911
8912 DRV_WriteReg32(CLK26CALI_0, (0x1 << 7));
8913
8914
8915 tmp = DRV_Reg32(CLK_DBG_CFG);
8916 tmp &= ~0x3;
8917
8918 if (u1CLKMeterSel == CKGEN_FMETER)
8919 tmp |= 0x1;
8920
8921 DRV_WriteReg32(CLK_DBG_CFG, tmp);
8922
8923
8924 tmp = DRV_Reg32(CLK_DBG_CFG);
8925
8926 if (u1CLKMeterSel == CKGEN_FMETER) {
8927 tmp &= ~(0xFF << 16);
8928 tmp |= u1CLKMuxSel << 16;
8929 } else {
8930 tmp &= ~(0x7F << 8);
8931 tmp |= u1CLKMuxSel << 8;
8932 }
8933
8934 DRV_WriteReg32(CLK_DBG_CFG, tmp);
8935
8936
8937 tmp = DRV_Reg32(CLK_MISC_CFG_0);
8938 tmp &= ~(0xFF << 24);
8939 DRV_WriteReg32(CLK_MISC_CFG_0, tmp);
8940
8941
8942 tmp = DRV_Reg32(CLK26CALI_1);
8943 tmp &= ~(0x3FF << 16);
8944 tmp |= 0x3FF << 16;
8945 DRV_WriteReg32(CLK26CALI_1, tmp);
8946
8947
8948 tmp = DRV_Reg32(CLK26CALI_0);
8949 tmp |= (0x1 << 4);
8950 DRV_WriteReg32(CLK26CALI_0, tmp);
8951
8952
8953 while (DRV_Reg32(CLK26CALI_0) & (0x1 << 4)) {
8954 mcDELAY_US(1);
8955 }
8956
8957
8958 u4CalCnt = DRV_Reg32(CLK26CALI_1) & 0xFFFF;
8959
8960
8961 tmp = DRV_Reg32(CLK26CALI_0);
8962 tmp &= ~(0x1 << 7);
8963 DRV_WriteReg32(CLK26CALI_0, tmp);
8964
8965 return ((u4CalCnt * 26) / 1024);
8966 #endif
8967 }
8968
DDRPhyFreqMeter(DRAMC_CTX_T * p)8969 unsigned int DDRPhyFreqMeter(DRAMC_CTX_T *p)
8970 {
8971
8972 #if (FOR_DV_SIMULATION_USED == 0)
8973
8974 unsigned int reg0=0;
8975 unsigned int backup_phypll = 0, backup_clrpll = 0;
8976 unsigned int before_value=0, after_value=0;
8977 unsigned int frq_result=0;
8978 unsigned int meter_value=0;
8979 U16 frqValue = 0;
8980
8981 #if 1
8982
8983
8984 reg0 = DRV_Reg32(Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x70c) ;
8985 backup_phypll = reg0;
8986 DRV_WriteReg32 (Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x70c , reg0 | (1 << 16));
8987 reg0 = DRV_Reg32(Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x72c) ;
8988 backup_clrpll = reg0;
8989 DRV_WriteReg32 (Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x72c , reg0 | (1 << 16));
8990
8991 mcDELAY_US(1);
8992
8993 frq_result = FMeter(ABIST_FMETER, 22);
8994 mcSHOW_DBG_MSG4(("AD_CLKSQ_FS26M_CK=%d MHz\n", frq_result));
8995
8996
8997 frq_result = FMeter(ABIST_FMETER, 30);
8998 mcSHOW_DBG_MSG4(("AD_MPLL_CK=%d MHz\n", frq_result));
8999
9000
9001 #if 1
9002 if((DRV_Reg32(Channel_A_DDRPHY_NAO_BASE_ADDRESS + 0x50c) & (1<<8))==0)
9003 {
9004
9005 //frq_result = FMeter(ABIST_FMETER, 119);
9006 //mcSHOW_DBG_MSG4(("AD_RCLRPLL_DIV4_CK_ch01 FREQ=%d MHz\n", frq_result));
9007
9008 }
9009 else
9010 {
9011
9012 //frq_result = FMeter(ABIST_FMETER, 120);
9013 //mcSHOW_DBG_MSG4(("AD_RPHYRPLL_DIV4_CK_ch01 FREQ=%d\n", frq_result));
9014
9015 }
9016 #endif
9017
9018 reg0 = DRV_Reg32(Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x504) ;
9019 DRV_WriteReg32 (Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x504 , reg0 | (1 << 11));
9020
9021
9022 before_value = FMeter(ABIST_FMETER, 118);
9023 mcSHOW_DBG_MSG4(("fmem_ck_bfe_dcm_ch0 FREQ=%d MHz\n", before_value));
9024
9025
9026
9027 after_value = FMeter(ABIST_FMETER, 117);
9028 mcSHOW_DBG_MSG4(("fmem_ck_aft_dcm_ch0 FREQ=%d MHz\n", after_value));
9029
9030
9031 //gddrphyfmeter_value = after_value << 2;
9032
9033 #if 0
9034 reg0 = DRV_Reg32(Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x70c) ;
9035 DRV_WriteReg32 (Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x70c , reg0 & ~(1 << 16));
9036 reg0 = DRV_Reg32(Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x72c) ;
9037 DRV_WriteReg32 (Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x72c , reg0 & ~(1 << 16));
9038 #else
9039 DRV_WriteReg32 (Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x70c , backup_phypll);
9040 DRV_WriteReg32 (Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x72c , backup_clrpll);
9041 #endif
9042
9043 #if (CHANNEL_NUM>2)
9044 if (channel_num_auxadc > 2) {
9045 reg0 = DRV_Reg32(Channel_C_DDRPHY_AO_BASE_ADDRESS + 0x70c) ;
9046 DRV_WriteReg32 (Channel_C_DDRPHY_AO_BASE_ADDRESS + 0x70c , reg0 | (1 << 16));
9047 reg0 = DRV_Reg32(Channel_C_DDRPHY_AO_BASE_ADDRESS + 0x72c) ;
9048 DRV_WriteReg32 (Channel_C_DDRPHY_AO_BASE_ADDRESS + 0x72c , reg0 | (1 << 16));
9049
9050 #if 1
9051 if((DRV_Reg32(Channel_C_DDRPHY_NAO_BASE_ADDRESS + 0x50c) & (1<<8))==0)
9052 {
9053
9054 //frq_result = FMeter(ABIST_FMETER, 116);
9055 //mcSHOW_DBG_MSG4(("AD_RCLRPLL_DIV4_CK_ch23 FREQ=%d MHz\n", frq_result));
9056
9057 }
9058 else
9059 {
9060
9061 //frq_result = FMeter(ABIST_FMETER, 115);
9062 //mcSHOW_DBG_MSG4(("AD_RPHYRPLL_DIV4_CK_ch23 FREQ=%d\n", frq_result));
9063
9064 }
9065 #endif
9066
9067 reg0 = DRV_Reg32(Channel_C_DDRPHY_AO_BASE_ADDRESS + 0x504) ;
9068 DRV_WriteReg32 (Channel_C_DDRPHY_AO_BASE_ADDRESS + 0x504 , reg0 | (1 << 11));
9069 reg0 = DRV_Reg32(Channel_D_DDRPHY_AO_BASE_ADDRESS + 0x504) ;
9070 DRV_WriteReg32 (Channel_D_DDRPHY_AO_BASE_ADDRESS + 0x504 , reg0 | (1 << 11));
9071
9072
9073 before_value = FMeter(ABIST_FMETER, 114);
9074 mcSHOW_DBG_MSG4(("fmem_ck_bfe_dcm_ch2 FREQ=%d MHz\n", before_value));
9075
9076
9077
9078 after_value = FMeter(ABIST_FMETER, 113);
9079 mcSHOW_DBG_MSG4(("fmem_ck_aft_dcm_ch2 FREQ=%d MHz\n", after_value));
9080
9081
9082 reg0 = DRV_Reg32(Channel_C_DDRPHY_AO_BASE_ADDRESS + 0x70c) ;
9083 DRV_WriteReg32 (Channel_C_DDRPHY_AO_BASE_ADDRESS + 0x70c , reg0 & ~(1 << 16));
9084 reg0 = DRV_Reg32(Channel_C_DDRPHY_AO_BASE_ADDRESS + 0x72c) ;
9085 DRV_WriteReg32 (Channel_C_DDRPHY_AO_BASE_ADDRESS + 0x72c , reg0 & ~(1 << 16));
9086 }
9087 #endif
9088
9089 meter_value = (before_value<<16 | after_value);
9090 #else
9091 mcSHOW_DBG_MSG3(("\n[PhyFreqMeter]\n"));
9092
9093 mcSHOW_DBG_MSG(("AD_MPLL_CK FREQ=%d\n", FMeter(ABIST_FMETER, 29)));
9094
9095
9096 mcSHOW_DBG_MSG(("AD_RCLRPLL_DIV4_CK_ch02 FREQ=%d\n", FMeter(ABIST_FMETER, 31)));
9097
9098
9099 mcSHOW_DBG_MSG(("AD_RCLRPLL_DIV4_CK_ch13 FREQ=%d\n", FMeter(ABIST_FMETER, 32)));
9100
9101
9102 mcSHOW_DBG_MSG(("AD_RPHYRPLL_DIV4_CK_ch02 FREQ=%d\n", FMeter(ABIST_FMETER, 33)));
9103
9104
9105 mcSHOW_DBG_MSG(("AD_RPHYRPLL_DIV4_CK_ch13 FREQ=%d\n", FMeter(ABIST_FMETER, 34)));
9106
9107
9108 reg0 = DRV_Reg32(Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x504) ;
9109 DRV_WriteReg32 (Channel_A_DDRPHY_AO_BASE_ADDRESS + 0x504 , reg0 | (1 << 11));
9110
9111 reg0 = DRV_Reg32(Channel_B_DDRPHY_AO_BASE_ADDRESS + 0x504) ;
9112 DRV_WriteReg32 (Channel_B_DDRPHY_AO_BASE_ADDRESS + 0x504 , reg0 | (1 << 11));
9113
9114 reg0 = DRV_Reg32(Channel_C_DDRPHY_AO_BASE_ADDRESS + 0x504) ;
9115 DRV_WriteReg32 (Channel_C_DDRPHY_AO_BASE_ADDRESS + 0x504 , reg0 | (1 << 11));
9116
9117 reg0 = DRV_Reg32(Channel_D_DDRPHY_AO_BASE_ADDRESS + 0x504) ;
9118 DRV_WriteReg32 (Channel_D_DDRPHY_AO_BASE_ADDRESS + 0x504 , reg0 | (1 << 11));
9119
9120
9121 before_value = FMeter(ABIST_FMETER, 44);
9122 mcSHOW_DBG_MSG(("fmem_ck_bfe_dcm_ch0 FREQ=%d\n", FMeter(ABIST_FMETER, 44)));
9123
9124
9125 before_value = FMeter(ABIST_FMETER, 45);
9126 mcSHOW_DBG_MSG(("fmem_ck_bfe_dcm_ch1 FREQ=%d\n", FMeter(ABIST_FMETER, 45)));
9127
9128
9129 before_value = FMeter(ABIST_FMETER, 46);
9130 mcSHOW_DBG_MSG(("fmem_ck_bfe_dcm_ch2 FREQ=%d\n", FMeter(ABIST_FMETER, 46)));
9131
9132
9133 before_value = FMeter(ABIST_FMETER, 47);
9134 mcSHOW_DBG_MSG(("fmem_ck_bfe_dcm_ch3 FREQ=%d\n", FMeter(ABIST_FMETER, 47)));
9135
9136 return 1;
9137 #if 0
9138 DRV_WriteReg32(DRAMC_CH0_TOP0_BASE + 0x2a0, reg0);
9139 DRV_WriteReg32(DRAMC_CH1_TOP0_BASE + 0x2a0, reg1);
9140
9141 return ((before_value<<16) | after_value);
9142 #endif
9143
9144 #endif
9145
9146 if(vGet_Div_Mode(p) == DIV8_MODE)
9147 {
9148 frqValue = (meter_value & 0xFFFF) << 2;
9149 }
9150 else if(vGet_Div_Mode(p) == DIV4_MODE)
9151 {
9152 frqValue = (meter_value & 0xFFFF) << 1;
9153 }
9154 else if(vGet_Div_Mode(p) == DIV16_MODE)
9155 {
9156 frqValue = (meter_value & 0xFFFF) << 4;
9157 }
9158 else
9159 {
9160 mcSHOW_ERR_MSG(("[DDRPhyFreqMeter] Get DIV mode error!\n"));
9161 #if __ETT__
9162 while (1);
9163 #endif
9164 }
9165
9166 return frqValue;
9167
9168 #endif
9169 }
9170