| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/PowerPC/ |
| D | PPCExpandAtomicPseudoInsts.cpp | 106 Register DstHi = TRI->getSubReg(Dst, PPC::sub_gp8_x0); in expandMI() local
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 575 unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi); in expandPseudoMTLoHi() local
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| D | MipsSEFrameLowering.cpp | 249 unsigned DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi); in expandCopyACC() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 734 Register DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi); in expandPseudoMTLoHi() local
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| D | MipsSEFrameLowering.cpp | 269 Register DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi); in expandCopyACC() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 748 Register DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi); in expandPseudoMTLoHi() local
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| D | MipsSEFrameLowering.cpp | 269 Register DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi); in expandCopyACC() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/GISel/ |
| D | AArch64LegalizerInfo.cpp | 1419 auto DstHi = MRI.createGenericVirtualRegister(s64); in legalizeAtomicCmpxchg128() local
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 859 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1); in expandPostRAPseudo() local
888 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1); in expandPostRAPseudo() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.cpp | 1604 unsigned DstHi = HRI.getSubReg(DstR, Hexagon::subreg_hireg); in expandLoadVec2() local
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| D | HexagonInstrInfo.cpp | 847 unsigned DstHi = HRI.getSubReg(DestReg, Hexagon::subreg_hireg); in copyPhysReg() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 348 Register DstHi = MRI->createVirtualRegister(&HalfRC); in selectG_ADD_SUB() local
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| D | SIInstrInfo.cpp | 1430 Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1); in expandPostRAPseudo() local
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| D | SIISelLowering.cpp | 3766 Register DstHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in EmitInstrWithCustomInserter() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.cpp | 1836 Register DstHi = HRI.getSubReg(DstR, Hexagon::vsub_hi); in expandLoadVec2() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.cpp | 1945 Register DstHi = HRI.getSubReg(DstR, Hexagon::vsub_hi); in expandLoadVec2() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 1947 Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1); in expandPostRAPseudo() local
2022 Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1); in expandPostRAPseudo() local
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| D | AMDGPURegisterBankInfo.cpp | 1592 Register DstHi; in applyMappingMAD_64_32() local
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| D | AMDGPUInstructionSelector.cpp | 364 Register DstHi = MRI->createVirtualRegister(&HalfRC); in selectG_ADD_SUB() local
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| D | SIISelLowering.cpp | 4285 Register DstHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in EmitInstrWithCustomInserter() local
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