| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/PowerPC/ |
| D | PPCExpandAtomicPseudoInsts.cpp | 107 Register DstLo = TRI->getSubReg(Dst, PPC::sub_gp8_x1); in expandMI() local
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 574 unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandPseudoMTLoHi() local
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| D | MipsSEFrameLowering.cpp | 248 unsigned DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo); in expandCopyACC() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 733 Register DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandPseudoMTLoHi() local
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| D | MipsSEFrameLowering.cpp | 268 Register DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo); in expandCopyACC() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 747 Register DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandPseudoMTLoHi() local
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| D | MipsSEFrameLowering.cpp | 268 Register DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo); in expandCopyACC() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/GISel/ |
| D | AArch64LegalizerInfo.cpp | 1418 auto DstLo = MRI.createGenericVirtualRegister(s64); in legalizeAtomicCmpxchg128() local
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 858 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0); in expandPostRAPseudo() local
887 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0); in expandPostRAPseudo() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.cpp | 1605 unsigned DstLo = HRI.getSubReg(DstR, Hexagon::subreg_loreg); in expandLoadVec2() local
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| D | HexagonInstrInfo.cpp | 850 unsigned DstLo = HRI.getSubReg(DestReg, Hexagon::subreg_loreg); in copyPhysReg() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 347 Register DstLo = MRI->createVirtualRegister(&HalfRC); in selectG_ADD_SUB() local
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| D | SIInstrInfo.cpp | 1429 Register DstLo = RI.getSubReg(Dst, AMDGPU::sub0); in expandPostRAPseudo() local
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| D | SIISelLowering.cpp | 3765 Register DstLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in EmitInstrWithCustomInserter() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.cpp | 1837 Register DstLo = HRI.getSubReg(DstR, Hexagon::vsub_lo); in expandLoadVec2() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.cpp | 1946 Register DstLo = HRI.getSubReg(DstR, Hexagon::vsub_lo); in expandLoadVec2() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 1946 Register DstLo = RI.getSubReg(Dst, AMDGPU::sub0); in expandPostRAPseudo() local
2021 Register DstLo = RI.getSubReg(Dst, AMDGPU::sub0); in expandPostRAPseudo() local
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| D | AMDGPURegisterBankInfo.cpp | 1593 Register DstLo = B.buildMul(S32, Src0, Src1).getReg(0); in applyMappingMAD_64_32() local
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| D | AMDGPUInstructionSelector.cpp | 363 Register DstLo = MRI->createVirtualRegister(&HalfRC); in selectG_ADD_SUB() local
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| D | SIISelLowering.cpp | 4284 Register DstLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in EmitInstrWithCustomInserter() local
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