1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __MAINBOARD_GOOGLE_OAK_GPIO_H__ 4 #define __MAINBOARD_GOOGLE_OAK_GPIO_H__ 5 #include <soc/gpio.h> 6 7 #define LID ((board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 7) ? \ 8 GPIO(EINT12) : GPIO(SPI_CK)) 9 #define RAM_ID_1 GPIO(RCN_A) 10 #define RAM_ID_2 GPIO(RCP_A) 11 12 /* Board ID related GPIOS. */ 13 #define BOARD_ID_0 GPIO(RDN3_A) 14 #define BOARD_ID_1 GPIO(RDP3_A) 15 #define BOARD_ID_2 GPIO(RDN2_A) 16 /* RAM ID related GPIOS. */ 17 #define RAM_ID_0 GPIO(RDP2_A) 18 #define RAM_ID_3 GPIO(RDN1_A) 19 /* Write Protect */ 20 #define WRITE_PROTECT GPIO(EINT4) 21 /* Power button */ 22 #define POWER_BUTTON GPIO(EINT14) 23 /* EC Interrupt */ 24 #define EC_IRQ GPIO(EINT0) 25 /* EC in RW signal */ 26 #define EC_IN_RW GPIO(DAIPCMIN) 27 /* EC AP suspend */ 28 #define EC_SUSPEND_L GPIO(KPROW1) 29 /* Cr50 interrupt */ 30 #define CR50_IRQ GPIO(EINT16) 31 32 void setup_chromeos_gpios(void); 33 34 #endif /* __MAINBOARD_GOOGLE_OAK_GPIO_H__ */ 35