1 /* 2 ************************************************************************************************************************ 3 * 4 * Copyright (C) 2007-2024 Advanced Micro Devices, Inc. All rights reserved. 5 * SPDX-License-Identifier: MIT 6 * 7 ***********************************************************************************************************************/ 8 9 /** 10 **************************************************************************************************** 11 * @file addrinterface.h 12 * @brief Contains the addrlib interfaces declaration and parameter defines 13 **************************************************************************************************** 14 */ 15 #ifndef __ADDR_INTERFACE_H__ 16 #define __ADDR_INTERFACE_H__ 17 18 // Includes should be before extern "C" 19 #include "addrtypes.h" 20 21 #if defined(__cplusplus) 22 extern "C" 23 { 24 #endif 25 26 #define ADDRLIB_VERSION_MAJOR 10 27 #define ADDRLIB_VERSION_MINOR 1 28 #define ADDRLIB_MAKE_VERSION(major, minor) ((major << 16) | minor) 29 #define ADDRLIB_VERSION ADDRLIB_MAKE_VERSION(ADDRLIB_VERSION_MAJOR, ADDRLIB_VERSION_MINOR) 30 31 /// Virtually all interface functions need ADDR_HANDLE as first parameter 32 typedef VOID* ADDR_HANDLE; 33 34 /// Client handle used in callbacks 35 typedef VOID* ADDR_CLIENT_HANDLE; 36 37 typedef struct _ADDR_COORD2D 38 { 39 UINT_32 x; 40 UINT_32 y; 41 } ADDR_COORD2D; 42 43 typedef struct _ADDR_COORD3D 44 { 45 UINT_32 x; 46 UINT_32 y; 47 UINT_32 z; // also slices for 2D images 48 } ADDR_COORD3D; 49 50 typedef struct _ADDR_EXTENT2D 51 { 52 UINT_32 width; 53 UINT_32 height; 54 } ADDR_EXTENT2D; 55 56 typedef struct _ADDR_EXTENT3D 57 { 58 UINT_32 width; 59 UINT_32 height; 60 UINT_32 depth; // also slices for 2D images 61 } ADDR_EXTENT3D; 62 63 /** 64 * ///////////////////////////////////////////////////////////////////////////////////////////////// 65 * // Callback functions 66 * ///////////////////////////////////////////////////////////////////////////////////////////////// 67 * typedef VOID* (ADDR_API* ADDR_ALLOCSYSMEM)( 68 * const ADDR_ALLOCSYSMEM_INPUT* pInput); 69 * typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_FREESYSMEM)( 70 * VOID* pVirtAddr); 71 * typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_DEBUGPRINT)( 72 * const ADDR_DEBUGPRINT_INPUT* pInput); 73 * 74 **/ 75 /** 76 * ///////////////////////////////////////////////////////////////////////////////////////////////// 77 * // Create/Destroy/Config functions 78 * ///////////////////////////////////////////////////////////////////////////////////////////////// 79 * AddrCreate() 80 * AddrDestroy() 81 * 82 * ///////////////////////////////////////////////////////////////////////////////////////////////// 83 * // Surface functions 84 * ///////////////////////////////////////////////////////////////////////////////////////////////// 85 * AddrComputeSurfaceInfo() 86 * AddrComputeSurfaceAddrFromCoord() 87 * AddrComputeSurfaceCoordFromAddr() 88 * 89 * ///////////////////////////////////////////////////////////////////////////////////////////////// 90 * // HTile functions 91 * ///////////////////////////////////////////////////////////////////////////////////////////////// 92 * AddrComputeHtileInfo() 93 * AddrComputeHtileAddrFromCoord() 94 * AddrComputeHtileCoordFromAddr() 95 * 96 * ///////////////////////////////////////////////////////////////////////////////////////////////// 97 * // C-mask functions 98 * ///////////////////////////////////////////////////////////////////////////////////////////////// 99 * AddrComputeCmaskInfo() 100 * AddrComputeCmaskAddrFromCoord() 101 * AddrComputeCmaskCoordFromAddr() 102 * 103 * ///////////////////////////////////////////////////////////////////////////////////////////////// 104 * // F-mask functions 105 * ///////////////////////////////////////////////////////////////////////////////////////////////// 106 * AddrComputeFmaskInfo() 107 * AddrComputeFmaskAddrFromCoord() 108 * AddrComputeFmaskCoordFromAddr() 109 * 110 **/ 111 /** 112 * ///////////////////////////////////////////////////////////////////////////////////////////////// 113 * // Element/Utility functions 114 * ///////////////////////////////////////////////////////////////////////////////////////////////// 115 * ElemFlt32ToDepthPixel() 116 * ElemFlt32ToColorPixel() 117 **/ 118 /** 119 * AddrExtractBankPipeSwizzle() 120 * AddrCombineBankPipeSwizzle() 121 * AddrComputeSliceSwizzle() 122 * AddrConvertTileInfoToHW() 123 * AddrConvertTileIndex() 124 * AddrConvertTileIndex1() 125 * AddrGetTileIndex() 126 * AddrComputeBaseSwizzle() 127 * AddrUseTileIndex() 128 * AddrUseCombinedSwizzle() 129 * 130 **/ 131 132 //////////////////////////////////////////////////////////////////////////////////////////////////// 133 // Callback functions 134 //////////////////////////////////////////////////////////////////////////////////////////////////// 135 136 /** 137 **************************************************************************************************** 138 * @brief channel setting structure 139 **************************************************************************************************** 140 */ 141 typedef union _ADDR_CHANNEL_SETTING 142 { 143 struct 144 { 145 UINT_8 valid : 1; ///< Indicate whehter this channel setting is valid 146 UINT_8 channel : 2; ///< 0 for x channel, 1 for y channel, 2 for z channel, 3 for MSAA sample index 147 UINT_8 index : 5; ///< Channel index 148 }; 149 UINT_8 value; ///< Value 150 } ADDR_CHANNEL_SETTING; 151 152 /** 153 **************************************************************************************************** 154 * @brief address equation key structure 155 **************************************************************************************************** 156 */ 157 typedef union _ADDR_EQUATION_KEY 158 { 159 struct 160 { 161 UINT_32 log2ElementBytes : 3; ///< Log2 of Bytes per pixel 162 UINT_32 tileMode : 5; ///< Tile mode 163 UINT_32 microTileType : 3; ///< Micro tile type 164 UINT_32 pipeConfig : 5; ///< pipe config 165 UINT_32 numBanksLog2 : 3; ///< Number of banks log2 166 UINT_32 bankWidth : 4; ///< Bank width 167 UINT_32 bankHeight : 4; ///< Bank height 168 UINT_32 macroAspectRatio : 3; ///< Macro tile aspect ratio 169 UINT_32 prt : 1; ///< SI only, indicate whether this equation is for prt 170 UINT_32 reserved : 1; ///< Reserved bit 171 } fields; 172 UINT_32 value; 173 } ADDR_EQUATION_KEY; 174 175 /** 176 **************************************************************************************************** 177 * @brief address equation structure 178 **************************************************************************************************** 179 */ 180 #define ADDR_MAX_LEGACY_EQUATION_COMP 3u 181 #define ADDR_MAX_EQUATION_COMP 5u 182 #define ADDR_MAX_EQUATION_BIT 20u 183 184 // Invalid equation index 185 #define ADDR_INVALID_EQUATION_INDEX 0xFFFFFFFF 186 187 typedef struct _ADDR_EQUATION 188 { 189 union 190 { 191 struct { 192 ADDR_CHANNEL_SETTING addr[ADDR_MAX_EQUATION_BIT]; ///< addr setting 193 ADDR_CHANNEL_SETTING xor1[ADDR_MAX_EQUATION_BIT]; ///< xor setting 194 ADDR_CHANNEL_SETTING xor2[ADDR_MAX_EQUATION_BIT]; ///< xor2 setting 195 ADDR_CHANNEL_SETTING xor3[ADDR_MAX_EQUATION_BIT]; ///< xor3 setting 196 ADDR_CHANNEL_SETTING xor4[ADDR_MAX_EQUATION_BIT]; ///< xor4 setting 197 }; 198 ///< Components showing the sources of each bit; each bit is result of addr ^ xor ^ xor2... 199 ADDR_CHANNEL_SETTING comps[ADDR_MAX_EQUATION_COMP][ADDR_MAX_EQUATION_BIT]; 200 }; 201 UINT_32 numBits; ///< The number of bits in equation 202 UINT_32 numBitComponents; ///< The max number of channels contributing to a bit 203 BOOL_32 stackedDepthSlices; ///< TRUE if depth slices are treated as being 204 ///< stacked vertically prior to swizzling 205 } ADDR_EQUATION; 206 207 208 /** 209 **************************************************************************************************** 210 * @brief Alloc system memory flags. 211 * @note These flags are reserved for future use and if flags are added will minimize the impact 212 * of the client. 213 **************************************************************************************************** 214 */ 215 typedef union _ADDR_ALLOCSYSMEM_FLAGS 216 { 217 struct 218 { 219 UINT_32 reserved : 32; ///< Reserved for future use. 220 } fields; 221 UINT_32 value; 222 223 } ADDR_ALLOCSYSMEM_FLAGS; 224 225 /** 226 **************************************************************************************************** 227 * @brief Alloc system memory input structure 228 **************************************************************************************************** 229 */ 230 typedef struct _ADDR_ALLOCSYSMEM_INPUT 231 { 232 UINT_32 size; ///< Size of this structure in bytes 233 234 ADDR_ALLOCSYSMEM_FLAGS flags; ///< System memory flags. 235 UINT_32 sizeInBytes; ///< System memory allocation size in bytes. 236 ADDR_CLIENT_HANDLE hClient; ///< Client handle 237 } ADDR_ALLOCSYSMEM_INPUT; 238 239 /** 240 **************************************************************************************************** 241 * ADDR_ALLOCSYSMEM 242 * @brief 243 * Allocate system memory callback function. Returns valid pointer on success. 244 **************************************************************************************************** 245 */ 246 typedef VOID* (ADDR_API* ADDR_ALLOCSYSMEM)( 247 const ADDR_ALLOCSYSMEM_INPUT* pInput); 248 249 /** 250 **************************************************************************************************** 251 * @brief Free system memory input structure 252 **************************************************************************************************** 253 */ 254 typedef struct _ADDR_FREESYSMEM_INPUT 255 { 256 UINT_32 size; ///< Size of this structure in bytes 257 258 VOID* pVirtAddr; ///< Virtual address 259 ADDR_CLIENT_HANDLE hClient; ///< Client handle 260 } ADDR_FREESYSMEM_INPUT; 261 262 /** 263 **************************************************************************************************** 264 * ADDR_FREESYSMEM 265 * @brief 266 * Free system memory callback function. 267 * Returns ADDR_OK on success. 268 **************************************************************************************************** 269 */ 270 typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_FREESYSMEM)( 271 const ADDR_FREESYSMEM_INPUT* pInput); 272 273 /** 274 **************************************************************************************************** 275 * @brief Print debug message input structure 276 **************************************************************************************************** 277 */ 278 typedef struct _ADDR_DEBUGPRINT_INPUT 279 { 280 UINT_32 size; ///< Size of this structure in bytes 281 282 CHAR* pDebugString; ///< Debug print string 283 va_list ap; ///< Variable argument list 284 ADDR_CLIENT_HANDLE hClient; ///< Client handle 285 } ADDR_DEBUGPRINT_INPUT; 286 287 /** 288 **************************************************************************************************** 289 * ADDR_DEBUGPRINT 290 * @brief 291 * Print debug message callback function. 292 * Returns ADDR_OK on success. 293 **************************************************************************************************** 294 */ 295 typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_DEBUGPRINT)( 296 const ADDR_DEBUGPRINT_INPUT* pInput); 297 298 /** 299 **************************************************************************************************** 300 * ADDR_CALLBACKS 301 * 302 * @brief 303 * Address Library needs client to provide system memory alloc/free routines. 304 **************************************************************************************************** 305 */ 306 typedef struct _ADDR_CALLBACKS 307 { 308 ADDR_ALLOCSYSMEM allocSysMem; ///< Routine to allocate system memory 309 ADDR_FREESYSMEM freeSysMem; ///< Routine to free system memory 310 ADDR_DEBUGPRINT debugPrint; ///< Routine to print debug message 311 } ADDR_CALLBACKS; 312 313 //////////////////////////////////////////////////////////////////////////////////////////////////// 314 // Create/Destroy functions 315 //////////////////////////////////////////////////////////////////////////////////////////////////// 316 317 /** 318 **************************************************************************************************** 319 * ADDR_CREATE_FLAGS 320 * 321 * @brief 322 * This structure is used to pass some setup in creation of AddrLib 323 * @note 324 **************************************************************************************************** 325 */ 326 typedef union _ADDR_CREATE_FLAGS 327 { 328 struct 329 { 330 UINT_32 noCubeMipSlicesPad : 1; ///< Turn cubemap faces padding off 331 UINT_32 fillSizeFields : 1; ///< If clients fill size fields in all input and 332 /// output structure 333 UINT_32 useTileIndex : 1; ///< Make tileIndex field in input valid 334 UINT_32 useCombinedSwizzle : 1; ///< Use combined tile swizzle 335 UINT_32 checkLast2DLevel : 1; ///< Check the last 2D mip sub level 336 UINT_32 useHtileSliceAlign : 1; ///< Do htile single slice alignment 337 UINT_32 allowLargeThickTile : 1; ///< Allow 64*thickness*bytesPerPixel > rowSize 338 UINT_32 forceDccAndTcCompat : 1; ///< Force enable DCC and TC compatibility 339 UINT_32 nonPower2MemConfig : 1; ///< Video memory bit width is not power of 2 340 UINT_32 enableAltTiling : 1; ///< Enable alt tile mode 341 UINT_32 reserved : 22; ///< Reserved bits for future use 342 }; 343 344 UINT_32 value; 345 } ADDR_CREATE_FLAGS; 346 347 /** 348 **************************************************************************************************** 349 * ADDR_REGISTER_VALUE 350 * 351 * @brief 352 * Data from registers to setup AddrLib global data, used in AddrCreate 353 **************************************************************************************************** 354 */ 355 typedef struct _ADDR_REGISTER_VALUE 356 { 357 UINT_32 gbAddrConfig; ///< For R8xx, use GB_ADDR_CONFIG register value. 358 /// For R6xx/R7xx, use GB_TILING_CONFIG. 359 /// But they can be treated as the same. 360 /// if this value is 0, use chip to set default value 361 UINT_32 backendDisables; ///< 1 bit per backend, starting with LSB. 1=disabled,0=enabled. 362 /// Register value of CC_RB_BACKEND_DISABLE.BACKEND_DISABLE 363 364 /// R800 registers----------------------------------------------- 365 UINT_32 noOfBanks; ///< Number of h/w ram banks - For r800: MC_ARB_RAMCFG.NOOFBANK 366 /// No enums for this value in h/w header files 367 /// 0: 4 368 /// 1: 8 369 /// 2: 16 370 UINT_32 noOfRanks; /// MC_ARB_RAMCFG.NOOFRANK 371 /// 0: 1 372 /// 1: 2 373 /// SI (R1000) registers----------------------------------------- 374 const UINT_32* pTileConfig; ///< Global tile setting tables 375 UINT_32 noOfEntries; ///< Number of entries in pTileConfig 376 377 ///< CI registers------------------------------------------------- 378 const UINT_32* pMacroTileConfig; ///< Global macro tile mode table 379 UINT_32 noOfMacroEntries; ///< Number of entries in pMacroTileConfig 380 } ADDR_REGISTER_VALUE; 381 382 /** 383 **************************************************************************************************** 384 * ADDR_CREATE_INPUT 385 * 386 * @brief 387 * Parameters use to create an AddrLib Object. Caller must provide all fields. 388 * 389 **************************************************************************************************** 390 */ 391 typedef struct _ADDR_CREATE_INPUT 392 { 393 UINT_32 size; ///< Size of this structure in bytes 394 395 UINT_32 chipEngine; ///< Chip Engine 396 UINT_32 chipFamily; ///< Chip Family 397 UINT_32 chipRevision; ///< Chip Revision 398 ADDR_CALLBACKS callbacks; ///< Callbacks for sysmem alloc/free/print 399 ADDR_CREATE_FLAGS createFlags; ///< Flags to setup AddrLib 400 ADDR_REGISTER_VALUE regValue; ///< Data from registers to setup AddrLib global data 401 ADDR_CLIENT_HANDLE hClient; ///< Client handle 402 UINT_32 minPitchAlignPixels; ///< Minimum pitch alignment in pixels 403 } ADDR_CREATE_INPUT; 404 405 /** 406 **************************************************************************************************** 407 * ADDR_CREATEINFO_OUTPUT 408 * 409 * @brief 410 * Return AddrLib handle to client driver 411 * 412 **************************************************************************************************** 413 */ 414 typedef struct _ADDR_CREATE_OUTPUT 415 { 416 UINT_32 size; ///< Size of this structure in bytes 417 418 ADDR_HANDLE hLib; ///< Address lib handle 419 420 UINT_32 numEquations; ///< Number of equations in the table 421 const ADDR_EQUATION* pEquationTable; ///< Pointer to the equation table 422 } ADDR_CREATE_OUTPUT; 423 424 /** 425 **************************************************************************************************** 426 * AddrCreate 427 * 428 * @brief 429 * Create AddrLib object, must be called before any interface calls 430 * 431 * @return 432 * ADDR_OK if successful 433 **************************************************************************************************** 434 */ 435 ADDR_E_RETURNCODE ADDR_API AddrCreate( 436 const ADDR_CREATE_INPUT* pAddrCreateIn, 437 ADDR_CREATE_OUTPUT* pAddrCreateOut); 438 439 440 441 /** 442 **************************************************************************************************** 443 * AddrDestroy 444 * 445 * @brief 446 * Destroy AddrLib object, must be called to free internally allocated resources. 447 * 448 * @return 449 * ADDR_OK if successful 450 **************************************************************************************************** 451 */ 452 ADDR_E_RETURNCODE ADDR_API AddrDestroy( 453 ADDR_HANDLE hLib); 454 455 456 //////////////////////////////////////////////////////////////////////////////////////////////////// 457 // Surface functions 458 //////////////////////////////////////////////////////////////////////////////////////////////////// 459 460 /** 461 **************************************************************************************************** 462 * @brief 463 * Bank/tiling parameters. On function input, these can be set as desired or 464 * left 0 for AddrLib to calculate/default. On function output, these are the actual 465 * parameters used. 466 * @note 467 * Valid bankWidth/bankHeight value: 468 * 1,2,4,8. They are factors instead of pixels or bytes. 469 * 470 * The bank number remains constant across each row of the 471 * macro tile as each pipe is selected, so the number of 472 * tiles in the x direction with the same bank number will 473 * be bank_width * num_pipes. 474 **************************************************************************************************** 475 */ 476 typedef struct _ADDR_TILEINFO 477 { 478 /// Any of these parameters can be set to 0 to use the HW default. 479 UINT_32 banks; ///< Number of banks, numerical value 480 UINT_32 bankWidth; ///< Number of tiles in the X direction in the same bank 481 UINT_32 bankHeight; ///< Number of tiles in the Y direction in the same bank 482 UINT_32 macroAspectRatio; ///< Macro tile aspect ratio. 1-1:1, 2-4:1, 4-16:1, 8-64:1 483 UINT_32 tileSplitBytes; ///< Tile split size, in bytes 484 AddrPipeCfg pipeConfig; ///< Pipe Config = HW enum + 1 485 } ADDR_TILEINFO; 486 487 // Create a define to avoid client change. The removal of R800 is because we plan to implement SI 488 // within 800 HWL - An AddrPipeCfg is added in above data structure 489 typedef ADDR_TILEINFO ADDR_R800_TILEINFO; 490 491 /** 492 **************************************************************************************************** 493 * @brief 494 * Information needed by quad buffer stereo support 495 **************************************************************************************************** 496 */ 497 typedef struct _ADDR_QBSTEREOINFO 498 { 499 UINT_32 eyeHeight; ///< Height (in pixel rows) to right eye 500 UINT_32 rightOffset; ///< Offset (in bytes) to right eye 501 UINT_32 rightSwizzle; ///< TileSwizzle for right eyes 502 } ADDR_QBSTEREOINFO; 503 504 /** 505 **************************************************************************************************** 506 * ADDR_SURFACE_FLAGS 507 * 508 * @brief 509 * Surface flags 510 **************************************************************************************************** 511 */ 512 typedef union _ADDR_SURFACE_FLAGS 513 { 514 struct 515 { 516 UINT_32 color : 1; ///< Flag indicates this is a color buffer 517 UINT_32 depth : 1; ///< Flag indicates this is a depth/stencil buffer 518 UINT_32 stencil : 1; ///< Flag indicates this is a stencil buffer 519 UINT_32 texture : 1; ///< Flag indicates this is a texture 520 UINT_32 cube : 1; ///< Flag indicates this is a cubemap 521 UINT_32 volume : 1; ///< Flag indicates this is a volume texture 522 UINT_32 fmask : 1; ///< Flag indicates this is an fmask 523 UINT_32 cubeAsArray : 1; ///< Flag indicates if treat cubemap as arrays 524 UINT_32 compressZ : 1; ///< Flag indicates z buffer is compressed 525 UINT_32 overlay : 1; ///< Flag indicates this is an overlay surface 526 UINT_32 noStencil : 1; ///< Flag indicates this depth has no separate stencil 527 UINT_32 display : 1; ///< Flag indicates this should match display controller req. 528 UINT_32 opt4Space : 1; ///< Flag indicates this surface should be optimized for space 529 /// i.e. save some memory but may lose performance 530 UINT_32 prt : 1; ///< Flag for partially resident texture 531 UINT_32 qbStereo : 1; ///< Quad buffer stereo surface 532 UINT_32 pow2Pad : 1; ///< SI: Pad to pow2, must set for mipmap (include level0) 533 UINT_32 interleaved : 1; ///< Special flag for interleaved YUV surface padding 534 UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable 535 UINT_32 dispTileType : 1; ///< NI: force display Tiling for 128 bit shared resoruce 536 UINT_32 dccCompatible : 1; ///< VI: whether to make MSAA surface support dcc fast clear 537 UINT_32 dccPipeWorkaround : 1; ///< VI: whether to workaround the HW limit that 538 /// dcc can't be enabled if pipe config of tile mode 539 /// is different from that of ASIC, this flag 540 /// is address lib internal flag, client should ignore it 541 UINT_32 czDispCompatible : 1; ///< SI+: CZ family has a HW bug needs special alignment. 542 /// This flag indicates we need to follow the 543 /// alignment with CZ families or other ASICs under 544 /// PX configuration + CZ. 545 UINT_32 nonSplit : 1; ///< CI: depth texture should not be split 546 UINT_32 disableLinearOpt : 1; ///< Disable tile mode optimization to linear 547 UINT_32 needEquation : 1; ///< Make the surface tile setting equation compatible. 548 /// This flag indicates we need to override tile 549 /// mode to PRT_* tile mode to disable slice rotation, 550 /// which is needed by swizzle pattern equation. 551 UINT_32 skipIndicesOutput : 1; ///< Skipping indices in output. 552 UINT_32 rotateDisplay : 1; ///< Rotate micro tile type 553 UINT_32 minimizeAlignment : 1; ///< Minimize alignment 554 UINT_32 preferEquation : 1; ///< Return equation index without adjusting tile mode 555 UINT_32 matchStencilTileCfg : 1; ///< Select tile index of stencil as well as depth surface 556 /// to make sure they share same tile config parameters 557 UINT_32 disallowLargeThickDegrade : 1; ///< Disallow large thick tile degrade 558 UINT_32 reserved : 1; ///< Reserved bits 559 }; 560 561 UINT_32 value; 562 } ADDR_SURFACE_FLAGS; 563 564 /** 565 **************************************************************************************************** 566 * ADDR_COMPUTE_SURFACE_INFO_INPUT 567 * 568 * @brief 569 * Input structure for AddrComputeSurfaceInfo 570 **************************************************************************************************** 571 */ 572 typedef struct _ADDR_COMPUTE_SURFACE_INFO_INPUT 573 { 574 UINT_32 size; ///< Size of this structure in bytes 575 576 AddrTileMode tileMode; ///< Tile mode 577 AddrFormat format; ///< If format is set to valid one, bpp/width/height 578 /// might be overwritten 579 UINT_32 bpp; ///< Bits per pixel 580 UINT_32 numSamples; ///< Number of samples 581 UINT_32 width; ///< Width, in pixels 582 UINT_32 height; ///< Height, in pixels 583 UINT_32 numSlices; ///< Number of surface slices or depth 584 UINT_32 slice; ///< Slice index 585 UINT_32 mipLevel; ///< Current mipmap level 586 UINT_32 numMipLevels; ///< Number of mips in mip chain 587 ADDR_SURFACE_FLAGS flags; ///< Surface type flags 588 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 589 /// number of samples for normal AA; Set it to the 590 /// number of fragments for EQAA 591 /// r800 and later HWL parameters 592 // Needed by 2D tiling, for linear and 1D tiling, just keep them 0's 593 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Set to 0 to default/calculate 594 AddrTileType tileType; ///< Micro tiling type, not needed when tileIndex != -1 595 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 596 /// while the global useTileIndex is set to 1 597 UINT_32 basePitch; ///< Base level pitch in pixels, 0 means ignored, is a 598 /// must for mip levels from SI+. 599 /// Don't use pitch in blocks for compressed formats! 600 UINT_32 maxBaseAlign; ///< Max base alignment request from client 601 UINT_32 pitchAlign; ///< Pitch alignment request from client 602 UINT_32 heightAlign; ///< Height alignment request from client 603 } ADDR_COMPUTE_SURFACE_INFO_INPUT; 604 605 /** 606 **************************************************************************************************** 607 * ADDR_COMPUTE_SURFACE_INFO_OUTPUT 608 * 609 * @brief 610 * Output structure for AddrComputeSurfInfo 611 * @note 612 Element: AddrLib unit for computing. e.g. BCn: 4x4 blocks; R32B32B32: 32bit with 3x pitch 613 Pixel: Original pixel 614 **************************************************************************************************** 615 */ 616 typedef struct _ADDR_COMPUTE_SURFACE_INFO_OUTPUT 617 { 618 UINT_32 size; ///< Size of this structure in bytes 619 620 UINT_32 pitch; ///< Pitch in elements (in blocks for compressed formats) 621 UINT_32 height; ///< Height in elements (in blocks for compressed formats) 622 UINT_32 depth; ///< Number of slice/depth 623 UINT_64 surfSize; ///< Surface size in bytes 624 AddrTileMode tileMode; ///< Actual tile mode. May differ from that in input 625 UINT_32 baseAlign; ///< Base address alignment 626 UINT_32 pitchAlign; ///< Pitch alignment, in elements 627 UINT_32 heightAlign; ///< Height alignment, in elements 628 UINT_32 depthAlign; ///< Depth alignment, aligned to thickness, for 3d texture 629 UINT_32 bpp; ///< Bits per elements (e.g. blocks for BCn, 1/3 for 96bit) 630 UINT_32 pixelPitch; ///< Pitch in original pixels 631 UINT_32 pixelHeight; ///< Height in original pixels 632 UINT_32 pixelBits; ///< Original bits per pixel, passed from input 633 UINT_64 sliceSize; ///< Size of slice specified by input's slice 634 /// The result is controlled by surface flags & createFlags 635 /// By default this value equals to surfSize for volume 636 UINT_32 pitchTileMax; ///< PITCH_TILE_MAX value for h/w register 637 UINT_32 heightTileMax; ///< HEIGHT_TILE_MAX value for h/w register 638 UINT_32 sliceTileMax; ///< SLICE_TILE_MAX value for h/w register 639 640 UINT_32 numSamples; ///< Pass the effective numSamples processed in this call 641 642 /// r800 and later HWL parameters 643 ADDR_TILEINFO* pTileInfo; ///< Tile parameters used. Filled in if 0 on input 644 AddrTileType tileType; ///< Micro tiling type, only valid when tileIndex != -1 645 INT_32 tileIndex; ///< Tile index, MAY be "downgraded" 646 647 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 648 /// Output flags 649 struct 650 { 651 /// Special information to work around SI mipmap swizzle bug UBTS #317508 652 UINT_32 last2DLevel : 1; ///< TRUE if this is the last 2D(3D) tiled 653 ///< Only meaningful when create flag checkLast2DLevel is set 654 UINT_32 tcCompatible : 1; ///< If the surface can be shader compatible 655 UINT_32 dccUnsupport : 1; ///< If the surface can support DCC compressed rendering 656 UINT_32 prtTileIndex : 1; ///< SI only, indicate the returned tile index is for PRT 657 ///< If address lib return true for mip 0, client should set prt flag 658 ///< for child mips in subsequent compute surface info calls 659 UINT_32 reserved :28; ///< Reserved bits 660 }; 661 662 UINT_32 equationIndex; ///< Equation index in the equation table; 663 664 UINT_32 blockWidth; ///< Width in element inside one block(1D->Micro, 2D->Macro) 665 UINT_32 blockHeight; ///< Height in element inside one block(1D->Micro, 2D->Macro) 666 UINT_32 blockSlices; ///< Slice number inside one block(1D->Micro, 2D->Macro) 667 668 /// Stereo info 669 ADDR_QBSTEREOINFO* pStereoInfo;///< Stereo information, needed when .qbStereo flag is TRUE 670 671 INT_32 stencilTileIdx; ///< stencil tile index output when matchStencilTileCfg was set 672 } ADDR_COMPUTE_SURFACE_INFO_OUTPUT; 673 674 /** 675 **************************************************************************************************** 676 * AddrComputeSurfaceInfo 677 * 678 * @brief 679 * Compute surface width/height/depth/alignments and suitable tiling mode 680 **************************************************************************************************** 681 */ 682 ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceInfo( 683 ADDR_HANDLE hLib, 684 const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, 685 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut); 686 687 688 689 /** 690 **************************************************************************************************** 691 * ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT 692 * 693 * @brief 694 * Input structure for AddrComputeSurfaceAddrFromCoord 695 **************************************************************************************************** 696 */ 697 typedef struct _ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT 698 { 699 UINT_32 size; ///< Size of this structure in bytes 700 701 UINT_32 x; ///< X coordinate 702 UINT_32 y; ///< Y coordinate 703 UINT_32 slice; ///< Slice index 704 UINT_32 sample; ///< Sample index, use fragment index for EQAA 705 706 UINT_32 bpp; ///< Bits per pixel 707 UINT_32 pitch; ///< Surface pitch, in pixels 708 UINT_32 height; ///< Surface height, in pixels 709 UINT_32 numSlices; ///< Surface depth 710 UINT_32 numSamples; ///< Number of samples 711 712 AddrTileMode tileMode; ///< Tile mode 713 BOOL_32 isDepth; ///< TRUE if the surface uses depth sample ordering within 714 /// micro tile. Textures can also choose depth sample order 715 UINT_32 tileBase; ///< Base offset (in bits) inside micro tile which handles 716 /// the case that components are stored separately 717 UINT_32 compBits; ///< The component bits actually needed(for planar surface) 718 719 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 720 /// number of samples for normal AA; Set it to the 721 /// number of fragments for EQAA 722 /// r800 and later HWL parameters 723 // Used for 1D tiling above 724 AddrTileType tileType; ///< See defintion of AddrTileType 725 struct 726 { 727 UINT_32 ignoreSE : 1; ///< TRUE if shader engines are ignored. This is texture 728 /// only flag. Only non-RT texture can set this to TRUE 729 UINT_32 reserved :31; ///< Reserved for future use. 730 }; 731 // 2D tiling needs following structure 732 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data 733 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 734 /// while the global useTileIndex is set to 1 735 union 736 { 737 struct 738 { 739 UINT_32 bankSwizzle; ///< Bank swizzle 740 UINT_32 pipeSwizzle; ///< Pipe swizzle 741 }; 742 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE 743 }; 744 } ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT; 745 746 /** 747 **************************************************************************************************** 748 * ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT 749 * 750 * @brief 751 * Output structure for AddrComputeSurfaceAddrFromCoord 752 **************************************************************************************************** 753 */ 754 typedef struct _ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT 755 { 756 UINT_32 size; ///< Size of this structure in bytes 757 758 UINT_64 addr; ///< Byte address 759 UINT_32 bitPosition; ///< Bit position within surfaceAddr, 0-7. 760 /// For surface bpp < 8, e.g. FMT_1. 761 UINT_32 prtBlockIndex; ///< Index of a PRT tile (64K block) 762 } ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT; 763 764 /** 765 **************************************************************************************************** 766 * AddrComputeSurfaceAddrFromCoord 767 * 768 * @brief 769 * Compute surface address from a given coordinate. 770 **************************************************************************************************** 771 */ 772 ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceAddrFromCoord( 773 ADDR_HANDLE hLib, 774 const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 775 ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut); 776 777 778 779 /** 780 **************************************************************************************************** 781 * ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT 782 * 783 * @brief 784 * Input structure for AddrComputeSurfaceCoordFromAddr 785 **************************************************************************************************** 786 */ 787 typedef struct _ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT 788 { 789 UINT_32 size; ///< Size of this structure in bytes 790 791 UINT_64 addr; ///< Address in bytes 792 UINT_32 bitPosition; ///< Bit position in addr. 0-7. for surface bpp < 8, 793 /// e.g. FMT_1; 794 UINT_32 bpp; ///< Bits per pixel 795 UINT_32 pitch; ///< Pitch, in pixels 796 UINT_32 height; ///< Height in pixels 797 UINT_32 numSlices; ///< Surface depth 798 UINT_32 numSamples; ///< Number of samples 799 800 AddrTileMode tileMode; ///< Tile mode 801 BOOL_32 isDepth; ///< Surface uses depth sample ordering within micro tile. 802 /// Note: Textures can choose depth sample order as well. 803 UINT_32 tileBase; ///< Base offset (in bits) inside micro tile which handles 804 /// the case that components are stored separately 805 UINT_32 compBits; ///< The component bits actually needed(for planar surface) 806 807 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 808 /// number of samples for normal AA; Set it to the 809 /// number of fragments for EQAA 810 /// r800 and later HWL parameters 811 // Used for 1D tiling above 812 AddrTileType tileType; ///< See defintion of AddrTileType 813 struct 814 { 815 UINT_32 ignoreSE : 1; ///< TRUE if shader engines are ignored. This is texture 816 /// only flag. Only non-RT texture can set this to TRUE 817 UINT_32 reserved :31; ///< Reserved for future use. 818 }; 819 // 2D tiling needs following structure 820 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data 821 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 822 /// while the global useTileIndex is set to 1 823 union 824 { 825 struct 826 { 827 UINT_32 bankSwizzle; ///< Bank swizzle 828 UINT_32 pipeSwizzle; ///< Pipe swizzle 829 }; 830 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE 831 }; 832 } ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT; 833 834 /** 835 **************************************************************************************************** 836 * ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT 837 * 838 * @brief 839 * Output structure for AddrComputeSurfaceCoordFromAddr 840 **************************************************************************************************** 841 */ 842 typedef struct _ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT 843 { 844 UINT_32 size; ///< Size of this structure in bytes 845 846 UINT_32 x; ///< X coordinate 847 UINT_32 y; ///< Y coordinate 848 UINT_32 slice; ///< Index of slices 849 UINT_32 sample; ///< Index of samples, means fragment index for EQAA 850 } ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT; 851 852 /** 853 **************************************************************************************************** 854 * AddrComputeSurfaceCoordFromAddr 855 * 856 * @brief 857 * Compute coordinate from a given surface address 858 **************************************************************************************************** 859 */ 860 ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceCoordFromAddr( 861 ADDR_HANDLE hLib, 862 const ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn, 863 ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut); 864 865 //////////////////////////////////////////////////////////////////////////////////////////////////// 866 // HTile functions 867 //////////////////////////////////////////////////////////////////////////////////////////////////// 868 869 /** 870 **************************************************************************************************** 871 * ADDR_HTILE_FLAGS 872 * 873 * @brief 874 * HTILE flags 875 **************************************************************************************************** 876 */ 877 typedef union _ADDR_HTILE_FLAGS 878 { 879 struct 880 { 881 UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable 882 UINT_32 skipTcCompatSizeAlign : 1; ///< Flag indicates that addrLib will not align htile 883 /// size to 256xBankxPipe when computing tc-compatible 884 /// htile info. 885 UINT_32 reserved : 30; ///< Reserved bits 886 }; 887 888 UINT_32 value; 889 } ADDR_HTILE_FLAGS; 890 891 /** 892 **************************************************************************************************** 893 * ADDR_COMPUTE_HTILE_INFO_INPUT 894 * 895 * @brief 896 * Input structure of AddrComputeHtileInfo 897 **************************************************************************************************** 898 */ 899 typedef struct _ADDR_COMPUTE_HTILE_INFO_INPUT 900 { 901 UINT_32 size; ///< Size of this structure in bytes 902 903 ADDR_HTILE_FLAGS flags; ///< HTILE flags 904 UINT_32 pitch; ///< Surface pitch, in pixels 905 UINT_32 height; ///< Surface height, in pixels 906 UINT_32 numSlices; ///< Number of slices 907 BOOL_32 isLinear; ///< Linear or tiled HTILE layout 908 AddrHtileBlockSize blockWidth; ///< 4 or 8. EG above only support 8 909 AddrHtileBlockSize blockHeight; ///< 4 or 8. EG above only support 8 910 ADDR_TILEINFO* pTileInfo; ///< Tile info 911 912 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 913 /// while the global useTileIndex is set to 1 914 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 915 ///< README: When tileIndex is not -1, this must be valid 916 } ADDR_COMPUTE_HTILE_INFO_INPUT; 917 918 /** 919 **************************************************************************************************** 920 * ADDR_COMPUTE_HTILE_INFO_OUTPUT 921 * 922 * @brief 923 * Output structure of AddrComputeHtileInfo 924 **************************************************************************************************** 925 */ 926 typedef struct _ADDR_COMPUTE_HTILE_INFO_OUTPUT 927 { 928 UINT_32 size; ///< Size of this structure in bytes 929 930 UINT_32 pitch; ///< Pitch in pixels of depth buffer represented in this 931 /// HTile buffer. This might be larger than original depth 932 /// buffer pitch when called with an unaligned pitch. 933 UINT_32 height; ///< Height in pixels, as above 934 UINT_64 htileBytes; ///< Size of HTILE buffer, in bytes 935 UINT_32 baseAlign; ///< Base alignment 936 UINT_32 bpp; ///< Bits per pixel for HTILE is how many bits for an 8x8 block! 937 UINT_32 macroWidth; ///< Macro width in pixels, actually squared cache shape 938 UINT_32 macroHeight; ///< Macro height in pixels 939 UINT_64 sliceSize; ///< Slice size, in bytes. 940 BOOL_32 sliceInterleaved; ///< Flag to indicate if different slice's htile is interleaved 941 /// Compute engine clear can't be used if htile is interleaved 942 BOOL_32 nextMipLevelCompressible; ///< Flag to indicate whether HTILE can be enabled in 943 /// next mip level, it also indicates if memory set based 944 /// fast clear can be used for current mip level. 945 } ADDR_COMPUTE_HTILE_INFO_OUTPUT; 946 947 /** 948 **************************************************************************************************** 949 * AddrComputeHtileInfo 950 * 951 * @brief 952 * Compute Htile pitch, height, base alignment and size in bytes 953 **************************************************************************************************** 954 */ 955 ADDR_E_RETURNCODE ADDR_API AddrComputeHtileInfo( 956 ADDR_HANDLE hLib, 957 const ADDR_COMPUTE_HTILE_INFO_INPUT* pIn, 958 ADDR_COMPUTE_HTILE_INFO_OUTPUT* pOut); 959 960 961 962 /** 963 **************************************************************************************************** 964 * ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT 965 * 966 * @brief 967 * Input structure for AddrComputeHtileAddrFromCoord 968 **************************************************************************************************** 969 */ 970 typedef struct _ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT 971 { 972 UINT_32 size; ///< Size of this structure in bytes 973 974 UINT_32 pitch; ///< Pitch, in pixels 975 UINT_32 height; ///< Height in pixels 976 UINT_32 x; ///< X coordinate 977 UINT_32 y; ///< Y coordinate 978 UINT_32 slice; ///< Index of slice 979 UINT_32 numSlices; ///< Number of slices 980 BOOL_32 isLinear; ///< Linear or tiled HTILE layout 981 ADDR_HTILE_FLAGS flags; ///< htile flags 982 AddrHtileBlockSize blockWidth; ///< 4 or 8. 1 means 8, 0 means 4. EG above only support 8 983 AddrHtileBlockSize blockHeight; ///< 4 or 8. 1 means 8, 0 means 4. EG above only support 8 984 ADDR_TILEINFO* pTileInfo; ///< Tile info 985 986 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 987 /// while the global useTileIndex is set to 1 988 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 989 ///< README: When tileIndex is not -1, this must be valid 990 UINT_32 bpp; ///< depth/stencil buffer bit per pixel size 991 UINT_32 zStencilAddr; ///< tcCompatible Z/Stencil surface address 992 } ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT; 993 994 /** 995 **************************************************************************************************** 996 * ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT 997 * 998 * @brief 999 * Output structure for AddrComputeHtileAddrFromCoord 1000 **************************************************************************************************** 1001 */ 1002 typedef struct _ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT 1003 { 1004 UINT_32 size; ///< Size of this structure in bytes 1005 1006 UINT_64 addr; ///< Address in bytes 1007 UINT_32 bitPosition; ///< Bit position, 0 or 4. CMASK and HTILE shares some lib method. 1008 /// So we keep bitPosition for HTILE as well 1009 } ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT; 1010 1011 /** 1012 **************************************************************************************************** 1013 * AddrComputeHtileAddrFromCoord 1014 * 1015 * @brief 1016 * Compute Htile address according to coordinates (of depth buffer) 1017 **************************************************************************************************** 1018 */ 1019 ADDR_E_RETURNCODE ADDR_API AddrComputeHtileAddrFromCoord( 1020 ADDR_HANDLE hLib, 1021 const ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, 1022 ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut); 1023 1024 1025 1026 /** 1027 **************************************************************************************************** 1028 * ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT 1029 * 1030 * @brief 1031 * Input structure for AddrComputeHtileCoordFromAddr 1032 **************************************************************************************************** 1033 */ 1034 typedef struct _ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT 1035 { 1036 UINT_32 size; ///< Size of this structure in bytes 1037 1038 UINT_64 addr; ///< Address 1039 UINT_32 bitPosition; ///< Bit position 0 or 4. CMASK and HTILE share some methods 1040 /// so we keep bitPosition for HTILE as well 1041 UINT_32 pitch; ///< Pitch, in pixels 1042 UINT_32 height; ///< Height, in pixels 1043 UINT_32 numSlices; ///< Number of slices 1044 BOOL_32 isLinear; ///< Linear or tiled HTILE layout 1045 AddrHtileBlockSize blockWidth; ///< 4 or 8. 1 means 8, 0 means 4. R8xx/R9xx only support 8 1046 AddrHtileBlockSize blockHeight; ///< 4 or 8. 1 means 8, 0 means 4. R8xx/R9xx only support 8 1047 ADDR_TILEINFO* pTileInfo; ///< Tile info 1048 1049 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1050 /// while the global useTileIndex is set to 1 1051 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1052 ///< README: When tileIndex is not -1, this must be valid 1053 } ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT; 1054 1055 /** 1056 **************************************************************************************************** 1057 * ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT 1058 * 1059 * @brief 1060 * Output structure for AddrComputeHtileCoordFromAddr 1061 **************************************************************************************************** 1062 */ 1063 typedef struct _ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT 1064 { 1065 UINT_32 size; ///< Size of this structure in bytes 1066 1067 UINT_32 x; ///< X coordinate 1068 UINT_32 y; ///< Y coordinate 1069 UINT_32 slice; ///< Slice index 1070 } ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT; 1071 1072 /** 1073 **************************************************************************************************** 1074 * AddrComputeHtileCoordFromAddr 1075 * 1076 * @brief 1077 * Compute coordinates within depth buffer (1st pixel of a micro tile) according to 1078 * Htile address 1079 **************************************************************************************************** 1080 */ 1081 ADDR_E_RETURNCODE ADDR_API AddrComputeHtileCoordFromAddr( 1082 ADDR_HANDLE hLib, 1083 const ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, 1084 ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut); 1085 1086 1087 1088 //////////////////////////////////////////////////////////////////////////////////////////////////// 1089 // C-mask functions 1090 //////////////////////////////////////////////////////////////////////////////////////////////////// 1091 1092 /** 1093 **************************************************************************************************** 1094 * ADDR_CMASK_FLAGS 1095 * 1096 * @brief 1097 * CMASK flags 1098 **************************************************************************************************** 1099 */ 1100 typedef union _ADDR_CMASK_FLAGS 1101 { 1102 struct 1103 { 1104 UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable 1105 UINT_32 reserved :31; ///< Reserved bits 1106 }; 1107 1108 UINT_32 value; 1109 } ADDR_CMASK_FLAGS; 1110 1111 /** 1112 **************************************************************************************************** 1113 * ADDR_COMPUTE_CMASK_INFO_INPUT 1114 * 1115 * @brief 1116 * Input structure of AddrComputeCmaskInfo 1117 **************************************************************************************************** 1118 */ 1119 typedef struct _ADDR_COMPUTE_CMASKINFO_INPUT 1120 { 1121 UINT_32 size; ///< Size of this structure in bytes 1122 1123 ADDR_CMASK_FLAGS flags; ///< CMASK flags 1124 UINT_32 pitch; ///< Pitch, in pixels, of color buffer 1125 UINT_32 height; ///< Height, in pixels, of color buffer 1126 UINT_32 numSlices; ///< Number of slices, of color buffer 1127 BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear 1128 ADDR_TILEINFO* pTileInfo; ///< Tile info 1129 1130 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1131 /// while the global useTileIndex is set to 1 1132 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1133 ///< README: When tileIndex is not -1, this must be valid 1134 } ADDR_COMPUTE_CMASK_INFO_INPUT; 1135 1136 /** 1137 **************************************************************************************************** 1138 * ADDR_COMPUTE_CMASK_INFO_OUTPUT 1139 * 1140 * @brief 1141 * Output structure of AddrComputeCmaskInfo 1142 **************************************************************************************************** 1143 */ 1144 typedef struct _ADDR_COMPUTE_CMASK_INFO_OUTPUT 1145 { 1146 UINT_32 size; ///< Size of this structure in bytes 1147 1148 UINT_32 pitch; ///< Pitch in pixels of color buffer which 1149 /// this Cmask matches. The size might be larger than 1150 /// original color buffer pitch when called with 1151 /// an unaligned pitch. 1152 UINT_32 height; ///< Height in pixels, as above 1153 UINT_64 cmaskBytes; ///< Size in bytes of CMask buffer 1154 UINT_32 baseAlign; ///< Base alignment 1155 UINT_32 blockMax; ///< Cmask block size. Need this to set CB_COLORn_MASK register 1156 UINT_32 macroWidth; ///< Macro width in pixels, actually squared cache shape 1157 UINT_32 macroHeight; ///< Macro height in pixels 1158 UINT_64 sliceSize; ///< Slice size, in bytes. 1159 } ADDR_COMPUTE_CMASK_INFO_OUTPUT; 1160 1161 /** 1162 **************************************************************************************************** 1163 * AddrComputeCmaskInfo 1164 * 1165 * @brief 1166 * Compute Cmask pitch, height, base alignment and size in bytes from color buffer 1167 * info 1168 **************************************************************************************************** 1169 */ 1170 ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskInfo( 1171 ADDR_HANDLE hLib, 1172 const ADDR_COMPUTE_CMASK_INFO_INPUT* pIn, 1173 ADDR_COMPUTE_CMASK_INFO_OUTPUT* pOut); 1174 1175 1176 1177 /** 1178 **************************************************************************************************** 1179 * ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT 1180 * 1181 * @brief 1182 * Input structure for AddrComputeCmaskAddrFromCoord 1183 * 1184 **************************************************************************************************** 1185 */ 1186 typedef struct _ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT 1187 { 1188 UINT_32 size; ///< Size of this structure in bytes 1189 UINT_32 x; ///< X coordinate 1190 UINT_32 y; ///< Y coordinate 1191 UINT_64 fmaskAddr; ///< Fmask addr for tc compatible Cmask 1192 UINT_32 slice; ///< Slice index 1193 UINT_32 pitch; ///< Pitch in pixels, of color buffer 1194 UINT_32 height; ///< Height in pixels, of color buffer 1195 UINT_32 numSlices; ///< Number of slices 1196 UINT_32 bpp; 1197 BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear 1198 ADDR_CMASK_FLAGS flags; ///< CMASK flags 1199 ADDR_TILEINFO* pTileInfo; ///< Tile info 1200 1201 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1202 ///< while the global useTileIndex is set to 1 1203 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1204 ///< README: When tileIndex is not -1, this must be valid 1205 } ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT; 1206 1207 /** 1208 **************************************************************************************************** 1209 * ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT 1210 * 1211 * @brief 1212 * Output structure for AddrComputeCmaskAddrFromCoord 1213 **************************************************************************************************** 1214 */ 1215 typedef struct _ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT 1216 { 1217 UINT_32 size; ///< Size of this structure in bytes 1218 1219 UINT_64 addr; ///< CMASK address in bytes 1220 UINT_32 bitPosition; ///< Bit position within addr, 0-7. CMASK is 4 bpp, 1221 /// so the address may be located in bit 0 (0) or 4 (4) 1222 } ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT; 1223 1224 /** 1225 **************************************************************************************************** 1226 * AddrComputeCmaskAddrFromCoord 1227 * 1228 * @brief 1229 * Compute Cmask address according to coordinates (of MSAA color buffer) 1230 **************************************************************************************************** 1231 */ 1232 ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskAddrFromCoord( 1233 ADDR_HANDLE hLib, 1234 const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, 1235 ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut); 1236 1237 1238 1239 /** 1240 **************************************************************************************************** 1241 * ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT 1242 * 1243 * @brief 1244 * Input structure for AddrComputeCmaskCoordFromAddr 1245 **************************************************************************************************** 1246 */ 1247 typedef struct _ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT 1248 { 1249 UINT_32 size; ///< Size of this structure in bytes 1250 1251 UINT_64 addr; ///< CMASK address in bytes 1252 UINT_32 bitPosition; ///< Bit position within addr, 0-7. CMASK is 4 bpp, 1253 /// so the address may be located in bit 0 (0) or 4 (4) 1254 UINT_32 pitch; ///< Pitch, in pixels 1255 UINT_32 height; ///< Height in pixels 1256 UINT_32 numSlices; ///< Number of slices 1257 BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear 1258 ADDR_TILEINFO* pTileInfo; ///< Tile info 1259 1260 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1261 /// while the global useTileIndex is set to 1 1262 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1263 ///< README: When tileIndex is not -1, this must be valid 1264 } ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT; 1265 1266 /** 1267 **************************************************************************************************** 1268 * ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT 1269 * 1270 * @brief 1271 * Output structure for AddrComputeCmaskCoordFromAddr 1272 **************************************************************************************************** 1273 */ 1274 typedef struct _ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT 1275 { 1276 UINT_32 size; ///< Size of this structure in bytes 1277 1278 UINT_32 x; ///< X coordinate 1279 UINT_32 y; ///< Y coordinate 1280 UINT_32 slice; ///< Slice index 1281 } ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT; 1282 1283 /** 1284 **************************************************************************************************** 1285 * AddrComputeCmaskCoordFromAddr 1286 * 1287 * @brief 1288 * Compute coordinates within color buffer (1st pixel of a micro tile) according to 1289 * Cmask address 1290 **************************************************************************************************** 1291 */ 1292 ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskCoordFromAddr( 1293 ADDR_HANDLE hLib, 1294 const ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn, 1295 ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut); 1296 1297 1298 1299 //////////////////////////////////////////////////////////////////////////////////////////////////// 1300 // F-mask functions 1301 //////////////////////////////////////////////////////////////////////////////////////////////////// 1302 1303 /** 1304 **************************************************************************************************** 1305 * ADDR_COMPUTE_FMASK_INFO_INPUT 1306 * 1307 * @brief 1308 * Input structure for AddrComputeFmaskInfo 1309 **************************************************************************************************** 1310 */ 1311 typedef struct _ADDR_COMPUTE_FMASK_INFO_INPUT 1312 { 1313 UINT_32 size; ///< Size of this structure in bytes 1314 1315 AddrTileMode tileMode; ///< Tile mode 1316 UINT_32 pitch; ///< Surface pitch, in pixels 1317 UINT_32 height; ///< Surface height, in pixels 1318 UINT_32 numSlices; ///< Number of slice/depth 1319 UINT_32 numSamples; ///< Number of samples 1320 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 1321 /// number of samples for normal AA; Set it to the 1322 /// number of fragments for EQAA 1323 /// r800 and later HWL parameters 1324 struct 1325 { 1326 UINT_32 resolved: 1; ///< TRUE if the surface is for resolved fmask, only used 1327 /// by H/W clients. S/W should always set it to FALSE. 1328 UINT_32 reserved: 31; ///< Reserved for future use. 1329 }; 1330 ADDR_TILEINFO* pTileInfo; ///< 2D tiling parameters. Clients must give valid data 1331 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1332 /// while the global useTileIndex is set to 1 1333 } ADDR_COMPUTE_FMASK_INFO_INPUT; 1334 1335 /** 1336 **************************************************************************************************** 1337 * ADDR_COMPUTE_FMASK_INFO_OUTPUT 1338 * 1339 * @brief 1340 * Output structure for AddrComputeFmaskInfo 1341 **************************************************************************************************** 1342 */ 1343 typedef struct _ADDR_COMPUTE_FMASK_INFO_OUTPUT 1344 { 1345 UINT_32 size; ///< Size of this structure in bytes 1346 1347 UINT_32 pitch; ///< Pitch of fmask in pixels 1348 UINT_32 height; ///< Height of fmask in pixels 1349 UINT_32 numSlices; ///< Slices of fmask 1350 UINT_64 fmaskBytes; ///< Size of fmask in bytes 1351 UINT_32 baseAlign; ///< Base address alignment 1352 UINT_32 pitchAlign; ///< Pitch alignment 1353 UINT_32 heightAlign; ///< Height alignment 1354 UINT_32 bpp; ///< Bits per pixel of FMASK is: number of bit planes 1355 UINT_32 numSamples; ///< Number of samples, used for dump, export this since input 1356 /// may be changed in 9xx and above 1357 /// r800 and later HWL parameters 1358 ADDR_TILEINFO* pTileInfo; ///< Tile parameters used. Fmask can have different 1359 /// bank_height from color buffer 1360 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1361 /// while the global useTileIndex is set to 1 1362 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1363 UINT_64 sliceSize; ///< Size of slice in bytes 1364 } ADDR_COMPUTE_FMASK_INFO_OUTPUT; 1365 1366 /** 1367 **************************************************************************************************** 1368 * AddrComputeFmaskInfo 1369 * 1370 * @brief 1371 * Compute Fmask pitch/height/depth/alignments and size in bytes 1372 **************************************************************************************************** 1373 */ 1374 ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskInfo( 1375 ADDR_HANDLE hLib, 1376 const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn, 1377 ADDR_COMPUTE_FMASK_INFO_OUTPUT* pOut); 1378 1379 1380 1381 /** 1382 **************************************************************************************************** 1383 * ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT 1384 * 1385 * @brief 1386 * Input structure for AddrComputeFmaskAddrFromCoord 1387 **************************************************************************************************** 1388 */ 1389 typedef struct _ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT 1390 { 1391 UINT_32 size; ///< Size of this structure in bytes 1392 1393 UINT_32 x; ///< X coordinate 1394 UINT_32 y; ///< Y coordinate 1395 UINT_32 slice; ///< Slice index 1396 UINT_32 plane; ///< Plane number 1397 UINT_32 sample; ///< Sample index (fragment index for EQAA) 1398 1399 UINT_32 pitch; ///< Surface pitch, in pixels 1400 UINT_32 height; ///< Surface height, in pixels 1401 UINT_32 numSamples; ///< Number of samples 1402 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 1403 /// number of samples for normal AA; Set it to the 1404 /// number of fragments for EQAA 1405 1406 AddrTileMode tileMode; ///< Tile mode 1407 union 1408 { 1409 struct 1410 { 1411 UINT_32 bankSwizzle; ///< Bank swizzle 1412 UINT_32 pipeSwizzle; ///< Pipe swizzle 1413 }; 1414 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE 1415 }; 1416 1417 /// r800 and later HWL parameters 1418 struct 1419 { 1420 UINT_32 resolved: 1; ///< TRUE if this is a resolved fmask, used by H/W clients 1421 UINT_32 ignoreSE: 1; ///< TRUE if shader engines are ignored. 1422 UINT_32 reserved: 30; ///< Reserved for future use. 1423 }; 1424 ADDR_TILEINFO* pTileInfo; ///< 2D tiling parameters. Client must provide all data 1425 1426 } ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT; 1427 1428 /** 1429 **************************************************************************************************** 1430 * ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT 1431 * 1432 * @brief 1433 * Output structure for AddrComputeFmaskAddrFromCoord 1434 **************************************************************************************************** 1435 */ 1436 typedef struct _ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT 1437 { 1438 UINT_32 size; ///< Size of this structure in bytes 1439 1440 UINT_64 addr; ///< Fmask address 1441 UINT_32 bitPosition; ///< Bit position within fmaskAddr, 0-7. 1442 } ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT; 1443 1444 /** 1445 **************************************************************************************************** 1446 * AddrComputeFmaskAddrFromCoord 1447 * 1448 * @brief 1449 * Compute Fmask address according to coordinates (x,y,slice,sample,plane) 1450 **************************************************************************************************** 1451 */ 1452 ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskAddrFromCoord( 1453 ADDR_HANDLE hLib, 1454 const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn, 1455 ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut); 1456 1457 1458 1459 /** 1460 **************************************************************************************************** 1461 * ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT 1462 * 1463 * @brief 1464 * Input structure for AddrComputeFmaskCoordFromAddr 1465 **************************************************************************************************** 1466 */ 1467 typedef struct _ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT 1468 { 1469 UINT_32 size; ///< Size of this structure in bytes 1470 1471 UINT_64 addr; ///< Address 1472 UINT_32 bitPosition; ///< Bit position within addr, 0-7. 1473 1474 UINT_32 pitch; ///< Pitch, in pixels 1475 UINT_32 height; ///< Height in pixels 1476 UINT_32 numSamples; ///< Number of samples 1477 UINT_32 numFrags; ///< Number of fragments 1478 AddrTileMode tileMode; ///< Tile mode 1479 union 1480 { 1481 struct 1482 { 1483 UINT_32 bankSwizzle; ///< Bank swizzle 1484 UINT_32 pipeSwizzle; ///< Pipe swizzle 1485 }; 1486 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE 1487 }; 1488 1489 /// r800 and later HWL parameters 1490 struct 1491 { 1492 UINT_32 resolved: 1; ///< TRUE if this is a resolved fmask, used by HW components 1493 UINT_32 ignoreSE: 1; ///< TRUE if shader engines are ignored. 1494 UINT_32 reserved: 30; ///< Reserved for future use. 1495 }; 1496 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data 1497 1498 } ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT; 1499 1500 /** 1501 **************************************************************************************************** 1502 * ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT 1503 * 1504 * @brief 1505 * Output structure for AddrComputeFmaskCoordFromAddr 1506 **************************************************************************************************** 1507 */ 1508 typedef struct _ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT 1509 { 1510 UINT_32 size; ///< Size of this structure in bytes 1511 1512 UINT_32 x; ///< X coordinate 1513 UINT_32 y; ///< Y coordinate 1514 UINT_32 slice; ///< Slice index 1515 UINT_32 plane; ///< Plane number 1516 UINT_32 sample; ///< Sample index (fragment index for EQAA) 1517 } ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT; 1518 1519 /** 1520 **************************************************************************************************** 1521 * AddrComputeFmaskCoordFromAddr 1522 * 1523 * @brief 1524 * Compute FMASK coordinate from an given address 1525 **************************************************************************************************** 1526 */ 1527 ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskCoordFromAddr( 1528 ADDR_HANDLE hLib, 1529 const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn, 1530 ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut); 1531 1532 1533 //////////////////////////////////////////////////////////////////////////////////////////////////// 1534 // Element/utility functions 1535 //////////////////////////////////////////////////////////////////////////////////////////////////// 1536 1537 /** 1538 **************************************************************************************************** 1539 * AddrGetVersion 1540 * 1541 * @brief 1542 * Get AddrLib version number 1543 **************************************************************************************************** 1544 */ 1545 UINT_32 ADDR_API AddrGetVersion(ADDR_HANDLE hLib); 1546 1547 /** 1548 **************************************************************************************************** 1549 * AddrGetInterfaceVersion 1550 * 1551 * @brief 1552 * Get AddrLib interface version number (eg. Addr2 = 2) 1553 **************************************************************************************************** 1554 */ 1555 UINT_32 ADDR_API AddrGetInterfaceVersion(ADDR_HANDLE hLib); 1556 1557 /** 1558 **************************************************************************************************** 1559 * AddrUseTileIndex 1560 * 1561 * @brief 1562 * Return TRUE if tileIndex is enabled in this address library 1563 **************************************************************************************************** 1564 */ 1565 BOOL_32 ADDR_API AddrUseTileIndex(ADDR_HANDLE hLib); 1566 1567 /** 1568 **************************************************************************************************** 1569 * AddrUseCombinedSwizzle 1570 * 1571 * @brief 1572 * Return TRUE if combined swizzle is enabled in this address library 1573 **************************************************************************************************** 1574 */ 1575 BOOL_32 ADDR_API AddrUseCombinedSwizzle(ADDR_HANDLE hLib); 1576 1577 /** 1578 **************************************************************************************************** 1579 * ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT 1580 * 1581 * @brief 1582 * Input structure of AddrExtractBankPipeSwizzle 1583 **************************************************************************************************** 1584 */ 1585 typedef struct _ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT 1586 { 1587 UINT_32 size; ///< Size of this structure in bytes 1588 1589 UINT_32 base256b; ///< Base256b value 1590 1591 /// r800 and later HWL parameters 1592 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data 1593 1594 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1595 /// while the global useTileIndex is set to 1 1596 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1597 ///< README: When tileIndex is not -1, this must be valid 1598 } ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT; 1599 1600 /** 1601 **************************************************************************************************** 1602 * ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT 1603 * 1604 * @brief 1605 * Output structure of AddrExtractBankPipeSwizzle 1606 **************************************************************************************************** 1607 */ 1608 typedef struct _ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT 1609 { 1610 UINT_32 size; ///< Size of this structure in bytes 1611 1612 UINT_32 bankSwizzle; ///< Bank swizzle 1613 UINT_32 pipeSwizzle; ///< Pipe swizzle 1614 } ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT; 1615 1616 /** 1617 **************************************************************************************************** 1618 * AddrExtractBankPipeSwizzle 1619 * 1620 * @brief 1621 * Extract Bank and Pipe swizzle from base256b 1622 * @return 1623 * ADDR_OK if no error 1624 **************************************************************************************************** 1625 */ 1626 ADDR_E_RETURNCODE ADDR_API AddrExtractBankPipeSwizzle( 1627 ADDR_HANDLE hLib, 1628 const ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT* pIn, 1629 ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT* pOut); 1630 1631 1632 /** 1633 **************************************************************************************************** 1634 * ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT 1635 * 1636 * @brief 1637 * Input structure of AddrCombineBankPipeSwizzle 1638 **************************************************************************************************** 1639 */ 1640 typedef struct _ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT 1641 { 1642 UINT_32 size; ///< Size of this structure in bytes 1643 1644 UINT_32 bankSwizzle; ///< Bank swizzle 1645 UINT_32 pipeSwizzle; ///< Pipe swizzle 1646 UINT_64 baseAddr; ///< Base address (leave it zero for driver clients) 1647 1648 /// r800 and later HWL parameters 1649 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data 1650 1651 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1652 /// while the global useTileIndex is set to 1 1653 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1654 ///< README: When tileIndex is not -1, this must be valid 1655 } ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT; 1656 1657 /** 1658 **************************************************************************************************** 1659 * ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT 1660 * 1661 * @brief 1662 * Output structure of AddrCombineBankPipeSwizzle 1663 **************************************************************************************************** 1664 */ 1665 typedef struct _ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT 1666 { 1667 UINT_32 size; ///< Size of this structure in bytes 1668 1669 UINT_32 tileSwizzle; ///< Combined swizzle 1670 } ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT; 1671 1672 /** 1673 **************************************************************************************************** 1674 * AddrCombineBankPipeSwizzle 1675 * 1676 * @brief 1677 * Combine Bank and Pipe swizzle 1678 * @return 1679 * ADDR_OK if no error 1680 * @note 1681 * baseAddr here is full MCAddress instead of base256b 1682 **************************************************************************************************** 1683 */ 1684 ADDR_E_RETURNCODE ADDR_API AddrCombineBankPipeSwizzle( 1685 ADDR_HANDLE hLib, 1686 const ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT* pIn, 1687 ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT* pOut); 1688 1689 1690 1691 /** 1692 **************************************************************************************************** 1693 * ADDR_COMPUTE_SLICESWIZZLE_INPUT 1694 * 1695 * @brief 1696 * Input structure of AddrComputeSliceSwizzle 1697 **************************************************************************************************** 1698 */ 1699 typedef struct _ADDR_COMPUTE_SLICESWIZZLE_INPUT 1700 { 1701 UINT_32 size; ///< Size of this structure in bytes 1702 1703 AddrTileMode tileMode; ///< Tile Mode 1704 UINT_32 baseSwizzle; ///< Base tile swizzle 1705 UINT_32 slice; ///< Slice index 1706 UINT_64 baseAddr; ///< Base address, driver should leave it 0 in most cases 1707 1708 /// r800 and later HWL parameters 1709 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Actually banks needed here! 1710 1711 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1712 /// while the global useTileIndex is set to 1 1713 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1714 ///< README: When tileIndex is not -1, this must be valid 1715 } ADDR_COMPUTE_SLICESWIZZLE_INPUT; 1716 1717 1718 1719 /** 1720 **************************************************************************************************** 1721 * ADDR_COMPUTE_SLICESWIZZLE_OUTPUT 1722 * 1723 * @brief 1724 * Output structure of AddrComputeSliceSwizzle 1725 **************************************************************************************************** 1726 */ 1727 typedef struct _ADDR_COMPUTE_SLICESWIZZLE_OUTPUT 1728 { 1729 UINT_32 size; ///< Size of this structure in bytes 1730 1731 UINT_32 tileSwizzle; ///< Recalculated tileSwizzle value 1732 } ADDR_COMPUTE_SLICESWIZZLE_OUTPUT; 1733 1734 /** 1735 **************************************************************************************************** 1736 * AddrComputeSliceSwizzle 1737 * 1738 * @brief 1739 * Extract Bank and Pipe swizzle from base256b 1740 * @return 1741 * ADDR_OK if no error 1742 **************************************************************************************************** 1743 */ 1744 ADDR_E_RETURNCODE ADDR_API AddrComputeSliceSwizzle( 1745 ADDR_HANDLE hLib, 1746 const ADDR_COMPUTE_SLICESWIZZLE_INPUT* pIn, 1747 ADDR_COMPUTE_SLICESWIZZLE_OUTPUT* pOut); 1748 1749 1750 /** 1751 **************************************************************************************************** 1752 * AddrSwizzleGenOption 1753 * 1754 * @brief 1755 * Which swizzle generating options: legacy or linear 1756 **************************************************************************************************** 1757 */ 1758 typedef enum _AddrSwizzleGenOption 1759 { 1760 ADDR_SWIZZLE_GEN_DEFAULT = 0, ///< As is in client driver implemention for swizzle 1761 ADDR_SWIZZLE_GEN_LINEAR = 1, ///< Using a linear increment of swizzle 1762 } AddrSwizzleGenOption; 1763 1764 /** 1765 **************************************************************************************************** 1766 * AddrBlockType 1767 * 1768 * @brief 1769 * Macro define resource block type 1770 **************************************************************************************************** 1771 */ 1772 typedef enum 1773 { 1774 AddrBlockLinear = 0, // Resource uses linear swizzle mode 1775 AddrBlockMicro = 1, // Resource uses 256B block 1776 AddrBlockThin4KB = 2, // Resource uses thin 4KB block 1777 AddrBlockThick4KB = 3, // Resource uses thick 4KB block 1778 AddrBlockThin64KB = 4, // Resource uses thin 64KB block 1779 AddrBlockThick64KB = 5, // Resource uses thick 64KB block 1780 AddrBlockThinVar = 6, // Resource uses thin var block 1781 AddrBlockThickVar = 7, // Resource uses thick var block 1782 AddrBlockMaxTiledType, 1783 1784 AddrBlockThin256KB = AddrBlockThinVar, 1785 AddrBlockThick256KB = AddrBlockThickVar, 1786 } AddrBlockType; 1787 1788 /** 1789 **************************************************************************************************** 1790 * AddrSwizzleOption 1791 * 1792 * @brief 1793 * Controls how swizzle is generated 1794 **************************************************************************************************** 1795 */ 1796 typedef union _ADDR_SWIZZLE_OPTION 1797 { 1798 struct 1799 { 1800 UINT_32 genOption : 1; ///< The way swizzle is generated, see AddrSwizzleGenOption 1801 UINT_32 reduceBankBit : 1; ///< TRUE if we need reduce swizzle bits 1802 UINT_32 reserved :30; ///< Reserved bits 1803 }; 1804 1805 UINT_32 value; 1806 1807 } ADDR_SWIZZLE_OPTION; 1808 1809 /** 1810 **************************************************************************************************** 1811 * ADDR_COMPUTE_BASE_SWIZZLE_INPUT 1812 * 1813 * @brief 1814 * Input structure of AddrComputeBaseSwizzle 1815 **************************************************************************************************** 1816 */ 1817 typedef struct _ADDR_COMPUTE_BASE_SWIZZLE_INPUT 1818 { 1819 UINT_32 size; ///< Size of this structure in bytes 1820 1821 ADDR_SWIZZLE_OPTION option; ///< Swizzle option 1822 UINT_32 surfIndex; ///< Index of this surface type 1823 AddrTileMode tileMode; ///< Tile Mode 1824 1825 /// r800 and later HWL parameters 1826 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Actually banks needed here! 1827 1828 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1829 /// while the global useTileIndex is set to 1 1830 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1831 ///< README: When tileIndex is not -1, this must be valid 1832 } ADDR_COMPUTE_BASE_SWIZZLE_INPUT; 1833 1834 /** 1835 **************************************************************************************************** 1836 * ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT 1837 * 1838 * @brief 1839 * Output structure of AddrComputeBaseSwizzle 1840 **************************************************************************************************** 1841 */ 1842 typedef struct _ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT 1843 { 1844 UINT_32 size; ///< Size of this structure in bytes 1845 1846 UINT_32 tileSwizzle; ///< Combined swizzle 1847 } ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT; 1848 1849 /** 1850 **************************************************************************************************** 1851 * AddrComputeBaseSwizzle 1852 * 1853 * @brief 1854 * Return a Combined Bank and Pipe swizzle base on surface based on surface type/index 1855 * @return 1856 * ADDR_OK if no error 1857 **************************************************************************************************** 1858 */ 1859 ADDR_E_RETURNCODE ADDR_API AddrComputeBaseSwizzle( 1860 ADDR_HANDLE hLib, 1861 const ADDR_COMPUTE_BASE_SWIZZLE_INPUT* pIn, 1862 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT* pOut); 1863 1864 1865 /** 1866 **************************************************************************************************** 1867 * ELEM_GETEXPORTNORM_INPUT 1868 * 1869 * @brief 1870 * Input structure for ElemGetExportNorm 1871 * 1872 **************************************************************************************************** 1873 */ 1874 typedef struct _ELEM_GETEXPORTNORM_INPUT 1875 { 1876 UINT_32 size; ///< Size of this structure in bytes 1877 1878 AddrColorFormat format; ///< Color buffer format; Client should use ColorFormat 1879 AddrSurfaceNumber num; ///< Surface number type; Client should use NumberType 1880 AddrSurfaceSwap swap; ///< Surface swap byte swap; Client should use SurfaceSwap 1881 UINT_32 numSamples; ///< Number of samples 1882 } ELEM_GETEXPORTNORM_INPUT; 1883 1884 /** 1885 **************************************************************************************************** 1886 * ElemGetExportNorm 1887 * 1888 * @brief 1889 * Helper function to check one format can be EXPORT_NUM, which is a register 1890 * CB_COLOR_INFO.SURFACE_FORMAT. FP16 can be reported as EXPORT_NORM for rv770 in r600 1891 * family 1892 * @note 1893 * The implementation is only for r600. 1894 * 00 - EXPORT_FULL: PS exports are 4 pixels with 4 components with 32-bits-per-component. (two 1895 * clocks per export) 1896 * 01 - EXPORT_NORM: PS exports are 4 pixels with 4 components with 16-bits-per-component. (one 1897 * clock per export) 1898 * 1899 **************************************************************************************************** 1900 */ 1901 BOOL_32 ADDR_API ElemGetExportNorm( 1902 ADDR_HANDLE hLib, 1903 const ELEM_GETEXPORTNORM_INPUT* pIn); 1904 1905 1906 1907 /** 1908 **************************************************************************************************** 1909 * ELEM_FLT32TODEPTHPIXEL_INPUT 1910 * 1911 * @brief 1912 * Input structure for addrFlt32ToDepthPixel 1913 * 1914 **************************************************************************************************** 1915 */ 1916 typedef struct _ELEM_FLT32TODEPTHPIXEL_INPUT 1917 { 1918 UINT_32 size; ///< Size of this structure in bytes 1919 1920 AddrDepthFormat format; ///< Depth buffer format 1921 ADDR_FLT_32 comps[2]; ///< Component values (Z/stencil) 1922 } ELEM_FLT32TODEPTHPIXEL_INPUT; 1923 1924 /** 1925 **************************************************************************************************** 1926 * ELEM_FLT32TODEPTHPIXEL_INPUT 1927 * 1928 * @brief 1929 * Output structure for ElemFlt32ToDepthPixel 1930 * 1931 **************************************************************************************************** 1932 */ 1933 typedef struct _ELEM_FLT32TODEPTHPIXEL_OUTPUT 1934 { 1935 UINT_32 size; ///< Size of this structure in bytes 1936 1937 UINT_8* pPixel; ///< Real depth value. Same data type as depth buffer. 1938 /// Client must provide enough storage for this type. 1939 UINT_32 depthBase; ///< Tile base in bits for depth bits 1940 UINT_32 stencilBase; ///< Tile base in bits for stencil bits 1941 UINT_32 depthBits; ///< Bits for depth 1942 UINT_32 stencilBits; ///< Bits for stencil 1943 } ELEM_FLT32TODEPTHPIXEL_OUTPUT; 1944 1945 /** 1946 **************************************************************************************************** 1947 * ElemFlt32ToDepthPixel 1948 * 1949 * @brief 1950 * Convert a FLT_32 value to a depth/stencil pixel value 1951 * 1952 * @return 1953 * Return code 1954 * 1955 **************************************************************************************************** 1956 */ 1957 ADDR_E_RETURNCODE ADDR_API ElemFlt32ToDepthPixel( 1958 ADDR_HANDLE hLib, 1959 const ELEM_FLT32TODEPTHPIXEL_INPUT* pIn, 1960 ELEM_FLT32TODEPTHPIXEL_OUTPUT* pOut); 1961 1962 1963 1964 /** 1965 **************************************************************************************************** 1966 * ELEM_FLT32TOCOLORPIXEL_INPUT 1967 * 1968 * @brief 1969 * Input structure for addrFlt32ToColorPixel 1970 * 1971 **************************************************************************************************** 1972 */ 1973 typedef struct _ELEM_FLT32TOCOLORPIXEL_INPUT 1974 { 1975 UINT_32 size; ///< Size of this structure in bytes 1976 1977 AddrColorFormat format; ///< Color buffer format 1978 AddrSurfaceNumber surfNum; ///< Surface number 1979 AddrSurfaceSwap surfSwap; ///< Surface swap 1980 ADDR_FLT_32 comps[4]; ///< Component values (r/g/b/a) 1981 } ELEM_FLT32TOCOLORPIXEL_INPUT; 1982 1983 /** 1984 **************************************************************************************************** 1985 * ELEM_FLT32TOCOLORPIXEL_INPUT 1986 * 1987 * @brief 1988 * Output structure for ElemFlt32ToColorPixel 1989 * 1990 **************************************************************************************************** 1991 */ 1992 typedef struct _ELEM_FLT32TOCOLORPIXEL_OUTPUT 1993 { 1994 UINT_32 size; ///< Size of this structure in bytes 1995 1996 UINT_8* pPixel; ///< Real color value. Same data type as color buffer. 1997 /// Client must provide enough storage for this type. 1998 } ELEM_FLT32TOCOLORPIXEL_OUTPUT; 1999 2000 /** 2001 **************************************************************************************************** 2002 * ElemFlt32ToColorPixel 2003 * 2004 * @brief 2005 * Convert a FLT_32 value to a red/green/blue/alpha pixel value 2006 * 2007 * @return 2008 * Return code 2009 * 2010 **************************************************************************************************** 2011 */ 2012 ADDR_E_RETURNCODE ADDR_API ElemFlt32ToColorPixel( 2013 ADDR_HANDLE hLib, 2014 const ELEM_FLT32TOCOLORPIXEL_INPUT* pIn, 2015 ELEM_FLT32TOCOLORPIXEL_OUTPUT* pOut); 2016 2017 /** 2018 **************************************************************************************************** 2019 * ElemSize 2020 * 2021 * @brief 2022 * Get bits-per-element for specified format 2023 * 2024 * @return 2025 * Bits-per-element of specified format 2026 * 2027 **************************************************************************************************** 2028 */ 2029 UINT_32 ADDR_API ElemSize( 2030 ADDR_HANDLE hLib, 2031 AddrFormat format); 2032 2033 /** 2034 **************************************************************************************************** 2035 * ADDR_CONVERT_TILEINFOTOHW_INPUT 2036 * 2037 * @brief 2038 * Input structure for AddrConvertTileInfoToHW 2039 * @note 2040 * When reverse is TRUE, indices are igonred 2041 **************************************************************************************************** 2042 */ 2043 typedef struct _ADDR_CONVERT_TILEINFOTOHW_INPUT 2044 { 2045 UINT_32 size; ///< Size of this structure in bytes 2046 BOOL_32 reverse; ///< Convert control flag. 2047 /// FALSE: convert from real value to HW value; 2048 /// TRUE: convert from HW value to real value. 2049 2050 /// r800 and later HWL parameters 2051 ADDR_TILEINFO* pTileInfo; ///< Tile parameters with real value 2052 2053 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 2054 /// while the global useTileIndex is set to 1 2055 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 2056 ///< README: When tileIndex is not -1, this must be valid 2057 UINT_32 bpp; ///< Bits per pixel 2058 } ADDR_CONVERT_TILEINFOTOHW_INPUT; 2059 2060 /** 2061 **************************************************************************************************** 2062 * ADDR_CONVERT_TILEINFOTOHW_OUTPUT 2063 * 2064 * @brief 2065 * Output structure for AddrConvertTileInfoToHW 2066 **************************************************************************************************** 2067 */ 2068 typedef struct _ADDR_CONVERT_TILEINFOTOHW_OUTPUT 2069 { 2070 UINT_32 size; ///< Size of this structure in bytes 2071 2072 /// r800 and later HWL parameters 2073 ADDR_TILEINFO* pTileInfo; ///< Tile parameters with hardware register value 2074 2075 } ADDR_CONVERT_TILEINFOTOHW_OUTPUT; 2076 2077 /** 2078 **************************************************************************************************** 2079 * AddrConvertTileInfoToHW 2080 * 2081 * @brief 2082 * Convert tile info from real value to hardware register value 2083 **************************************************************************************************** 2084 */ 2085 ADDR_E_RETURNCODE ADDR_API AddrConvertTileInfoToHW( 2086 ADDR_HANDLE hLib, 2087 const ADDR_CONVERT_TILEINFOTOHW_INPUT* pIn, 2088 ADDR_CONVERT_TILEINFOTOHW_OUTPUT* pOut); 2089 2090 2091 2092 /** 2093 **************************************************************************************************** 2094 * ADDR_CONVERT_TILEINDEX_INPUT 2095 * 2096 * @brief 2097 * Input structure for AddrConvertTileIndex 2098 **************************************************************************************************** 2099 */ 2100 typedef struct _ADDR_CONVERT_TILEINDEX_INPUT 2101 { 2102 UINT_32 size; ///< Size of this structure in bytes 2103 2104 INT_32 tileIndex; ///< Tile index 2105 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 2106 UINT_32 bpp; ///< Bits per pixel 2107 BOOL_32 tileInfoHw; ///< Set to TRUE if client wants HW enum, otherwise actual 2108 } ADDR_CONVERT_TILEINDEX_INPUT; 2109 2110 /** 2111 **************************************************************************************************** 2112 * ADDR_CONVERT_TILEINDEX_OUTPUT 2113 * 2114 * @brief 2115 * Output structure for AddrConvertTileIndex 2116 **************************************************************************************************** 2117 */ 2118 typedef struct _ADDR_CONVERT_TILEINDEX_OUTPUT 2119 { 2120 UINT_32 size; ///< Size of this structure in bytes 2121 2122 AddrTileMode tileMode; ///< Tile mode 2123 AddrTileType tileType; ///< Tile type 2124 ADDR_TILEINFO* pTileInfo; ///< Tile info 2125 2126 } ADDR_CONVERT_TILEINDEX_OUTPUT; 2127 2128 /** 2129 **************************************************************************************************** 2130 * AddrConvertTileIndex 2131 * 2132 * @brief 2133 * Convert tile index to tile mode/type/info 2134 **************************************************************************************************** 2135 */ 2136 ADDR_E_RETURNCODE ADDR_API AddrConvertTileIndex( 2137 ADDR_HANDLE hLib, 2138 const ADDR_CONVERT_TILEINDEX_INPUT* pIn, 2139 ADDR_CONVERT_TILEINDEX_OUTPUT* pOut); 2140 2141 /** 2142 **************************************************************************************************** 2143 * ADDR_GET_MACROMODEINDEX_INPUT 2144 * 2145 * @brief 2146 * Input structure for AddrGetMacroModeIndex 2147 **************************************************************************************************** 2148 */ 2149 typedef struct _ADDR_GET_MACROMODEINDEX_INPUT 2150 { 2151 UINT_32 size; ///< Size of this structure in bytes 2152 ADDR_SURFACE_FLAGS flags; ///< Surface flag 2153 INT_32 tileIndex; ///< Tile index 2154 UINT_32 bpp; ///< Bits per pixel 2155 UINT_32 numFrags; ///< Number of color fragments 2156 } ADDR_GET_MACROMODEINDEX_INPUT; 2157 2158 /** 2159 **************************************************************************************************** 2160 * ADDR_GET_MACROMODEINDEX_OUTPUT 2161 * 2162 * @brief 2163 * Output structure for AddrGetMacroModeIndex 2164 **************************************************************************************************** 2165 */ 2166 typedef struct _ADDR_GET_MACROMODEINDEX_OUTPUT 2167 { 2168 UINT_32 size; ///< Size of this structure in bytes 2169 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 2170 } ADDR_GET_MACROMODEINDEX_OUTPUT; 2171 2172 /** 2173 **************************************************************************************************** 2174 * AddrGetMacroModeIndex 2175 * 2176 * @brief 2177 * Get macro mode index based on input parameters 2178 **************************************************************************************************** 2179 */ 2180 ADDR_E_RETURNCODE ADDR_API AddrGetMacroModeIndex( 2181 ADDR_HANDLE hLib, 2182 const ADDR_GET_MACROMODEINDEX_INPUT* pIn, 2183 ADDR_GET_MACROMODEINDEX_OUTPUT* pOut); 2184 2185 /** 2186 **************************************************************************************************** 2187 * ADDR_CONVERT_TILEINDEX1_INPUT 2188 * 2189 * @brief 2190 * Input structure for AddrConvertTileIndex1 (without macro mode index) 2191 **************************************************************************************************** 2192 */ 2193 typedef struct _ADDR_CONVERT_TILEINDEX1_INPUT 2194 { 2195 UINT_32 size; ///< Size of this structure in bytes 2196 2197 INT_32 tileIndex; ///< Tile index 2198 UINT_32 bpp; ///< Bits per pixel 2199 UINT_32 numSamples; ///< Number of samples 2200 BOOL_32 tileInfoHw; ///< Set to TRUE if client wants HW enum, otherwise actual 2201 } ADDR_CONVERT_TILEINDEX1_INPUT; 2202 2203 /** 2204 **************************************************************************************************** 2205 * AddrConvertTileIndex1 2206 * 2207 * @brief 2208 * Convert tile index to tile mode/type/info 2209 **************************************************************************************************** 2210 */ 2211 ADDR_E_RETURNCODE ADDR_API AddrConvertTileIndex1( 2212 ADDR_HANDLE hLib, 2213 const ADDR_CONVERT_TILEINDEX1_INPUT* pIn, 2214 ADDR_CONVERT_TILEINDEX_OUTPUT* pOut); 2215 2216 2217 2218 /** 2219 **************************************************************************************************** 2220 * ADDR_GET_TILEINDEX_INPUT 2221 * 2222 * @brief 2223 * Input structure for AddrGetTileIndex 2224 **************************************************************************************************** 2225 */ 2226 typedef struct _ADDR_GET_TILEINDEX_INPUT 2227 { 2228 UINT_32 size; ///< Size of this structure in bytes 2229 2230 AddrTileMode tileMode; ///< Tile mode 2231 AddrTileType tileType; ///< Tile-type: disp/non-disp/... 2232 ADDR_TILEINFO* pTileInfo; ///< Pointer to tile-info structure, can be NULL for linear/1D 2233 } ADDR_GET_TILEINDEX_INPUT; 2234 2235 /** 2236 **************************************************************************************************** 2237 * ADDR_GET_TILEINDEX_OUTPUT 2238 * 2239 * @brief 2240 * Output structure for AddrGetTileIndex 2241 **************************************************************************************************** 2242 */ 2243 typedef struct _ADDR_GET_TILEINDEX_OUTPUT 2244 { 2245 UINT_32 size; ///< Size of this structure in bytes 2246 2247 INT_32 index; ///< index in table 2248 } ADDR_GET_TILEINDEX_OUTPUT; 2249 2250 /** 2251 **************************************************************************************************** 2252 * AddrGetTileIndex 2253 * 2254 * @brief 2255 * Get the tiling mode index in table 2256 **************************************************************************************************** 2257 */ 2258 ADDR_E_RETURNCODE ADDR_API AddrGetTileIndex( 2259 ADDR_HANDLE hLib, 2260 const ADDR_GET_TILEINDEX_INPUT* pIn, 2261 ADDR_GET_TILEINDEX_OUTPUT* pOut); 2262 2263 2264 2265 /** 2266 **************************************************************************************************** 2267 * ADDR_PRT_INFO_INPUT 2268 * 2269 * @brief 2270 * Input structure for AddrComputePrtInfo 2271 **************************************************************************************************** 2272 */ 2273 typedef struct _ADDR_PRT_INFO_INPUT 2274 { 2275 AddrFormat format; ///< Surface format 2276 UINT_32 baseMipWidth; ///< Base mipmap width 2277 UINT_32 baseMipHeight; ///< Base mipmap height 2278 UINT_32 baseMipDepth; ///< Base mipmap depth 2279 UINT_32 numFrags; ///< Number of fragments, 2280 } ADDR_PRT_INFO_INPUT; 2281 2282 /** 2283 **************************************************************************************************** 2284 * ADDR_PRT_INFO_OUTPUT 2285 * 2286 * @brief 2287 * Input structure for AddrComputePrtInfo 2288 **************************************************************************************************** 2289 */ 2290 typedef struct _ADDR_PRT_INFO_OUTPUT 2291 { 2292 UINT_32 prtTileWidth; 2293 UINT_32 prtTileHeight; 2294 } ADDR_PRT_INFO_OUTPUT; 2295 2296 /** 2297 **************************************************************************************************** 2298 * AddrComputePrtInfo 2299 * 2300 * @brief 2301 * Compute prt surface related information 2302 **************************************************************************************************** 2303 */ 2304 ADDR_E_RETURNCODE ADDR_API AddrComputePrtInfo( 2305 ADDR_HANDLE hLib, 2306 const ADDR_PRT_INFO_INPUT* pIn, 2307 ADDR_PRT_INFO_OUTPUT* pOut); 2308 2309 2310 2311 //////////////////////////////////////////////////////////////////////////////////////////////////// 2312 // DCC key functions 2313 //////////////////////////////////////////////////////////////////////////////////////////////////// 2314 2315 /** 2316 **************************************************************************************************** 2317 * _ADDR_COMPUTE_DCCINFO_INPUT 2318 * 2319 * @brief 2320 * Input structure of AddrComputeDccInfo 2321 **************************************************************************************************** 2322 */ 2323 typedef struct _ADDR_COMPUTE_DCCINFO_INPUT 2324 { 2325 UINT_32 size; ///< Size of this structure in bytes 2326 UINT_32 bpp; ///< BitPP of color surface 2327 UINT_32 numSamples; ///< Sample number of color surface 2328 UINT_64 colorSurfSize; ///< Size of color surface to which dcc key is bound 2329 AddrTileMode tileMode; ///< Tile mode of color surface 2330 ADDR_TILEINFO tileInfo; ///< Tile info of color surface 2331 UINT_32 tileSwizzle; ///< Tile swizzle 2332 INT_32 tileIndex; ///< Tile index of color surface, 2333 ///< MUST be -1 if you don't want to use it 2334 ///< while the global useTileIndex is set to 1 2335 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 2336 ///< README: When tileIndex is not -1, this must be valid 2337 } ADDR_COMPUTE_DCCINFO_INPUT; 2338 2339 /** 2340 **************************************************************************************************** 2341 * ADDR_COMPUTE_DCCINFO_OUTPUT 2342 * 2343 * @brief 2344 * Output structure of AddrComputeDccInfo 2345 **************************************************************************************************** 2346 */ 2347 typedef struct _ADDR_COMPUTE_DCCINFO_OUTPUT 2348 { 2349 UINT_32 size; ///< Size of this structure in bytes 2350 UINT_32 dccRamBaseAlign; ///< Base alignment of dcc key 2351 UINT_64 dccRamSize; ///< Size of dcc key 2352 UINT_64 dccFastClearSize; ///< Size of dcc key portion that can be fast cleared 2353 BOOL_32 subLvlCompressible; ///< Whether sub resource is compressiable 2354 BOOL_32 dccRamSizeAligned; ///< Whether the dcc key size is aligned 2355 } ADDR_COMPUTE_DCCINFO_OUTPUT; 2356 2357 /** 2358 **************************************************************************************************** 2359 * AddrComputeDccInfo 2360 * 2361 * @brief 2362 * Compute DCC key size, base alignment 2363 * info 2364 **************************************************************************************************** 2365 */ 2366 ADDR_E_RETURNCODE ADDR_API AddrComputeDccInfo( 2367 ADDR_HANDLE hLib, 2368 const ADDR_COMPUTE_DCCINFO_INPUT* pIn, 2369 ADDR_COMPUTE_DCCINFO_OUTPUT* pOut); 2370 2371 2372 /** 2373 **************************************************************************************************** 2374 * ADDR_GET_MAX_ALIGNMENTS_OUTPUT 2375 * 2376 * @brief 2377 * Output structure of AddrGetMaxAlignments 2378 **************************************************************************************************** 2379 */ 2380 typedef struct ADDR_GET_MAX_ALINGMENTS_OUTPUT 2381 { 2382 UINT_32 size; ///< Size of this structure in bytes 2383 UINT_32 baseAlign; ///< Maximum base alignment in bytes 2384 } ADDR_GET_MAX_ALIGNMENTS_OUTPUT; 2385 2386 /** 2387 **************************************************************************************************** 2388 * AddrGetMaxAlignments 2389 * 2390 * @brief 2391 * Gets maximnum alignments 2392 **************************************************************************************************** 2393 */ 2394 ADDR_E_RETURNCODE ADDR_API AddrGetMaxAlignments( 2395 ADDR_HANDLE hLib, 2396 ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut); 2397 2398 /** 2399 **************************************************************************************************** 2400 * AddrGetMaxMetaAlignments 2401 * 2402 * @brief 2403 * Gets maximnum alignments for metadata 2404 **************************************************************************************************** 2405 */ 2406 ADDR_E_RETURNCODE ADDR_API AddrGetMaxMetaAlignments( 2407 ADDR_HANDLE hLib, 2408 ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut); 2409 2410 /** 2411 **************************************************************************************************** 2412 * Address library interface version 2 2413 * available from Gfx9 hardware 2414 **************************************************************************************************** 2415 * Addr2ComputeSurfaceInfo() 2416 * Addr2ComputeSurfaceAddrFromCoord() 2417 * Addr2ComputeSurfaceCoordFromAddr() 2418 2419 * Addr2ComputeHtileInfo() 2420 * Addr2ComputeHtileAddrFromCoord() 2421 * Addr2ComputeHtileCoordFromAddr() 2422 * 2423 * Addr2ComputeCmaskInfo() 2424 * Addr2ComputeCmaskAddrFromCoord() 2425 * Addr2ComputeCmaskCoordFromAddr() 2426 * 2427 * Addr2ComputeFmaskInfo() 2428 * Addr2ComputeFmaskAddrFromCoord() 2429 * Addr2ComputeFmaskCoordFromAddr() 2430 * 2431 * Addr2ComputeDccInfo() 2432 * 2433 **/ 2434 2435 2436 //////////////////////////////////////////////////////////////////////////////////////////////////// 2437 // Surface functions for Addr2 2438 //////////////////////////////////////////////////////////////////////////////////////////////////// 2439 2440 /** 2441 **************************************************************************************************** 2442 * ADDR2_SURFACE_FLAGS 2443 * 2444 * @brief 2445 * Surface flags 2446 **************************************************************************************************** 2447 */ 2448 typedef union _ADDR2_SURFACE_FLAGS 2449 { 2450 struct 2451 { 2452 UINT_32 color : 1; ///< This resource is a color buffer, can be used with RTV 2453 UINT_32 depth : 1; ///< Thie resource is a depth buffer, can be used with DSV 2454 UINT_32 stencil : 1; ///< Thie resource is a stencil buffer, can be used with DSV 2455 UINT_32 fmask : 1; ///< This is an fmask surface 2456 UINT_32 overlay : 1; ///< This is an overlay surface 2457 UINT_32 display : 1; ///< This resource is displayable, can be used with DRV 2458 UINT_32 prt : 1; ///< This is a partially resident texture 2459 UINT_32 qbStereo : 1; ///< This is a quad buffer stereo surface 2460 UINT_32 interleaved : 1; ///< Special flag for interleaved YUV surface padding 2461 UINT_32 texture : 1; ///< This resource can be used with SRV 2462 UINT_32 unordered : 1; ///< This resource can be used with UAV 2463 UINT_32 rotated : 1; ///< This resource is rotated and displayable 2464 UINT_32 needEquation : 1; ///< This resource needs equation to be generated if possible 2465 UINT_32 opt4space : 1; ///< This resource should be optimized for space 2466 UINT_32 minimizeAlign : 1; ///< This resource should use minimum alignment 2467 UINT_32 noMetadata : 1; ///< This resource has no metadata 2468 UINT_32 metaRbUnaligned : 1; ///< This resource has rb unaligned metadata 2469 UINT_32 metaPipeUnaligned : 1; ///< This resource has pipe unaligned metadata 2470 UINT_32 view3dAs2dArray : 1; ///< This resource is a 3D resource viewed as 2D array 2471 UINT_32 allowExtEquation : 1; ///< If unset, only legacy DX eqs are allowed (2 XORs) 2472 UINT_32 requireMetadata : 1; ///< This resource must support metadata 2473 UINT_32 reserved : 11; ///< Reserved bits 2474 }; 2475 2476 UINT_32 value; 2477 } ADDR2_SURFACE_FLAGS; 2478 2479 /** 2480 **************************************************************************************************** 2481 * ADDR2_COMPUTE_SURFACE_INFO_INPUT 2482 * 2483 * @brief 2484 * Input structure for Addr2ComputeSurfaceInfo 2485 **************************************************************************************************** 2486 */ 2487 typedef struct _ADDR2_COMPUTE_SURFACE_INFO_INPUT 2488 { 2489 UINT_32 size; ///< Size of this structure in bytes 2490 2491 ADDR2_SURFACE_FLAGS flags; ///< Surface flags 2492 AddrSwizzleMode swizzleMode; ///< Swizzle Mode for Addr2 2493 AddrResourceType resourceType; ///< Surface type 2494 AddrFormat format; ///< Surface format 2495 UINT_32 bpp; ///< bits per pixel 2496 UINT_32 width; ///< Width (of mip0), in pixels 2497 UINT_32 height; ///< Height (of mip0), in pixels 2498 UINT_32 numSlices; ///< Number surface slice/depth (of mip0), 2499 UINT_32 numMipLevels; ///< Total mipmap levels. 2500 UINT_32 numSamples; ///< Number of samples 2501 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 2502 /// number of samples for normal AA; Set it to the 2503 /// number of fragments for EQAA 2504 UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats) 2505 UINT_32 sliceAlign; ///< Required slice size in bytes 2506 } ADDR2_COMPUTE_SURFACE_INFO_INPUT; 2507 2508 /** 2509 **************************************************************************************************** 2510 * ADDR2_MIP_INFO 2511 * 2512 * @brief 2513 * Structure that contains information for mip level 2514 * 2515 **************************************************************************************************** 2516 */ 2517 typedef struct _ADDR2_MIP_INFO 2518 { 2519 UINT_32 pitch; ///< Pitch in elements 2520 UINT_32 height; ///< Padded height in elements 2521 UINT_32 depth; ///< Padded depth 2522 UINT_32 pixelPitch; ///< Pitch in pixels 2523 UINT_32 pixelHeight; ///< Padded height in pixels 2524 UINT_32 equationIndex; ///< Equation index in the equation table 2525 UINT_64 offset; ///< Offset in bytes from mip base, should only be used 2526 ///< to setup vam surface descriptor, can't be used 2527 ///< to setup swizzle pattern 2528 UINT_64 macroBlockOffset; ///< macro block offset in bytes from mip base 2529 UINT_32 mipTailOffset; ///< mip tail offset in bytes 2530 UINT_32 mipTailCoordX; ///< mip tail coord x 2531 UINT_32 mipTailCoordY; ///< mip tail coord y 2532 UINT_32 mipTailCoordZ; ///< mip tail coord z 2533 } ADDR2_MIP_INFO; 2534 2535 /** 2536 **************************************************************************************************** 2537 * ADDR2_COMPUTE_SURFACE_INFO_OUTPUT 2538 * 2539 * @brief 2540 * Output structure for Addr2ComputeSurfInfo 2541 * @note 2542 Element: AddrLib unit for computing. e.g. BCn: 4x4 blocks; R32B32B32: 32bit with 3x pitch 2543 Pixel: Original pixel 2544 **************************************************************************************************** 2545 */ 2546 typedef struct _ADDR2_COMPUTE_SURFACE_INFO_OUTPUT 2547 { 2548 UINT_32 size; ///< Size of this structure in bytes 2549 2550 UINT_32 pitch; ///< Pitch in elements (blocks for compressed formats) 2551 UINT_32 height; ///< Padded height (of mip0) in elements 2552 UINT_32 numSlices; ///< Padded depth for 3d resource 2553 ///< or padded number of slices for 2d array resource 2554 UINT_32 mipChainPitch; ///< Pitch (of total mip chain) in elements 2555 UINT_32 mipChainHeight; ///< Padded height (of total mip chain) in elements 2556 UINT_32 mipChainSlice; ///< Padded depth (of total mip chain) 2557 UINT_64 sliceSize; ///< Slice (total mip chain) size in bytes 2558 UINT_64 surfSize; ///< Surface (total mip chain) size in bytes 2559 UINT_32 baseAlign; ///< Base address alignment 2560 UINT_32 bpp; ///< Bits per elements 2561 /// (e.g. blocks for BCn, 1/3 for 96bit) 2562 UINT_32 pixelMipChainPitch; ///< Mip chain pitch in original pixels 2563 UINT_32 pixelMipChainHeight; ///< Mip chain height in original pixels 2564 UINT_32 pixelPitch; ///< Pitch in original pixels 2565 UINT_32 pixelHeight; ///< Height in original pixels 2566 UINT_32 pixelBits; ///< Original bits per pixel, passed from input 2567 2568 UINT_32 blockWidth; ///< Width in element inside one block 2569 UINT_32 blockHeight; ///< Height in element inside one block 2570 UINT_32 blockSlices; ///< Slice number inside one block 2571 ///< Prt tile is one block, its width/height/slice 2572 ///< equals to blcok width/height/slice 2573 2574 BOOL_32 epitchIsHeight; ///< Whether to use height to program epitch register 2575 /// Stereo info 2576 ADDR_QBSTEREOINFO* pStereoInfo; ///< Stereo info, needed if qbStereo flag is TRUE 2577 /// Mip info 2578 ADDR2_MIP_INFO* pMipInfo; ///< Pointer to mip information array 2579 /// if it is not NULL, the array is assumed to 2580 /// contain numMipLevels entries 2581 2582 UINT_32 equationIndex; ///< Equation index in the equation table of mip0 2583 BOOL_32 mipChainInTail; ///< If whole mipchain falls into mip tail block 2584 UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if there is no mip 2585 /// in tail, it will be set to number of mip levels 2586 } ADDR2_COMPUTE_SURFACE_INFO_OUTPUT; 2587 2588 /** 2589 **************************************************************************************************** 2590 * Addr2ComputeSurfaceInfo 2591 * 2592 * @brief 2593 * Compute surface width/height/slices/alignments and suitable tiling mode 2594 **************************************************************************************************** 2595 */ 2596 ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceInfo( 2597 ADDR_HANDLE hLib, 2598 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 2599 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut); 2600 2601 2602 2603 /** 2604 **************************************************************************************************** 2605 * ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT 2606 * 2607 * @brief 2608 * Input structure for Addr2ComputeSurfaceAddrFromCoord 2609 **************************************************************************************************** 2610 */ 2611 typedef struct _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT 2612 { 2613 UINT_32 size; ///< Size of this structure in bytes 2614 2615 UINT_32 x; ///< X coordinate 2616 UINT_32 y; ///< Y coordinate 2617 UINT_32 slice; ///< Slice index 2618 UINT_32 sample; ///< Sample index, use fragment index for EQAA 2619 UINT_32 mipId; ///< the mip ID in mip chain 2620 2621 AddrSwizzleMode swizzleMode; ///< Swizzle mode for Addr2 2622 ADDR2_SURFACE_FLAGS flags; ///< Surface flags 2623 AddrResourceType resourceType; ///< Surface type 2624 UINT_32 bpp; ///< Bits per pixel 2625 UINT_32 unalignedWidth; ///< Surface original width (of mip0) 2626 UINT_32 unalignedHeight; ///< Surface original height (of mip0) 2627 UINT_32 numSlices; ///< Surface original slices (of mip0) 2628 UINT_32 numMipLevels; ///< Total mipmap levels 2629 UINT_32 numSamples; ///< Number of samples 2630 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 2631 /// number of samples for normal AA; Set it to the 2632 /// number of fragments for EQAA 2633 2634 UINT_32 pipeBankXor; ///< Combined swizzle used to do bank/pipe rotation 2635 UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats) 2636 } ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT; 2637 2638 /** 2639 **************************************************************************************************** 2640 * ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT 2641 * 2642 * @brief 2643 * Output structure for Addr2ComputeSurfaceAddrFromCoord 2644 **************************************************************************************************** 2645 */ 2646 typedef struct _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT 2647 { 2648 UINT_32 size; ///< Size of this structure in bytes 2649 2650 UINT_64 addr; ///< Byte offset from the image starting address 2651 UINT_32 bitPosition; ///< Bit position within surfaceAddr, 0-7. 2652 /// For surface bpp < 8, e.g. FMT_1. 2653 UINT_32 prtBlockIndex; ///< Index of a PRT tile (64K block) 2654 } ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT; 2655 2656 /** 2657 **************************************************************************************************** 2658 * Addr2ComputeSurfaceAddrFromCoord 2659 * 2660 * @brief 2661 * Compute surface address from a given coordinate. 2662 **************************************************************************************************** 2663 */ 2664 ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceAddrFromCoord( 2665 ADDR_HANDLE hLib, 2666 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 2667 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut); 2668 2669 /** 2670 **************************************************************************************************** 2671 * ADDR2_COPY_MEMSURFACE_REGION 2672 * 2673 * @brief 2674 * Input structure for Addr2CopyMemToSurface and Addr2CopySurfaceToMem 2675 **************************************************************************************************** 2676 */ 2677 typedef struct _ADDR2_COPY_MEMSURFACE_REGION 2678 { 2679 UINT_32 size; ///< Size of this structure in bytes 2680 2681 UINT_32 x; ///< Starting X coordinate, in elements 2682 UINT_32 y; ///< Starting Y coordinate, in elements 2683 UINT_32 slice; ///< Starting slice index or Z coordinate, in elements 2684 UINT_32 mipId; ///< The mip ID in mip chain 2685 ADDR_EXTENT3D copyDims; ///< Size of the region to copy, in elements 2686 2687 void* pMem; ///< Pointer to memory to copy 2688 UINT_64 memRowPitch; ///< Pitch between rows in bytes 2689 UINT_64 memSlicePitch; ///< Pitch between array/depth slices in bytes 2690 } ADDR2_COPY_MEMSURFACE_REGION; 2691 2692 /** 2693 **************************************************************************************************** 2694 * ADDR2_COPY_MEMSURFACE_INPUT 2695 * 2696 * @brief 2697 * Input structure for Addr2CopyMemToSurface and Addr2CopySurfaceToMem 2698 **************************************************************************************************** 2699 */ 2700 typedef struct _ADDR2_COPY_MEMSURFACE_INPUT 2701 { 2702 UINT_32 size; ///< Size of this structure in bytes 2703 2704 AddrSwizzleMode swizzleMode; ///< Swizzle mode 2705 AddrFormat format; ///< Format 2706 ADDR2_SURFACE_FLAGS flags; ///< Surface flags 2707 AddrResourceType resourceType; ///< Surface type 2708 UINT_32 bpp; ///< Bits per pixel 2709 ADDR_EXTENT3D unAlignedDims; ///< Surface original dimensions (of mip0), in pixels 2710 UINT_32 numMipLevels; ///< Total mipmap levels 2711 UINT_32 numSamples; ///< Number of samples 2712 UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats) 2713 UINT_32 pbXor; ///< Xor value 2714 2715 void* pMappedSurface; ///< Pointer to the image surface, mapped to CPU memory 2716 BOOL_32 singleSubres; ///< Pointer is to the base of the subresource, not to the 2717 /// base of the surface image data. Requires: 2718 /// - copyDims.depth == 1 2719 /// - all copy regions target the same mip 2720 /// - all copy regions target the same slice/depth 2721 } ADDR2_COPY_MEMSURFACE_INPUT; 2722 2723 /** 2724 **************************************************************************************************** 2725 * Addr2CopyMemToSurface 2726 * 2727 * @brief 2728 * Copy an image region from memory to an uncompressed CPU-mapped surface 2729 **************************************************************************************************** 2730 */ 2731 ADDR_E_RETURNCODE ADDR_API Addr2CopyMemToSurface( 2732 ADDR_HANDLE hLib, 2733 const ADDR2_COPY_MEMSURFACE_INPUT* pIn, 2734 const ADDR2_COPY_MEMSURFACE_REGION* pRegions, 2735 UINT_32 regionCount 2736 ); 2737 2738 /** 2739 **************************************************************************************************** 2740 * Addr2CopySurfaceToMem 2741 * 2742 * @brief 2743 * Copy an image region from an uncompressed CPU-mapped surface to memory 2744 **************************************************************************************************** 2745 */ 2746 ADDR_E_RETURNCODE ADDR_API Addr2CopySurfaceToMem( 2747 ADDR_HANDLE hLib, 2748 const ADDR2_COPY_MEMSURFACE_INPUT* pIn, 2749 const ADDR2_COPY_MEMSURFACE_REGION* pRegions, 2750 UINT_32 regionCount 2751 ); 2752 2753 2754 /** 2755 **************************************************************************************************** 2756 * ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT 2757 * 2758 * @brief 2759 * Input structure for Addr2ComputeSurfaceCoordFromAddr 2760 **************************************************************************************************** 2761 */ 2762 typedef struct _ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT 2763 { 2764 UINT_32 size; ///< Size of this structure in bytes 2765 2766 UINT_64 addr; ///< Address in bytes 2767 UINT_32 bitPosition; ///< Bit position in addr. 0-7. for surface bpp < 8, 2768 /// e.g. FMT_1; 2769 2770 AddrSwizzleMode swizzleMode; ///< Swizzle mode for Addr2 2771 ADDR2_SURFACE_FLAGS flags; ///< Surface flags 2772 AddrResourceType resourceType; ///< Surface type 2773 UINT_32 bpp; ///< Bits per pixel 2774 UINT_32 unalignedWidth; ///< Surface original width (of mip0) 2775 UINT_32 unalignedHeight; ///< Surface original height (of mip0) 2776 UINT_32 numSlices; ///< Surface original slices (of mip0) 2777 UINT_32 numMipLevels; ///< Total mipmap levels. 2778 UINT_32 numSamples; ///< Number of samples 2779 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 2780 /// number of samples for normal AA; Set it to the 2781 /// number of fragments for EQAA 2782 2783 UINT_32 pipeBankXor; ///< Combined swizzle used to do bank/pipe rotation 2784 UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats) 2785 } ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT; 2786 2787 /** 2788 **************************************************************************************************** 2789 * ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT 2790 * 2791 * @brief 2792 * Output structure for Addr2ComputeSurfaceCoordFromAddr 2793 **************************************************************************************************** 2794 */ 2795 typedef struct _ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT 2796 { 2797 UINT_32 size; ///< Size of this structure in bytes 2798 2799 UINT_32 x; ///< X coordinate 2800 UINT_32 y; ///< Y coordinate 2801 UINT_32 slice; ///< Index of slices 2802 UINT_32 sample; ///< Index of samples, means fragment index for EQAA 2803 UINT_32 mipId; ///< mipmap level id 2804 } ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT; 2805 2806 /** 2807 **************************************************************************************************** 2808 * Addr2ComputeSurfaceCoordFromAddr 2809 * 2810 * @brief 2811 * Compute coordinate from a given surface address 2812 **************************************************************************************************** 2813 */ 2814 ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceCoordFromAddr( 2815 ADDR_HANDLE hLib, 2816 const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn, 2817 ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut); 2818 2819 2820 2821 //////////////////////////////////////////////////////////////////////////////////////////////////// 2822 // HTile functions for Addr2 2823 //////////////////////////////////////////////////////////////////////////////////////////////////// 2824 2825 /** 2826 **************************************************************************************************** 2827 * ADDR2_META_FLAGS 2828 * 2829 * @brief 2830 * Metadata flags 2831 **************************************************************************************************** 2832 */ 2833 typedef union _ADDR2_META_FLAGS 2834 { 2835 struct 2836 { 2837 UINT_32 pipeAligned : 1; ///< if Metadata being pipe aligned 2838 UINT_32 rbAligned : 1; ///< if Metadata being RB aligned 2839 UINT_32 linear : 1; ///< if Metadata linear, GFX9 does not suppord this! 2840 UINT_32 reserved : 29; ///< Reserved bits 2841 }; 2842 2843 UINT_32 value; 2844 } ADDR2_META_FLAGS; 2845 2846 /** 2847 **************************************************************************************************** 2848 * ADDR2_META_MIP_INFO 2849 * 2850 * @brief 2851 * Structure to store per mip metadata information 2852 **************************************************************************************************** 2853 */ 2854 typedef struct _ADDR2_META_MIP_INFO 2855 { 2856 BOOL_32 inMiptail; 2857 union 2858 { 2859 struct 2860 { 2861 UINT_32 startX; 2862 UINT_32 startY; 2863 UINT_32 startZ; 2864 UINT_32 width; 2865 UINT_32 height; 2866 UINT_32 depth; 2867 }; 2868 2869 // GFX10 2870 struct 2871 { 2872 UINT_32 offset; ///< Metadata offset within one slice, 2873 /// the thickness of a slice is meta block depth. 2874 UINT_32 sliceSize; ///< Metadata size within one slice, 2875 /// the thickness of a slice is meta block depth. 2876 }; 2877 }; 2878 } ADDR2_META_MIP_INFO; 2879 2880 /** 2881 **************************************************************************************************** 2882 * ADDR2_COMPUTE_HTILE_INFO_INPUT 2883 * 2884 * @brief 2885 * Input structure of Addr2ComputeHtileInfo 2886 **************************************************************************************************** 2887 */ 2888 typedef struct _ADDR2_COMPUTE_HTILE_INFO_INPUT 2889 { 2890 UINT_32 size; ///< Size of this structure in bytes 2891 2892 ADDR2_META_FLAGS hTileFlags; ///< HTILE flags 2893 ADDR2_SURFACE_FLAGS depthFlags; ///< Depth surface flags 2894 AddrSwizzleMode swizzleMode; ///< Depth surface swizzle mode 2895 UINT_32 unalignedWidth; ///< Depth surface original width (of mip0) 2896 UINT_32 unalignedHeight; ///< Depth surface original height (of mip0) 2897 UINT_32 numSlices; ///< Number of slices of depth surface (of mip0) 2898 UINT_32 numMipLevels; ///< Total mipmap levels of color surface 2899 UINT_32 firstMipIdInTail; /// Id of the first mip in tail, 2900 /// if no mip is in tail, it should be set to 2901 /// number of mip levels 2902 /// Only for GFX10 2903 } ADDR2_COMPUTE_HTILE_INFO_INPUT; 2904 2905 /** 2906 **************************************************************************************************** 2907 * ADDR2_COMPUTE_HTILE_INFO_OUTPUT 2908 * 2909 * @brief 2910 * Output structure of Addr2ComputeHtileInfo 2911 **************************************************************************************************** 2912 */ 2913 typedef struct _ADDR2_COMPUTE_HTILE_INFO_OUTPUT 2914 { 2915 UINT_32 size; ///< Size of this structure in bytes 2916 2917 UINT_32 pitch; ///< Pitch in pixels of depth buffer represented in this 2918 /// HTile buffer. This might be larger than original depth 2919 /// buffer pitch when called with an unaligned pitch. 2920 UINT_32 height; ///< Height in pixels, as above 2921 UINT_32 baseAlign; ///< Base alignment 2922 UINT_32 sliceSize; ///< Slice size, in bytes. 2923 UINT_32 htileBytes; ///< Size of HTILE buffer, in bytes 2924 UINT_32 metaBlkWidth; ///< Meta block width 2925 UINT_32 metaBlkHeight; ///< Meta block height 2926 UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice 2927 2928 ADDR2_META_MIP_INFO* pMipInfo; ///< HTILE mip information 2929 2930 struct { 2931 UINT_16* gfx10_bits; /* 72 2-byte elements */ 2932 } equation; 2933 } ADDR2_COMPUTE_HTILE_INFO_OUTPUT; 2934 2935 /** 2936 **************************************************************************************************** 2937 * Addr2ComputeHtileInfo 2938 * 2939 * @brief 2940 * Compute Htile pitch, height, base alignment and size in bytes 2941 **************************************************************************************************** 2942 */ 2943 ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileInfo( 2944 ADDR_HANDLE hLib, 2945 const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn, 2946 ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut); 2947 2948 2949 2950 /** 2951 **************************************************************************************************** 2952 * ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT 2953 * 2954 * @brief 2955 * Input structure for Addr2ComputeHtileAddrFromCoord 2956 **************************************************************************************************** 2957 */ 2958 typedef struct _ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT 2959 { 2960 UINT_32 size; ///< Size of this structure in bytes 2961 2962 UINT_32 x; ///< X coordinate 2963 UINT_32 y; ///< Y coordinate 2964 UINT_32 slice; ///< Index of slices 2965 UINT_32 mipId; ///< mipmap level id 2966 2967 ADDR2_META_FLAGS hTileFlags; ///< HTILE flags 2968 ADDR2_SURFACE_FLAGS depthflags; ///< Depth surface flags 2969 AddrSwizzleMode swizzleMode; ///< Depth surface swizzle mode 2970 UINT_32 bpp; ///< Depth surface bits per pixel 2971 UINT_32 unalignedWidth; ///< Depth surface original width (of mip0) 2972 UINT_32 unalignedHeight; ///< Depth surface original height (of mip0) 2973 UINT_32 numSlices; ///< Depth surface original depth (of mip0) 2974 UINT_32 numMipLevels; ///< Depth surface total mipmap levels 2975 UINT_32 numSamples; ///< Depth surface number of samples 2976 UINT_32 pipeXor; ///< Pipe xor setting 2977 } ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT; 2978 2979 /** 2980 **************************************************************************************************** 2981 * ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT 2982 * 2983 * @brief 2984 * Output structure for Addr2ComputeHtileAddrFromCoord 2985 **************************************************************************************************** 2986 */ 2987 typedef struct _ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT 2988 { 2989 UINT_32 size; ///< Size of this structure in bytes 2990 2991 UINT_64 addr; ///< Address in bytes 2992 } ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT; 2993 2994 /** 2995 **************************************************************************************************** 2996 * Addr2ComputeHtileAddrFromCoord 2997 * 2998 * @brief 2999 * Compute Htile address according to coordinates (of depth buffer) 3000 **************************************************************************************************** 3001 */ 3002 ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileAddrFromCoord( 3003 ADDR_HANDLE hLib, 3004 const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, 3005 ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut); 3006 3007 3008 3009 /** 3010 **************************************************************************************************** 3011 * ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT 3012 * 3013 * @brief 3014 * Input structure for Addr2ComputeHtileCoordFromAddr 3015 **************************************************************************************************** 3016 */ 3017 typedef struct _ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT 3018 { 3019 UINT_32 size; ///< Size of this structure in bytes 3020 3021 UINT_64 addr; ///< Address 3022 3023 ADDR2_META_FLAGS hTileFlags; ///< HTILE flags 3024 ADDR2_SURFACE_FLAGS depthFlags; ///< Depth surface flags 3025 AddrSwizzleMode swizzleMode; ///< Depth surface swizzle mode 3026 UINT_32 bpp; ///< Depth surface bits per pixel 3027 UINT_32 unalignedWidth; ///< Depth surface original width (of mip0) 3028 UINT_32 unalignedHeight; ///< Depth surface original height (of mip0) 3029 UINT_32 numSlices; ///< Depth surface original depth (of mip0) 3030 UINT_32 numMipLevels; ///< Depth surface total mipmap levels 3031 UINT_32 numSamples; ///< Depth surface number of samples 3032 UINT_32 pipeXor; ///< Pipe xor setting 3033 } ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT; 3034 3035 /** 3036 **************************************************************************************************** 3037 * ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT 3038 * 3039 * @brief 3040 * Output structure for Addr2ComputeHtileCoordFromAddr 3041 **************************************************************************************************** 3042 */ 3043 typedef struct _ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT 3044 { 3045 UINT_32 size; ///< Size of this structure in bytes 3046 3047 UINT_32 x; ///< X coordinate 3048 UINT_32 y; ///< Y coordinate 3049 UINT_32 slice; ///< Index of slices 3050 UINT_32 mipId; ///< mipmap level id 3051 } ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT; 3052 3053 /** 3054 **************************************************************************************************** 3055 * Addr2ComputeHtileCoordFromAddr 3056 * 3057 * @brief 3058 * Compute coordinates within depth buffer (1st pixel of a micro tile) according to 3059 * Htile address 3060 **************************************************************************************************** 3061 */ 3062 ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileCoordFromAddr( 3063 ADDR_HANDLE hLib, 3064 const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, 3065 ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut); 3066 3067 3068 3069 //////////////////////////////////////////////////////////////////////////////////////////////////// 3070 // C-mask functions for Addr2 3071 //////////////////////////////////////////////////////////////////////////////////////////////////// 3072 3073 /** 3074 **************************************************************************************************** 3075 * ADDR2_COMPUTE_CMASK_INFO_INPUT 3076 * 3077 * @brief 3078 * Input structure of Addr2ComputeCmaskInfo 3079 **************************************************************************************************** 3080 */ 3081 typedef struct _ADDR2_COMPUTE_CMASKINFO_INPUT 3082 { 3083 UINT_32 size; ///< Size of this structure in bytes 3084 3085 ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags 3086 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags 3087 AddrResourceType resourceType; ///< Color surface type 3088 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 3089 UINT_32 unalignedWidth; ///< Color surface original width 3090 UINT_32 unalignedHeight; ///< Color surface original height 3091 UINT_32 numSlices; ///< Number of slices of color buffer 3092 UINT_32 numMipLevels; ///< Number of mip levels 3093 UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if no mip is in tail, 3094 /// it should be number of mip levels 3095 /// Only for GFX10 3096 } ADDR2_COMPUTE_CMASK_INFO_INPUT; 3097 3098 /* DCC addr meta equation for GFX9. */ 3099 struct gfx9_addr_meta_equation { 3100 UINT_8 num_bits; 3101 3102 struct { 3103 struct { 3104 UINT_8 dim; /* 0..4 as index, 5 means invalid */ 3105 UINT_8 ord; /* 0..31 */ 3106 } coord[8]; /* 0..num_coords */ 3107 } bit[32]; /* 0..num_bits */ 3108 3109 UINT_8 numPipeBits; 3110 }; 3111 3112 /** 3113 **************************************************************************************************** 3114 * ADDR2_COMPUTE_CMASK_INFO_OUTPUT 3115 * 3116 * @brief 3117 * Output structure of Addr2ComputeCmaskInfo 3118 **************************************************************************************************** 3119 */ 3120 typedef struct _ADDR2_COMPUTE_CMASK_INFO_OUTPUT 3121 { 3122 UINT_32 size; ///< Size of this structure in bytes 3123 3124 UINT_32 pitch; ///< Pitch in pixels of color buffer which 3125 /// this Cmask matches. The size might be larger than 3126 /// original color buffer pitch when called with 3127 /// an unaligned pitch. 3128 UINT_32 height; ///< Height in pixels, as above 3129 UINT_32 baseAlign; ///< Base alignment 3130 UINT_32 sliceSize; ///< Slice size, in bytes. 3131 UINT_32 cmaskBytes; ///< Size in bytes of CMask buffer 3132 UINT_32 metaBlkWidth; ///< Meta block width 3133 UINT_32 metaBlkHeight; ///< Meta block height 3134 3135 UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice 3136 3137 ADDR2_META_MIP_INFO* pMipInfo; ///< CMASK mip information 3138 3139 /* The equation for doing CMASK address computations in shaders. */ 3140 union { 3141 /* This is chip-specific, and it varies with: 3142 * - resource type 3143 * - swizzle_mode 3144 * - bpp 3145 * - pipe_aligned 3146 * - rb_aligned 3147 */ 3148 struct gfx9_addr_meta_equation gfx9; 3149 3150 /* This is chip-specific, it requires 64KB_Z_X. */ 3151 UINT_16 *gfx10_bits; /* 68 2-byte elements */ 3152 } equation; 3153 } ADDR2_COMPUTE_CMASK_INFO_OUTPUT; 3154 3155 /** 3156 **************************************************************************************************** 3157 * Addr2ComputeCmaskInfo 3158 * 3159 * @brief 3160 * Compute Cmask pitch, height, base alignment and size in bytes from color buffer 3161 * info 3162 **************************************************************************************************** 3163 */ 3164 ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskInfo( 3165 ADDR_HANDLE hLib, 3166 const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn, 3167 ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut); 3168 3169 3170 3171 /** 3172 **************************************************************************************************** 3173 * ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT 3174 * 3175 * @brief 3176 * Input structure for Addr2ComputeCmaskAddrFromCoord 3177 * 3178 **************************************************************************************************** 3179 */ 3180 typedef struct _ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT 3181 { 3182 UINT_32 size; ///< Size of this structure in bytes 3183 3184 UINT_32 x; ///< X coordinate 3185 UINT_32 y; ///< Y coordinate 3186 UINT_32 slice; ///< Index of slices 3187 3188 ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags 3189 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags 3190 AddrResourceType resourceType; ///< Color surface type 3191 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 3192 3193 UINT_32 unalignedWidth; ///< Color surface original width (of mip0) 3194 UINT_32 unalignedHeight; ///< Color surface original height (of mip0) 3195 UINT_32 numSlices; ///< Color surface original slices (of mip0) 3196 3197 UINT_32 numSamples; ///< Color surfae sample number 3198 UINT_32 numFrags; ///< Color surface fragment number 3199 3200 UINT_32 pipeXor; ///< pipe Xor setting 3201 } ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT; 3202 3203 /** 3204 **************************************************************************************************** 3205 * ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT 3206 * 3207 * @brief 3208 * Output structure for Addr2ComputeCmaskAddrFromCoord 3209 **************************************************************************************************** 3210 */ 3211 typedef struct _ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT 3212 { 3213 UINT_32 size; ///< Size of this structure in bytes 3214 3215 UINT_64 addr; ///< CMASK address in bytes 3216 UINT_32 bitPosition; ///< Bit position within addr, 0 or 4 3217 } ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT; 3218 3219 /** 3220 **************************************************************************************************** 3221 * Addr2ComputeCmaskAddrFromCoord 3222 * 3223 * @brief 3224 * Compute Cmask address according to coordinates (of MSAA color buffer) 3225 **************************************************************************************************** 3226 */ 3227 ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskAddrFromCoord( 3228 ADDR_HANDLE hLib, 3229 const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, 3230 ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut); 3231 3232 3233 3234 /** 3235 **************************************************************************************************** 3236 * ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT 3237 * 3238 * @brief 3239 * Input structure for Addr2ComputeCmaskCoordFromAddr 3240 **************************************************************************************************** 3241 */ 3242 typedef struct _ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT 3243 { 3244 UINT_32 size; ///< Size of this structure in bytes 3245 3246 UINT_64 addr; ///< CMASK address in bytes 3247 UINT_32 bitPosition; ///< Bit position within addr, 0 or 4 3248 3249 ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags 3250 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags 3251 AddrResourceType resourceType; ///< Color surface type 3252 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 3253 3254 UINT_32 unalignedWidth; ///< Color surface original width (of mip0) 3255 UINT_32 unalignedHeight; ///< Color surface original height (of mip0) 3256 UINT_32 numSlices; ///< Color surface original slices (of mip0) 3257 UINT_32 numMipLevels; ///< Color surface total mipmap levels. 3258 } ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT; 3259 3260 /** 3261 **************************************************************************************************** 3262 * ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT 3263 * 3264 * @brief 3265 * Output structure for Addr2ComputeCmaskCoordFromAddr 3266 **************************************************************************************************** 3267 */ 3268 typedef struct _ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT 3269 { 3270 UINT_32 size; ///< Size of this structure in bytes 3271 3272 UINT_32 x; ///< X coordinate 3273 UINT_32 y; ///< Y coordinate 3274 UINT_32 slice; ///< Index of slices 3275 UINT_32 mipId; ///< mipmap level id 3276 } ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT; 3277 3278 /** 3279 **************************************************************************************************** 3280 * Addr2ComputeCmaskCoordFromAddr 3281 * 3282 * @brief 3283 * Compute coordinates within color buffer (1st pixel of a micro tile) according to 3284 * Cmask address 3285 **************************************************************************************************** 3286 */ 3287 ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskCoordFromAddr( 3288 ADDR_HANDLE hLib, 3289 const ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn, 3290 ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut); 3291 3292 3293 3294 //////////////////////////////////////////////////////////////////////////////////////////////////// 3295 // F-mask functions for Addr2 3296 //////////////////////////////////////////////////////////////////////////////////////////////////// 3297 3298 /** 3299 **************************************************************************************************** 3300 * ADDR2_FMASK_FLAGS 3301 * 3302 * @brief 3303 * FMASK flags 3304 **************************************************************************************************** 3305 */ 3306 typedef union _ADDR2_FMASK_FLAGS 3307 { 3308 struct 3309 { 3310 UINT_32 resolved : 1; ///< TRUE if this is a resolved fmask, used by H/W clients 3311 /// by H/W clients. S/W should always set it to FALSE. 3312 UINT_32 reserved : 31; ///< Reserved for future use. 3313 }; 3314 3315 UINT_32 value; 3316 } ADDR2_FMASK_FLAGS; 3317 3318 /** 3319 **************************************************************************************************** 3320 * ADDR2_COMPUTE_FMASK_INFO_INPUT 3321 * 3322 * @brief 3323 * Input structure for Addr2ComputeFmaskInfo 3324 **************************************************************************************************** 3325 */ 3326 typedef struct _ADDR2_COMPUTE_FMASK_INFO_INPUT 3327 { 3328 UINT_32 size; ///< Size of this structure in bytes 3329 3330 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 3331 UINT_32 unalignedWidth; ///< Color surface original width 3332 UINT_32 unalignedHeight; ///< Color surface original height 3333 UINT_32 numSlices; ///< Number of slices/depth 3334 UINT_32 numSamples; ///< Number of samples 3335 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 3336 /// number of samples for normal AA; Set it to the 3337 /// number of fragments for EQAA 3338 ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags 3339 } ADDR2_COMPUTE_FMASK_INFO_INPUT; 3340 3341 /** 3342 **************************************************************************************************** 3343 * ADDR2_COMPUTE_FMASK_INFO_OUTPUT 3344 * 3345 * @brief 3346 * Output structure for Addr2ComputeFmaskInfo 3347 **************************************************************************************************** 3348 */ 3349 typedef struct _ADDR2_COMPUTE_FMASK_INFO_OUTPUT 3350 { 3351 UINT_32 size; ///< Size of this structure in bytes 3352 3353 UINT_32 pitch; ///< Pitch of fmask in pixels 3354 UINT_32 height; ///< Height of fmask in pixels 3355 UINT_32 baseAlign; ///< Base alignment 3356 UINT_32 numSlices; ///< Slices of fmask 3357 UINT_32 fmaskBytes; ///< Size of fmask in bytes 3358 UINT_32 bpp; ///< Bits per pixel of FMASK is: number of bit planes 3359 UINT_32 numSamples; ///< Number of samples 3360 UINT_32 sliceSize; ///< Size of slice in bytes 3361 } ADDR2_COMPUTE_FMASK_INFO_OUTPUT; 3362 3363 /** 3364 **************************************************************************************************** 3365 * Addr2ComputeFmaskInfo 3366 * 3367 * @brief 3368 * Compute Fmask pitch/height/slices/alignments and size in bytes 3369 **************************************************************************************************** 3370 */ 3371 ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskInfo( 3372 ADDR_HANDLE hLib, 3373 const ADDR2_COMPUTE_FMASK_INFO_INPUT* pIn, 3374 ADDR2_COMPUTE_FMASK_INFO_OUTPUT* pOut); 3375 3376 3377 3378 /** 3379 **************************************************************************************************** 3380 * ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT 3381 * 3382 * @brief 3383 * Input structure for Addr2ComputeFmaskAddrFromCoord 3384 **************************************************************************************************** 3385 */ 3386 typedef struct _ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT 3387 { 3388 UINT_32 size; ///< Size of this structure in bytes 3389 3390 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 3391 UINT_32 x; ///< X coordinate 3392 UINT_32 y; ///< Y coordinate 3393 UINT_32 slice; ///< Slice index 3394 UINT_32 sample; ///< Sample index (fragment index for EQAA) 3395 UINT_32 plane; ///< Plane number 3396 3397 UINT_32 unalignedWidth; ///< Color surface original width 3398 UINT_32 unalignedHeight; ///< Color surface original height 3399 UINT_32 numSamples; ///< Number of samples 3400 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 3401 /// number of samples for normal AA; Set it to the 3402 /// number of fragments for EQAA 3403 UINT_32 tileSwizzle; ///< Combined swizzle used to do bank/pipe rotation 3404 3405 ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags 3406 } ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT; 3407 3408 /** 3409 **************************************************************************************************** 3410 * ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT 3411 * 3412 * @brief 3413 * Output structure for Addr2ComputeFmaskAddrFromCoord 3414 **************************************************************************************************** 3415 */ 3416 typedef struct _ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT 3417 { 3418 UINT_32 size; ///< Size of this structure in bytes 3419 3420 UINT_64 addr; ///< Fmask address 3421 UINT_32 bitPosition; ///< Bit position within fmaskAddr, 0-7. 3422 } ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT; 3423 3424 /** 3425 **************************************************************************************************** 3426 * Addr2ComputeFmaskAddrFromCoord 3427 * 3428 * @brief 3429 * Compute Fmask address according to coordinates (x,y,slice,sample,plane) 3430 **************************************************************************************************** 3431 */ 3432 ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskAddrFromCoord( 3433 ADDR_HANDLE hLib, 3434 const ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn, 3435 ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut); 3436 3437 3438 3439 /** 3440 **************************************************************************************************** 3441 * ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT 3442 * 3443 * @brief 3444 * Input structure for Addr2ComputeFmaskCoordFromAddr 3445 **************************************************************************************************** 3446 */ 3447 typedef struct _ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT 3448 { 3449 UINT_32 size; ///< Size of this structure in bytes 3450 3451 UINT_64 addr; ///< Address 3452 UINT_32 bitPosition; ///< Bit position within addr, 0-7. 3453 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 3454 3455 UINT_32 unalignedWidth; ///< Color surface original width 3456 UINT_32 unalignedHeight; ///< Color surface original height 3457 UINT_32 numSamples; ///< Number of samples 3458 UINT_32 numFrags; ///< Number of fragments 3459 3460 UINT_32 tileSwizzle; ///< Combined swizzle used to do bank/pipe rotation 3461 3462 ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags 3463 } ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT; 3464 3465 /** 3466 **************************************************************************************************** 3467 * ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT 3468 * 3469 * @brief 3470 * Output structure for Addr2ComputeFmaskCoordFromAddr 3471 **************************************************************************************************** 3472 */ 3473 typedef struct _ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT 3474 { 3475 UINT_32 size; ///< Size of this structure in bytes 3476 3477 UINT_32 x; ///< X coordinate 3478 UINT_32 y; ///< Y coordinate 3479 UINT_32 slice; ///< Slice index 3480 UINT_32 sample; ///< Sample index (fragment index for EQAA) 3481 UINT_32 plane; ///< Plane number 3482 } ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT; 3483 3484 /** 3485 **************************************************************************************************** 3486 * Addr2ComputeFmaskCoordFromAddr 3487 * 3488 * @brief 3489 * Compute FMASK coordinate from an given address 3490 **************************************************************************************************** 3491 */ 3492 ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskCoordFromAddr( 3493 ADDR_HANDLE hLib, 3494 const ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn, 3495 ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut); 3496 3497 3498 3499 //////////////////////////////////////////////////////////////////////////////////////////////////// 3500 // DCC key functions for Addr2 3501 //////////////////////////////////////////////////////////////////////////////////////////////////// 3502 3503 /** 3504 **************************************************************************************************** 3505 * _ADDR2_COMPUTE_DCCINFO_INPUT 3506 * 3507 * @brief 3508 * Input structure of Addr2ComputeDccInfo 3509 **************************************************************************************************** 3510 */ 3511 typedef struct _ADDR2_COMPUTE_DCCINFO_INPUT 3512 { 3513 UINT_32 size; ///< Size of this structure in bytes 3514 3515 ADDR2_META_FLAGS dccKeyFlags; ///< DCC key flags 3516 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags 3517 AddrResourceType resourceType; ///< Color surface type 3518 AddrSwizzleMode swizzleMode; ///< Color surface swizzle mode 3519 UINT_32 bpp; ///< bits per pixel 3520 UINT_32 unalignedWidth; ///< Color surface original width (of mip0) 3521 UINT_32 unalignedHeight; ///< Color surface original height (of mip0) 3522 UINT_32 numSlices; ///< Number of slices, of color surface (of mip0) 3523 UINT_32 numFrags; ///< Fragment number of color surface 3524 UINT_32 numMipLevels; ///< Total mipmap levels of color surface 3525 UINT_32 dataSurfaceSize; ///< The padded size of all slices and mip levels 3526 ///< useful in meta linear case 3527 UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if no mip is in tail, 3528 /// it should be number of mip levels 3529 /// Only for GFX10 3530 } ADDR2_COMPUTE_DCCINFO_INPUT; 3531 3532 /** 3533 **************************************************************************************************** 3534 * ADDR2_COMPUTE_DCCINFO_OUTPUT 3535 * 3536 * @brief 3537 * Output structure of Addr2ComputeDccInfo 3538 **************************************************************************************************** 3539 */ 3540 typedef struct _ADDR2_COMPUTE_DCCINFO_OUTPUT 3541 { 3542 UINT_32 size; ///< Size of this structure in bytes 3543 3544 UINT_32 dccRamBaseAlign; ///< Base alignment of dcc key 3545 UINT_32 dccRamSize; ///< Size of dcc key 3546 3547 UINT_32 pitch; ///< DCC surface mip chain pitch 3548 UINT_32 height; ///< DCC surface mip chain height 3549 UINT_32 depth; ///< DCC surface mip chain depth 3550 3551 UINT_32 compressBlkWidth; ///< DCC compress block width 3552 UINT_32 compressBlkHeight; ///< DCC compress block height 3553 UINT_32 compressBlkDepth; ///< DCC compress block depth 3554 3555 UINT_32 metaBlkWidth; ///< DCC meta block width 3556 UINT_32 metaBlkHeight; ///< DCC meta block height 3557 UINT_32 metaBlkDepth; ///< DCC meta block depth 3558 UINT_32 metaBlkSize; ///< DCC meta block size in bytes 3559 UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice 3560 3561 union 3562 { 3563 UINT_32 fastClearSizePerSlice; ///< Size of DCC within a slice should be fast cleared 3564 UINT_32 dccRamSliceSize; ///< DCC ram size per slice. For mipmap, it's 3565 /// the slize size of a mip chain, the thickness of a 3566 /// a slice is meta block depth 3567 /// Only for GFX10 3568 }; 3569 3570 ADDR2_META_MIP_INFO* pMipInfo; ///< DCC mip information 3571 3572 /* The equation for doing DCC address computations in shaders. */ 3573 union { 3574 /* This is chip-specific, and it varies with: 3575 * - resource type 3576 * - swizzle_mode 3577 * - bpp 3578 * - number of fragments 3579 * - pipe_aligned 3580 * - rb_aligned 3581 */ 3582 struct gfx9_addr_meta_equation gfx9; 3583 3584 /* This is chip-specific, it requires 64KB_R_X, and it varies with: 3585 * - bpp 3586 * - pipe_aligned 3587 */ 3588 UINT_16 *gfx10_bits; /* 68 2-byte elements */ 3589 } equation; 3590 } ADDR2_COMPUTE_DCCINFO_OUTPUT; 3591 3592 /** 3593 **************************************************************************************************** 3594 * Addr2ComputeDccInfo 3595 * 3596 * @brief 3597 * Compute DCC key size, base alignment 3598 * info 3599 **************************************************************************************************** 3600 */ 3601 ADDR_E_RETURNCODE ADDR_API Addr2ComputeDccInfo( 3602 ADDR_HANDLE hLib, 3603 const ADDR2_COMPUTE_DCCINFO_INPUT* pIn, 3604 ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut); 3605 3606 3607 /** 3608 **************************************************************************************************** 3609 * ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT 3610 * 3611 * @brief 3612 * Input structure for Addr2ComputeDccAddrFromCoord 3613 * 3614 **************************************************************************************************** 3615 */ 3616 typedef struct _ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT 3617 { 3618 UINT_32 size; ///< Size of this structure in bytes 3619 3620 UINT_32 x; ///< X coordinate 3621 UINT_32 y; ///< Y coordinate 3622 UINT_32 slice; ///< Index of slices 3623 UINT_32 sample; ///< Index of samples, means fragment index for EQAA 3624 UINT_32 mipId; ///< mipmap level id 3625 3626 ADDR2_META_FLAGS dccKeyFlags; ///< DCC flags 3627 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags 3628 AddrResourceType resourceType; ///< Color surface type 3629 AddrSwizzleMode swizzleMode; ///< Color surface swizzle mode 3630 UINT_32 bpp; ///< Color surface bits per pixel 3631 UINT_32 unalignedWidth; ///< Color surface original width (of mip0) 3632 UINT_32 unalignedHeight; ///< Color surface original height (of mip0) 3633 UINT_32 numSlices; ///< Color surface original slices (of mip0) 3634 UINT_32 numMipLevels; ///< Color surface mipmap levels 3635 UINT_32 numFrags; ///< Color surface fragment number 3636 3637 UINT_32 pipeXor; ///< pipe Xor setting 3638 UINT_32 pitch; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::pitch 3639 UINT_32 height; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::height 3640 UINT_32 compressBlkWidth; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::compressBlkWidth 3641 UINT_32 compressBlkHeight; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::compressBlkHeight 3642 UINT_32 compressBlkDepth; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::compressBlkDepth 3643 UINT_32 metaBlkWidth; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::metaBlkWidth 3644 UINT_32 metaBlkHeight; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::metaBlkHeight 3645 UINT_32 metaBlkDepth; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::metaBlkDepth 3646 UINT_32 dccRamSliceSize; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::dccRamSliceSize 3647 } ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT; 3648 3649 /** 3650 **************************************************************************************************** 3651 * ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT 3652 * 3653 * @brief 3654 * Output structure for Addr2ComputeDccAddrFromCoord 3655 **************************************************************************************************** 3656 */ 3657 typedef struct _ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT 3658 { 3659 UINT_32 size; ///< Size of this structure in bytes 3660 3661 UINT_64 addr; ///< DCC address in bytes 3662 } ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT; 3663 3664 /** 3665 **************************************************************************************************** 3666 * Addr2ComputeDccAddrFromCoord 3667 * 3668 * @brief 3669 * Compute DCC address according to coordinates (of MSAA color buffer) 3670 **************************************************************************************************** 3671 */ 3672 ADDR_E_RETURNCODE ADDR_API Addr2ComputeDccAddrFromCoord( 3673 ADDR_HANDLE hLib, 3674 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn, 3675 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut); 3676 3677 //////////////////////////////////////////////////////////////////////////////////////////////////// 3678 // Misc functions for Addr2 3679 //////////////////////////////////////////////////////////////////////////////////////////////////// 3680 3681 /** 3682 **************************************************************************************************** 3683 * ADDR2_COMPUTE_PIPEBANKXOR_INPUT 3684 * 3685 * @brief 3686 * Input structure of Addr2ComputePipebankXor 3687 **************************************************************************************************** 3688 */ 3689 typedef struct _ADDR2_COMPUTE_PIPEBANKXOR_INPUT 3690 { 3691 UINT_32 size; ///< Size of this structure in bytes 3692 UINT_32 surfIndex; ///< Input surface index 3693 ADDR2_SURFACE_FLAGS flags; ///< Surface flag 3694 AddrSwizzleMode swizzleMode; ///< Surface swizzle mode 3695 AddrResourceType resourceType; ///< Surface resource type 3696 AddrFormat format; ///< Surface format 3697 UINT_32 numSamples; ///< Number of samples 3698 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 3699 /// number of samples for normal AA; Set it to the 3700 /// number of fragments for EQAA 3701 } ADDR2_COMPUTE_PIPEBANKXOR_INPUT; 3702 3703 /** 3704 **************************************************************************************************** 3705 * ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT 3706 * 3707 * @brief 3708 * Output structure of Addr2ComputePipebankXor 3709 **************************************************************************************************** 3710 */ 3711 typedef struct _ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT 3712 { 3713 UINT_32 size; ///< Size of this structure in bytes 3714 UINT_32 pipeBankXor; ///< Pipe bank xor 3715 } ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT; 3716 3717 /** 3718 **************************************************************************************************** 3719 * Addr2ComputePipeBankXor 3720 * 3721 * @brief 3722 * Calculate a valid bank pipe xor value for client to use. 3723 **************************************************************************************************** 3724 */ 3725 ADDR_E_RETURNCODE ADDR_API Addr2ComputePipeBankXor( 3726 ADDR_HANDLE hLib, 3727 const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn, 3728 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut); 3729 3730 /** 3731 **************************************************************************************************** 3732 * ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT 3733 * 3734 * @brief 3735 * Input structure of Addr2ComputeSlicePipeBankXor 3736 **************************************************************************************************** 3737 */ 3738 typedef struct _ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT 3739 { 3740 UINT_32 size; ///< Size of this structure in bytes 3741 AddrSwizzleMode swizzleMode; ///< Surface swizzle mode 3742 AddrResourceType resourceType; ///< Surface resource type 3743 UINT_32 bpe; ///< bits per element (e.g. block size for BCn format) 3744 UINT_32 basePipeBankXor; ///< Base pipe bank xor 3745 UINT_32 slice; ///< Slice id 3746 UINT_32 numSamples; ///< Number of samples 3747 } ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT; 3748 3749 /** 3750 **************************************************************************************************** 3751 * ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT 3752 * 3753 * @brief 3754 * Output structure of Addr2ComputeSlicePipeBankXor 3755 **************************************************************************************************** 3756 */ 3757 typedef struct _ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT 3758 { 3759 UINT_32 size; ///< Size of this structure in bytes 3760 UINT_32 pipeBankXor; ///< Pipe bank xor 3761 } ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT; 3762 3763 /** 3764 **************************************************************************************************** 3765 * Addr2ComputeSlicePipeBankXor 3766 * 3767 * @brief 3768 * Calculate slice pipe bank xor value based on base pipe bank xor and slice id. 3769 **************************************************************************************************** 3770 */ 3771 ADDR_E_RETURNCODE ADDR_API Addr2ComputeSlicePipeBankXor( 3772 ADDR_HANDLE hLib, 3773 const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn, 3774 ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut); 3775 3776 /** 3777 **************************************************************************************************** 3778 * ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT 3779 * 3780 * @brief 3781 * Input structure of Addr2ComputeSubResourceOffsetForSwizzlePattern 3782 **************************************************************************************************** 3783 */ 3784 typedef struct _ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT 3785 { 3786 UINT_32 size; ///< Size of this structure in bytes 3787 AddrSwizzleMode swizzleMode; ///< Surface swizzle mode 3788 AddrResourceType resourceType; ///< Surface resource type 3789 UINT_32 pipeBankXor; ///< Per resource xor 3790 UINT_32 slice; ///< Slice id 3791 UINT_64 sliceSize; ///< Slice size of a mip chain 3792 UINT_64 macroBlockOffset; ///< Macro block offset, returned in ADDR2_MIP_INFO 3793 UINT_32 mipTailOffset; ///< Mip tail offset, returned in ADDR2_MIP_INFO 3794 } ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT; 3795 3796 /** 3797 **************************************************************************************************** 3798 * ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT 3799 * 3800 * @brief 3801 * Output structure of Addr2ComputeSubResourceOffsetForSwizzlePattern 3802 **************************************************************************************************** 3803 */ 3804 typedef struct _ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT 3805 { 3806 UINT_32 size; ///< Size of this structure in bytes 3807 UINT_64 offset; ///< offset 3808 } ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT; 3809 3810 /** 3811 **************************************************************************************************** 3812 * Addr2ComputeSubResourceOffsetForSwizzlePattern 3813 * 3814 * @brief 3815 * Calculate sub resource offset to support swizzle pattern. 3816 **************************************************************************************************** 3817 */ 3818 ADDR_E_RETURNCODE ADDR_API Addr2ComputeSubResourceOffsetForSwizzlePattern( 3819 ADDR_HANDLE hLib, 3820 const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn, 3821 ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut); 3822 3823 /** 3824 **************************************************************************************************** 3825 * ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT 3826 * 3827 * @brief 3828 * Input structure of Addr2ComputeNonBlockCompressedView 3829 **************************************************************************************************** 3830 */ 3831 typedef struct _ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT 3832 { 3833 UINT_32 size; ///< Size of this structure in bytes 3834 ADDR2_SURFACE_FLAGS flags; ///< Surface flags 3835 AddrSwizzleMode swizzleMode; ///< Swizzle Mode for Addr2 3836 AddrResourceType resourceType; ///< Surface type 3837 AddrFormat format; ///< Surface format 3838 UINT_32 width; ///< Width of mip0 in texels (not in compressed block) 3839 UINT_32 height; ///< Height of mip0 in texels (not in compressed block) 3840 UINT_32 numSlices; ///< Number surface slice/depth of mip0 3841 UINT_32 numMipLevels; ///< Total mipmap levels. 3842 UINT_32 pipeBankXor; ///< Combined swizzle used to do bank/pipe rotation 3843 UINT_32 slice; ///< Index of slice to view 3844 UINT_32 mipId; ///< Id of mip to view 3845 } ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT; 3846 3847 /** 3848 **************************************************************************************************** 3849 * ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT 3850 * 3851 * @brief 3852 * Output structure of Addr2ComputeNonBlockCompressedView 3853 **************************************************************************************************** 3854 */ 3855 typedef struct _ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT 3856 { 3857 UINT_32 size; ///< Size of this structure in bytes 3858 UINT_64 offset; ///< Offset shifted from resource base for the view 3859 UINT_32 pipeBankXor; ///< Pipe bank xor for the view 3860 UINT_32 unalignedWidth; ///< Mip0 width (in element) for the view 3861 UINT_32 unalignedHeight; ///< Mip0 height (in element) for the view 3862 UINT_32 numMipLevels; ///< Total mipmap levels for the view 3863 UINT_32 mipId; ///< Mip ID for the view 3864 } ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT; 3865 3866 /** 3867 **************************************************************************************************** 3868 * Addr2ComputeNonBlockCompressedView 3869 * 3870 * @brief 3871 * Compute non-block-compressed view for a given mipmap level/slice 3872 **************************************************************************************************** 3873 */ 3874 ADDR_E_RETURNCODE ADDR_API Addr2ComputeNonBlockCompressedView( 3875 ADDR_HANDLE hLib, 3876 const ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT* pIn, 3877 ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT* pOut); 3878 3879 /** 3880 **************************************************************************************************** 3881 * ADDR2_BLOCK_SET 3882 * 3883 * @brief 3884 * Bit field that defines block type 3885 **************************************************************************************************** 3886 */ 3887 typedef union _ADDR2_BLOCK_SET 3888 { 3889 struct 3890 { 3891 UINT_32 micro : 1; // 256B block for 2D resource 3892 UINT_32 macroThin4KB : 1; // Thin 4KB for 2D/3D resource 3893 UINT_32 macroThick4KB : 1; // Thick 4KB for 3D resource 3894 UINT_32 macroThin64KB : 1; // Thin 64KB for 2D/3D resource 3895 UINT_32 macroThick64KB : 1; // Thick 64KB for 3D resource 3896 UINT_32 var : 1; // VAR block 3897 UINT_32 : 1; 3898 UINT_32 linear : 1; // Linear block 3899 UINT_32 reserved : 24; 3900 }; 3901 3902 struct 3903 { 3904 UINT_32 : 5; 3905 UINT_32 thin256KB : 1; // Thin 256KB block 3906 UINT_32 thick256KB : 1; // Thick 256KB block 3907 UINT_32 : 25; 3908 } gfx11; 3909 3910 UINT_32 value; 3911 } ADDR2_BLOCK_SET; 3912 3913 /** 3914 **************************************************************************************************** 3915 * ADDR2_SWTYPE_SET 3916 * 3917 * @brief 3918 * Bit field that defines swizzle type 3919 **************************************************************************************************** 3920 */ 3921 typedef union _ADDR2_SWTYPE_SET 3922 { 3923 struct 3924 { 3925 UINT_32 sw_Z : 1; // SW_*_Z_* 3926 UINT_32 sw_S : 1; // SW_*_S_* 3927 UINT_32 sw_D : 1; // SW_*_D_* 3928 UINT_32 sw_R : 1; // SW_*_R_* 3929 UINT_32 reserved : 28; 3930 }; 3931 3932 UINT_32 value; 3933 } ADDR2_SWTYPE_SET; 3934 3935 /** 3936 **************************************************************************************************** 3937 * ADDR2_SWMODE_SET 3938 * 3939 * @brief 3940 * Bit field that defines swizzle type 3941 **************************************************************************************************** 3942 */ 3943 typedef union _ADDR2_SWMODE_SET 3944 { 3945 struct 3946 { 3947 UINT_32 swLinear : 1; 3948 UINT_32 sw256B_S : 1; 3949 UINT_32 sw256B_D : 1; 3950 UINT_32 sw256B_R : 1; 3951 UINT_32 sw4KB_Z : 1; 3952 UINT_32 sw4KB_S : 1; 3953 UINT_32 sw4KB_D : 1; 3954 UINT_32 sw4KB_R : 1; 3955 UINT_32 sw64KB_Z : 1; 3956 UINT_32 sw64KB_S : 1; 3957 UINT_32 sw64KB_D : 1; 3958 UINT_32 sw64KB_R : 1; 3959 UINT_32 swMiscDef12 : 1; 3960 UINT_32 swMiscDef13 : 1; 3961 UINT_32 swMiscDef14 : 1; 3962 UINT_32 swMiscDef15 : 1; 3963 UINT_32 sw64KB_Z_T : 1; 3964 UINT_32 sw64KB_S_T : 1; 3965 UINT_32 sw64KB_D_T : 1; 3966 UINT_32 sw64KB_R_T : 1; 3967 UINT_32 sw4KB_Z_X : 1; 3968 UINT_32 sw4KB_S_X : 1; 3969 UINT_32 sw4KB_D_X : 1; 3970 UINT_32 sw4KB_R_X : 1; 3971 UINT_32 sw64KB_Z_X : 1; 3972 UINT_32 sw64KB_S_X : 1; 3973 UINT_32 sw64KB_D_X : 1; 3974 UINT_32 sw64KB_R_X : 1; 3975 UINT_32 swMiscDef28 : 1; 3976 UINT_32 swMiscDef29 : 1; 3977 UINT_32 swMiscDef30 : 1; 3978 UINT_32 swMiscDef31 : 1; 3979 }; 3980 3981 struct 3982 { 3983 UINT_32 : 28; 3984 UINT_32 swVar_Z_X : 1; 3985 UINT_32 : 2; 3986 UINT_32 swVar_R_X : 1; 3987 } gfx10; 3988 3989 struct 3990 { 3991 UINT_32 : 28; 3992 UINT_32 sw256KB_Z_X : 1; 3993 UINT_32 sw256KB_S_X : 1; 3994 UINT_32 sw256KB_D_X : 1; 3995 UINT_32 sw256KB_R_X : 1; 3996 } gfx11; 3997 3998 UINT_32 value; 3999 } ADDR2_SWMODE_SET; 4000 4001 /** 4002 **************************************************************************************************** 4003 * ADDR2_GET_PREFERRED_SURF_SETTING_INPUT 4004 * 4005 * @brief 4006 * Input structure of Addr2GetPreferredSurfaceSetting 4007 **************************************************************************************************** 4008 */ 4009 typedef struct _ADDR2_GET_PREFERRED_SURF_SETTING_INPUT 4010 { 4011 UINT_32 size; ///< Size of this structure in bytes 4012 4013 ADDR2_SURFACE_FLAGS flags; ///< Surface flags 4014 AddrResourceType resourceType; ///< Surface type 4015 AddrFormat format; ///< Surface format 4016 AddrResrouceLocation resourceLoction; ///< Surface heap choice 4017 ADDR2_BLOCK_SET forbiddenBlock; ///< Client can use it to disable some block setting 4018 ///< such as linear for DXTn, tiled for YUV 4019 ADDR2_SWTYPE_SET preferredSwSet; ///< Client can use it to specify sw type(s) wanted 4020 BOOL_32 noXor; ///< Do not use xor mode for this resource 4021 UINT_32 bpp; ///< bits per pixel 4022 UINT_32 width; ///< Width (of mip0), in pixels 4023 UINT_32 height; ///< Height (of mip0), in pixels 4024 UINT_32 numSlices; ///< Number surface slice/depth (of mip0), 4025 UINT_32 numMipLevels; ///< Total mipmap levels. 4026 UINT_32 numSamples; ///< Number of samples 4027 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 4028 /// number of samples for normal AA; Set it to the 4029 /// number of fragments for EQAA 4030 UINT_32 maxAlign; ///< maximum base/size alignment requested by client 4031 UINT_32 minSizeAlign; ///< memory allocated for surface in client driver will 4032 /// be padded to multiple of this value (in bytes) 4033 DOUBLE memoryBudget; ///< Memory consumption ratio based on minimum possible 4034 /// size. 4035 } ADDR2_GET_PREFERRED_SURF_SETTING_INPUT; 4036 4037 /** 4038 **************************************************************************************************** 4039 * ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT 4040 * 4041 * @brief 4042 * Output structure of Addr2GetPreferredSurfaceSetting 4043 **************************************************************************************************** 4044 */ 4045 typedef struct _ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT 4046 { 4047 UINT_32 size; ///< Size of this structure in bytes 4048 4049 AddrSwizzleMode swizzleMode; ///< Suggested swizzle mode to be used 4050 AddrResourceType resourceType; ///< Suggested resource type to program HW 4051 ADDR2_BLOCK_SET validBlockSet; ///< Valid block type bit conbination 4052 BOOL_32 canXor; ///< If client can use xor on a valid macro block 4053 /// type 4054 ADDR2_SWTYPE_SET validSwTypeSet; ///< Valid swizzle type bit combination 4055 ADDR2_SWTYPE_SET clientPreferredSwSet; ///< Client-preferred swizzle type bit combination 4056 ADDR2_SWMODE_SET validSwModeSet; ///< Valid swizzle mode bit combination 4057 } ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT; 4058 4059 /** 4060 **************************************************************************************************** 4061 * Addr2GetPreferredSurfaceSetting 4062 * 4063 * @brief 4064 * Suggest a preferred setting for client driver to program HW register 4065 **************************************************************************************************** 4066 */ 4067 ADDR_E_RETURNCODE ADDR_API Addr2GetPreferredSurfaceSetting( 4068 ADDR_HANDLE hLib, 4069 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn, 4070 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut); 4071 4072 /** 4073 **************************************************************************************************** 4074 * Addr2GetPossibleSwizzleModes 4075 * 4076 * @brief 4077 * Returns a list of swizzle modes that are valid from the hardware's perspective for the 4078 * client to choose from 4079 **************************************************************************************************** 4080 */ 4081 ADDR_E_RETURNCODE ADDR_API Addr2GetPossibleSwizzleModes( 4082 ADDR_HANDLE hLib, 4083 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn, 4084 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut); 4085 4086 /** 4087 **************************************************************************************************** 4088 * Addr2IsValidDisplaySwizzleMode 4089 * 4090 * @brief 4091 * Return whether the swizzle mode is supported by display engine 4092 pResult: whether it is displayAble or not for the given displaySwizzleMode 4093 **************************************************************************************************** 4094 */ 4095 ADDR_E_RETURNCODE ADDR_API Addr2IsValidDisplaySwizzleMode( 4096 ADDR_HANDLE hLib, 4097 AddrSwizzleMode swizzleMode, 4098 UINT_32 bpp, 4099 BOOL_32 *pResult); 4100 4101 /** 4102 **************************************************************************************************** 4103 * Addr2GetAllowedBlockSet 4104 * 4105 * @brief 4106 * Returns the set of allowed block sizes given the allowed swizzle modes and resource type 4107 **************************************************************************************************** 4108 */ 4109 ADDR_E_RETURNCODE ADDR_API Addr2GetAllowedBlockSet( 4110 ADDR_HANDLE hLib, 4111 ADDR2_SWMODE_SET allowedSwModeSet, 4112 AddrResourceType rsrcType, 4113 ADDR2_BLOCK_SET* pAllowedBlockSet); 4114 4115 /** 4116 **************************************************************************************************** 4117 * Addr2GetAllowedSwSet 4118 * 4119 * @brief 4120 * Returns the set of allowed swizzle types given the allowed swizzle modes 4121 **************************************************************************************************** 4122 */ 4123 ADDR_E_RETURNCODE ADDR_API Addr2GetAllowedSwSet( 4124 ADDR_HANDLE hLib, 4125 ADDR2_SWMODE_SET allowedSwModeSet, 4126 ADDR2_SWTYPE_SET* pAllowedSwSet); 4127 4128 /** 4129 **************************************************************************************************** 4130 * Addr2IsBlockTypeAvailable 4131 * 4132 * @brief 4133 * Determine whether a block type is allowed in a given blockSet 4134 **************************************************************************************************** 4135 */ 4136 BOOL_32 Addr2IsBlockTypeAvailable(ADDR2_BLOCK_SET blockSet, AddrBlockType blockType); 4137 4138 /** 4139 **************************************************************************************************** 4140 * Addr2BlockTypeWithinMemoryBudget 4141 * 4142 * @brief 4143 * Determine whether a new block type is acceptable based on memory waste ratio. Will favor 4144 * larger block types. 4145 **************************************************************************************************** 4146 */ 4147 BOOL_32 Addr2BlockTypeWithinMemoryBudget( 4148 UINT_64 minSize, 4149 UINT_64 newBlockTypeSize, 4150 UINT_32 ratioLow, 4151 UINT_32 ratioHi, 4152 #if defined(__cplusplus) 4153 DOUBLE memoryBudget = 0.0f, 4154 BOOL_32 newBlockTypeBigger = TRUE); 4155 #else 4156 DOUBLE memoryBudget, 4157 BOOL_32 newBlockTypeBigger); 4158 #endif 4159 4160 /** 4161 **************************************************************************************************** 4162 * ADDR3_SURFACE_FLAGS 4163 * 4164 * @brief 4165 * Surface flags 4166 **************************************************************************************************** 4167 */ 4168 typedef union _ADDR3_SURFACE_FLAGS 4169 { 4170 struct 4171 { 4172 UINT_32 depth : 1; ///< This resource is a depth buffer, can be used with DSV 4173 UINT_32 stencil : 1; ///< This resource is a stencil buffer, can be used with DSV 4174 UINT_32 hiZHiS : 1; 4175 UINT_32 blockCompressed : 1; 4176 UINT_32 nv12 : 1; 4177 UINT_32 p010 : 1; 4178 UINT_32 view3dAs2dArray : 1; 4179 UINT_32 isVrsImage : 1; ///< This resource is a VRS source image 4180 UINT_32 standardPrt : 1; ///< This resource is a PRT resource with the specific block 4181 /// dimensions that some APIs want 4182 UINT_32 reserved1 : 2; 4183 UINT_32 denseSliceExact : 1; ///< Pad dimensions such that 4184 /// Pow2Align(pitch*height, surfAlign)==pitch*height 4185 UINT_32 qbStereo : 1; ///< Quad buffer stereo surface 4186 UINT_32 display : 1; ///< This resource is displayable, can be used with DRV 4187 UINT_32 reserved : 18; ///< Reserved bits 4188 }; 4189 4190 UINT_32 value; 4191 } ADDR3_SURFACE_FLAGS; 4192 4193 /** 4194 **************************************************************************************************** 4195 * ADDR3_COMPUTE_SURFACE_INFO_INPUT 4196 * 4197 * @brief 4198 * Input structure for Addr3ComputeSurfaceInfo 4199 **************************************************************************************************** 4200 */ 4201 typedef struct _ADDR3_COMPUTE_SURFACE_INFO_INPUT 4202 { 4203 UINT_32 size; ///< Size of this structure in bytes 4204 4205 ADDR3_SURFACE_FLAGS flags; ///< Surface flags 4206 Addr3SwizzleMode swizzleMode; ///< Swizzle Mode for Gfx12 4207 AddrResourceType resourceType; ///< Surface type 4208 AddrFormat format; ///< Surface format 4209 UINT_32 bpp; ///< bits per pixel 4210 UINT_32 width; ///< Width (of mip0), in pixels 4211 UINT_32 height; ///< Height (of mip0), in pixels 4212 UINT_32 numSlices; ///< Number surface slice/depth (of mip0), 4213 UINT_32 numMipLevels; ///< Total mipmap levels. 4214 UINT_32 numSamples; ///< Number of samples 4215 UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats) 4216 UINT_32 sliceAlign; ///< Required slice size in bytes 4217 } ADDR3_COMPUTE_SURFACE_INFO_INPUT; 4218 4219 /** 4220 **************************************************************************************************** 4221 * ADDR3_MIP_INFO 4222 * 4223 * @brief 4224 * Structure that contains information for mip level 4225 * 4226 **************************************************************************************************** 4227 */ 4228 typedef struct _ADDR3_MIP_INFO 4229 { 4230 UINT_32 pitch; ///< Pitch in elements of image data 4231 UINT_32 pitchForSlice; ///< Pitch in elements used to compute slice size 4232 UINT_32 height; ///< Padded height in elements 4233 UINT_32 depth; ///< Padded depth 4234 UINT_32 pixelPitch; ///< Pitch in pixels for image data 4235 UINT_32 pixelHeight; ///< Padded height in pixels 4236 UINT_32 equationIndex; ///< Equation index in the equation table 4237 UINT_64 offset; ///< Offset in bytes from mip base, should only be used 4238 ///< to setup vam surface descriptor, can't be used 4239 ///< to setup swizzle pattern 4240 UINT_64 macroBlockOffset; ///< macro block offset in bytes from mip base 4241 UINT_32 mipTailOffset; ///< mip tail offset in bytes 4242 UINT_32 mipTailCoordX; ///< mip tail coord x 4243 UINT_32 mipTailCoordY; ///< mip tail coord y 4244 UINT_32 mipTailCoordZ; ///< mip tail coord z 4245 } ADDR3_MIP_INFO; 4246 4247 /** 4248 **************************************************************************************************** 4249 * ADDR3_COMPUTE_SURFACE_INFO_OUTPUT 4250 * 4251 * @brief 4252 * Output structure for Addr3ComputeSurfaceInfo 4253 * @note 4254 Element: AddrLib unit for computing. e.g. BCn: 4x4 blocks; R32B32B32: 32bit with 3x pitch 4255 Pixel: Original pixel 4256 **************************************************************************************************** 4257 */ 4258 typedef struct _ADDR3_COMPUTE_SURFACE_INFO_OUTPUT 4259 { 4260 UINT_32 size; ///< Size of this structure in bytes 4261 UINT_32 pitch; ///< Pitch in elements for image data 4262 UINT_32 pitchForSlice; ///< Pitch in elements used to compute slice size 4263 UINT_32 pixelPitch; ///< Pitch in original pixels 4264 UINT_32 pixelHeight; ///< Height in original pixels 4265 UINT_32 pixelBits; ///< Original bits per pixel, passed from input 4266 UINT_32 bpp; ///< Bits per elements 4267 /// (e.g. blocks for BCn, 1/3 for 96bit) 4268 UINT_32 numSlices; ///< Padded depth for 3d resource 4269 /// or padded number of slices for 2d array resource 4270 UINT_32 height; ///< Padded height (of mip0) in elements 4271 UINT_64 sliceSize; ///< Slice (total mip chain) size in bytes 4272 UINT_64 sliceSizeDensePacked; ///< Slice (total mip chain) size of image data in bytes 4273 UINT_64 surfSize; ///< Surface (total mip chain) size in bytes 4274 UINT_32 baseAlign; ///< Base address alignment 4275 ADDR_EXTENT3D blockExtent; ///< Dimensions in element inside one block 4276 UINT_32 pixelMipChainPitch; ///< Mip chain pitch in original pixels 4277 UINT_32 pixelMipChainHeight; ///< Mip chain height in original pixels 4278 ADDR3_MIP_INFO* pMipInfo; ///< Info regarding the start, sizes of the mip levels 4279 BOOL_32 mipChainInTail; ///< If whole mipchain falls into mip tail block 4280 UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if there is no mip 4281 /// in tail, it will be set to number of mip levels 4282 /// Stereo info 4283 ADDR_QBSTEREOINFO* pStereoInfo; ///< Stereo info, needed if qbStereo flag is TRUE 4284 } ADDR3_COMPUTE_SURFACE_INFO_OUTPUT; 4285 4286 /** 4287 **************************************************************************************************** 4288 * ADDR3_SWMODE_SET 4289 * 4290 * @brief 4291 * Bit field that defines swizzle type 4292 **************************************************************************************************** 4293 */ 4294 // The bit order MUST be the same as Addr3SwizzleMode enumerations, otherwise using bitset to enable 4295 // or disable swizzle modes will be problematic. 4296 typedef union _ADDR3_SWMODE_SET 4297 { 4298 struct 4299 { 4300 UINT_32 swLinear : 1; 4301 UINT_32 sw2d256B : 1; 4302 UINT_32 sw2d4kB : 1; 4303 UINT_32 sw2d64kB : 1; 4304 UINT_32 sw2d256kB : 1; 4305 UINT_32 sw3d4kB : 1; 4306 UINT_32 sw3d64kB : 1; 4307 UINT_32 sw3d256kB : 1; 4308 UINT_32 reserved1 : 2; 4309 UINT_32 reserved : 22; 4310 }; 4311 4312 UINT_32 value; 4313 } ADDR3_SWMODE_SET; 4314 4315 /** 4316 **************************************************************************************************** 4317 * ADDR3_GET_POSSIBLE_SWIZZLE_MODE_INPUT 4318 * 4319 * @brief 4320 * Input structure of Addr3GetPossibleSwizzleModes 4321 **************************************************************************************************** 4322 */ 4323 typedef struct _ADDR3_GET_POSSIBLE_SWIZZLE_MODE_INPUT 4324 { 4325 UINT_32 size; ///< Size of this structure in bytes 4326 4327 ADDR3_SURFACE_FLAGS flags; ///< Surface flags 4328 AddrResourceType resourceType; ///< Surface type 4329 UINT_32 bpp; ///< bits per pixel 4330 UINT_32 width; ///< Width (of mip0), in pixels 4331 UINT_32 height; ///< Height (of mip0), in pixels 4332 UINT_32 numSlices; ///< Number surface slice/depth (of mip0), 4333 UINT_32 numMipLevels; ///< Total mipmap levels. 4334 UINT_32 numSamples; ///< Number of samples 4335 UINT_32 maxAlign; ///< maximum base/size alignment requested by client 4336 } ADDR3_GET_POSSIBLE_SWIZZLE_MODE_INPUT; 4337 4338 /** 4339 **************************************************************************************************** 4340 * ADDR3_GET_POSSIBLE_SWIZZLE_MODE_OUTPUT 4341 * 4342 * @brief 4343 * Output structure of Addr3GetPossibleSwizzleModes 4344 **************************************************************************************************** 4345 */ 4346 typedef struct _ADDR3_GET_POSSIBLE_SWIZZLE_MODE_OUTPUT 4347 { 4348 UINT_32 size; ///< Size of this structure in bytes 4349 ADDR3_SWMODE_SET validModes; ///< List of valid swizzle modes for this function. 4350 } ADDR3_GET_POSSIBLE_SWIZZLE_MODE_OUTPUT; 4351 4352 /** 4353 **************************************************************************************************** 4354 * Addr3ComputeSurfaceInfo 4355 * 4356 * @brief 4357 * Compute surface width/height/slices/alignments and suitable tiling mode 4358 **************************************************************************************************** 4359 */ 4360 ADDR_E_RETURNCODE ADDR_API Addr3ComputeSurfaceInfo( 4361 ADDR_HANDLE hLib, 4362 const ADDR3_COMPUTE_SURFACE_INFO_INPUT* pIn, 4363 ADDR3_COMPUTE_SURFACE_INFO_OUTPUT* pOut); 4364 4365 /** 4366 **************************************************************************************************** 4367 * Addr3GetPossibleSwizzleModes 4368 * 4369 * @brief 4370 * Returns a list of swizzle modes that are valid from the hardware's perspective for the 4371 * client to choose from 4372 **************************************************************************************************** 4373 */ 4374 ADDR_E_RETURNCODE ADDR_API Addr3GetPossibleSwizzleModes( 4375 ADDR_HANDLE hLib, 4376 const ADDR3_GET_POSSIBLE_SWIZZLE_MODE_INPUT* pIn, 4377 ADDR3_GET_POSSIBLE_SWIZZLE_MODE_OUTPUT* pOut); 4378 4379 /** 4380 **************************************************************************************************** 4381 * ADDR3_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT 4382 * 4383 * @brief 4384 * Input structure for Addr3ComputeSurfaceAddrFromCoord 4385 **************************************************************************************************** 4386 */ 4387 typedef struct _ADDR3_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT 4388 { 4389 UINT_32 size; ///< Size of this structure in bytes 4390 4391 UINT_32 x; ///< X coordinate 4392 UINT_32 y; ///< Y coordinate 4393 UINT_32 slice; ///< Slice index 4394 UINT_32 sample; ///< Sample index, use fragment index for EQAA 4395 UINT_32 mipId; ///< the mip ID in mip chain 4396 4397 Addr3SwizzleMode swizzleMode; ///< Swizzle mode for Gfx12 4398 ADDR3_SURFACE_FLAGS flags; ///< Surface flags 4399 AddrResourceType resourceType; ///< Surface type 4400 UINT_32 bpp; ///< Bits per pixel 4401 ADDR_EXTENT3D unAlignedDims; ///< Surface original dimensions (of mip0) 4402 UINT_32 numMipLevels; ///< Total mipmap levels 4403 UINT_32 numSamples; ///< Number of samples 4404 UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats) 4405 } ADDR3_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT; 4406 4407 /** 4408 **************************************************************************************************** 4409 * ADDR3_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT 4410 * 4411 * @brief 4412 * Output structure for Addr3ComputeSurfaceAddrFromCoord 4413 **************************************************************************************************** 4414 */ 4415 typedef struct _ADDR3_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT 4416 { 4417 UINT_32 size; ///< Size of this structure in bytes 4418 4419 UINT_64 addr; ///< Byte offset from the image starting address 4420 UINT_32 bitPosition; ///< Bit position within surfaceAddr, 0-7. 4421 /// For surface bpp < 8, e.g. FMT_1. 4422 UINT_32 prtBlockIndex; ///< Index of a PRT tile (64K block) 4423 } ADDR3_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT; 4424 4425 /** 4426 **************************************************************************************************** 4427 * Addr3ComputeSurfaceAddrFromCoord 4428 * 4429 * @brief 4430 * Compute surface address from a given coordinate. 4431 **************************************************************************************************** 4432 */ 4433 ADDR_E_RETURNCODE ADDR_API Addr3ComputeSurfaceAddrFromCoord( 4434 ADDR_HANDLE hLib, 4435 const ADDR3_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 4436 ADDR3_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut); 4437 4438 4439 /** 4440 **************************************************************************************************** 4441 * ADDR3_COPY_MEMSURFACE_REGION 4442 * 4443 * @brief 4444 * Input structure for Addr3CopyMemToSurface and Addr3CopySurfaceToMem 4445 **************************************************************************************************** 4446 */ 4447 typedef struct _ADDR3_COPY_MEMSURFACE_REGION 4448 { 4449 UINT_32 size; ///< Size of this structure in bytes 4450 4451 UINT_32 x; ///< Starting X coordinate, in elements 4452 UINT_32 y; ///< Starting Y coordinate, in elements 4453 UINT_32 slice; ///< Starting slice index or Z coordinate, in elements 4454 UINT_32 mipId; ///< The mip ID in mip chain 4455 ADDR_EXTENT3D copyDims; ///< Size of the region to copy, in elements 4456 4457 void* pMem; ///< Pointer to memory to copy 4458 UINT_64 memRowPitch; ///< Pitch between rows in bytes 4459 UINT_64 memSlicePitch; ///< Pitch between array/depth slices in bytes 4460 } ADDR3_COPY_MEMSURFACE_REGION; 4461 4462 /** 4463 **************************************************************************************************** 4464 * ADDR3_COPY_MEMSURFACE_INPUT 4465 * 4466 * @brief 4467 * Input structure for Addr3CopyMemToSurface and Addr3CopySurfaceToMem 4468 **************************************************************************************************** 4469 */ 4470 typedef struct _ADDR3_COPY_MEMSURFACE_INPUT 4471 { 4472 UINT_32 size; ///< Size of this structure in bytes 4473 4474 Addr3SwizzleMode swizzleMode; ///< Swizzle mode for Gfx12 4475 ADDR3_SURFACE_FLAGS flags; ///< Surface flags 4476 AddrFormat format; ///< Format 4477 AddrResourceType resourceType; ///< Surface type 4478 UINT_32 bpp; ///< Bits per pixel 4479 ADDR_EXTENT3D unAlignedDims; ///< Surface original dimensions (of mip0), in pixels 4480 UINT_32 numMipLevels; ///< Total mipmap levels 4481 UINT_32 numSamples; ///< Number of samples 4482 UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats) 4483 UINT_32 pbXor; ///< Xor value 4484 4485 void* pMappedSurface; ///< Pointer to the image surface, mapped to CPU memory 4486 BOOL_32 singleSubres; ///< Pointer is to the base of the subresource, not to the 4487 /// base of the surface image data. Requires: 4488 /// - copyDims.depth == 1 4489 /// - all copy regions target the same mip 4490 /// - all copy regions target the same slice/depth 4491 } ADDR3_COPY_MEMSURFACE_INPUT; 4492 4493 /** 4494 **************************************************************************************************** 4495 * Addr3CopyMemToSurface 4496 * 4497 * @brief 4498 * Copy an image region from memory to an uncompressed CPU-mapped surface 4499 **************************************************************************************************** 4500 */ 4501 ADDR_E_RETURNCODE ADDR_API Addr3CopyMemToSurface( 4502 ADDR_HANDLE hLib, 4503 const ADDR3_COPY_MEMSURFACE_INPUT* pIn, 4504 const ADDR3_COPY_MEMSURFACE_REGION* pRegions, 4505 UINT_32 regionCount 4506 ); 4507 4508 /** 4509 **************************************************************************************************** 4510 * Addr3CopySurfaceToMem 4511 * 4512 * @brief 4513 * Copy an image region from an uncompressed CPU-mapped surface to memory 4514 **************************************************************************************************** 4515 */ 4516 ADDR_E_RETURNCODE ADDR_API Addr3CopySurfaceToMem( 4517 ADDR_HANDLE hLib, 4518 const ADDR3_COPY_MEMSURFACE_INPUT* pIn, 4519 const ADDR3_COPY_MEMSURFACE_REGION* pRegions, 4520 UINT_32 regionCount 4521 ); 4522 4523 /** 4524 **************************************************************************************************** 4525 * ADDR3_COMPUTE_PIPEBANKXOR_INPUT 4526 * 4527 * @brief 4528 * Input structure of Addr3ComputePipebankXor 4529 **************************************************************************************************** 4530 */ 4531 typedef struct _ADDR3_COMPUTE_PIPEBANKXOR_INPUT 4532 { 4533 UINT_32 size; ///< Size of this structure in bytes 4534 UINT_32 surfIndex; ///< Input surface index 4535 Addr3SwizzleMode swizzleMode; ///< Surface swizzle mode 4536 } ADDR3_COMPUTE_PIPEBANKXOR_INPUT; 4537 4538 /** 4539 **************************************************************************************************** 4540 * ADDR3_COMPUTE_PIPEBANKXOR_OUTPUT 4541 * 4542 * @brief 4543 * Output structure of Addr3ComputePipebankXor 4544 **************************************************************************************************** 4545 */ 4546 typedef struct _ADDR3_COMPUTE_PIPEBANKXOR_OUTPUT 4547 { 4548 UINT_32 size; ///< Size of this structure in bytes 4549 UINT_32 pipeBankXor; ///< Pipe bank xor 4550 } ADDR3_COMPUTE_PIPEBANKXOR_OUTPUT; 4551 4552 /** 4553 **************************************************************************************************** 4554 * Addr3ComputePipeBankXor 4555 * 4556 * @brief 4557 * Calculate a valid bank pipe xor value for client to use. 4558 **************************************************************************************************** 4559 */ 4560 ADDR_E_RETURNCODE ADDR_API Addr3ComputePipeBankXor( 4561 ADDR_HANDLE hLib, 4562 const ADDR3_COMPUTE_PIPEBANKXOR_INPUT* pIn, 4563 ADDR3_COMPUTE_PIPEBANKXOR_OUTPUT* pOut); 4564 4565 /** 4566 **************************************************************************************************** 4567 * ADDR3_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT 4568 * 4569 * @brief 4570 * Input structure of Addr3ComputeNonBlockCompressedView 4571 **************************************************************************************************** 4572 */ 4573 typedef struct _ADDR3_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT 4574 { 4575 UINT_32 size; ///< Size of this structure in bytes 4576 ADDR3_SURFACE_FLAGS flags; ///< Surface flags 4577 Addr3SwizzleMode swizzleMode; ///< Swizzle Mode for Gfx12 4578 AddrResourceType resourceType; ///< Surface type 4579 AddrFormat format; ///< Surface format 4580 ADDR_EXTENT3D unAlignedDims; ///< Surface original dimensions (of mip0) 4581 UINT_32 numMipLevels; ///< Total mipmap levels. 4582 UINT_32 pipeBankXor; ///< Combined swizzle used to do bank/pipe rotation 4583 UINT_32 slice; ///< Index of slice to view 4584 UINT_32 mipId; ///< Id of mip to view 4585 } ADDR3_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT; 4586 4587 /** 4588 **************************************************************************************************** 4589 * ADDR3_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT 4590 * 4591 * @brief 4592 * Output structure of Addr3ComputeNonBlockCompressedView 4593 **************************************************************************************************** 4594 */ 4595 typedef struct _ADDR3_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT 4596 { 4597 UINT_32 size; ///< Size of this structure in bytes 4598 UINT_64 offset; ///< Offset from resource base for the view 4599 UINT_32 pipeBankXor; ///< Pipe bank xor for the view 4600 ADDR_EXTENT3D unAlignedDims; ///< Mip0 dimens (in element) for the view 4601 UINT_32 numMipLevels; ///< Total mipmap levels for the view 4602 UINT_32 mipId; ///< Mip ID for the view 4603 } ADDR3_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT; 4604 4605 /** 4606 **************************************************************************************************** 4607 * Addr3ComputeNonBlockCompressedView 4608 * 4609 * @brief 4610 * Compute non-block-compressed view for a given mipmap level/slice 4611 **************************************************************************************************** 4612 */ 4613 ADDR_E_RETURNCODE ADDR_API Addr3ComputeNonBlockCompressedView( 4614 ADDR_HANDLE hLib, 4615 const ADDR3_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT* pIn, 4616 ADDR3_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT* pOut); 4617 4618 /** 4619 **************************************************************************************************** 4620 * ADDR3_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT 4621 * 4622 * @brief 4623 * Input structure of Addr3ComputeSubResourceOffsetForSwizzlePattern 4624 **************************************************************************************************** 4625 */ 4626 typedef struct _ADDR3_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT 4627 { 4628 UINT_32 size; ///< Size of this structure in bytes 4629 Addr3SwizzleMode swizzleMode; ///< Surface swizzle mode 4630 AddrResourceType resourceType; ///< Surface resource type 4631 UINT_32 pipeBankXor; ///< Per resource xor 4632 UINT_32 slice; ///< Slice id 4633 UINT_64 sliceSize; ///< Slice size of a mip chain 4634 UINT_64 macroBlockOffset; ///< Macro block offset, returned in ADDR3_MIP_INFO 4635 UINT_32 mipTailOffset; ///< Mip tail offset, returned in ADDR3_MIP_INFO 4636 } ADDR3_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT; 4637 4638 /** 4639 **************************************************************************************************** 4640 * ADDR3_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT 4641 * 4642 * @brief 4643 * Output structure of Addr3ComputeSubResourceOffsetForSwizzlePattern 4644 **************************************************************************************************** 4645 */ 4646 typedef struct _ADDR3_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT 4647 { 4648 UINT_32 size; ///< Size of this structure in bytes 4649 UINT_64 offset; ///< offset 4650 } ADDR3_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT; 4651 4652 /** 4653 **************************************************************************************************** 4654 * Addr3ComputeSubResourceOffsetForSwizzlePattern 4655 * 4656 * @brief 4657 * Calculate sub resource offset to support swizzle pattern. 4658 **************************************************************************************************** 4659 */ 4660 ADDR_E_RETURNCODE ADDR_API Addr3ComputeSubResourceOffsetForSwizzlePattern( 4661 ADDR_HANDLE hLib, 4662 const ADDR3_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn, 4663 ADDR3_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut); 4664 4665 /** 4666 **************************************************************************************************** 4667 * ADDR3_COMPUTE_SLICE_PIPEBANKXOR_INPUT 4668 * 4669 * @brief 4670 * Input structure of Addr2ComputeSlicePipeBankXor 4671 **************************************************************************************************** 4672 */ 4673 typedef struct _ADDR3_COMPUTE_SLICE_PIPEBANKXOR_INPUT 4674 { 4675 UINT_32 size; ///< Size of this structure in bytes 4676 Addr3SwizzleMode swizzleMode; ///< Surface swizzle mode 4677 AddrResourceType resourceType; ///< Surface resource type 4678 UINT_32 bpe; ///< bits per element (e.g. block size for BCn format) 4679 UINT_32 basePipeBankXor; ///< Base pipe bank xor 4680 UINT_32 slice; ///< Slice id 4681 UINT_32 numSamples; ///< Number of samples 4682 } ADDR3_COMPUTE_SLICE_PIPEBANKXOR_INPUT; 4683 4684 /** 4685 **************************************************************************************************** 4686 * ADDR3_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT 4687 * 4688 * @brief 4689 * Output structure of Addr3ComputeSlicePipeBankXor 4690 **************************************************************************************************** 4691 */ 4692 typedef struct _ADDR3_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT 4693 { 4694 UINT_32 size; ///< Size of this structure in bytes 4695 UINT_32 pipeBankXor; ///< Pipe bank xor 4696 } ADDR3_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT; 4697 4698 /** 4699 **************************************************************************************************** 4700 * Addr3ComputeSlicePipeBankXor 4701 * 4702 * @brief 4703 * Calculate slice pipe bank xor value based on base pipe bank xor and slice id. 4704 **************************************************************************************************** 4705 */ 4706 ADDR_E_RETURNCODE ADDR_API Addr3ComputeSlicePipeBankXor( 4707 ADDR_HANDLE hLib, 4708 const ADDR3_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn, 4709 ADDR3_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut); 4710 4711 #if defined(__cplusplus) 4712 } 4713 #endif 4714 4715 #endif // __ADDR_INTERFACE_H__ 4716