1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ 2 3 #ifndef __SOC_MEDIATEK_MT8188_INCLUDE_SOC_ADDRESSMAP_H__ 4 #define __SOC_MEDIATEK_MT8188_INCLUDE_SOC_ADDRESSMAP_H__ 5 6 /* 7 * This file is created based on MT8188 Application Processor Registers 8 */ 9 10 enum { 11 MCUSYS_BASE = 0x0C530000, 12 MCUPM_SRAM_BASE = 0x0C540000, 13 MCUPM_CFG_BASE = 0x0C560000, 14 BUS_TRACE_MONITOR_BASE = 0x0D040000, 15 IO_PHYS = 0x10000000, 16 MCUCFG_BASE = MCUSYS_BASE + 0x00008000, 17 }; 18 19 enum { 20 CKSYS_BASE = IO_PHYS + 0x00000000, 21 INFRACFG_AO_BASE = IO_PHYS + 0x00001000, 22 GPIO_BASE = IO_PHYS + 0x00005000, 23 SPM_BASE = IO_PHYS + 0x00006000, 24 RGU_BASE = IO_PHYS + 0x00007000, 25 GPT_BASE = IO_PHYS + 0x00008000, 26 EINT_BASE = IO_PHYS + 0x0000B000, 27 APMIXED_BASE = IO_PHYS + 0x0000C000, 28 SYSTIMER_BASE = IO_PHYS + 0x00017000, 29 INFRACFG_AO_BCRM_BASE = IO_PHYS + 0x00022000, 30 INFRA_AO_DBUG_BASE = IO_PHYS + 0x00023000, 31 PMIF_SPI_BASE = IO_PHYS + 0x00024000, 32 PMICSPI_MST_BASE = IO_PHYS + 0x00025000, 33 PMIF_SPMI_BASE = IO_PHYS + 0x00027000, 34 INFRA2_AO_DBUG_BASE = IO_PHYS + 0x00028000, 35 SPMI_MST_BASE = IO_PHYS + 0x00029000, 36 PERI_AO_BASE = IO_PHYS + 0x0002B000, 37 PERI_AO2_BASE = IO_PHYS + 0x0002E000, 38 DEVAPC_INFRA_AO_BASE = IO_PHYS + 0x00030000, 39 DEVAPC_PERI_AO_BASE = IO_PHYS + 0x00034000, 40 DEVAPC_PERI2_AO_BASE = IO_PHYS + 0x00038000, 41 DEVAPC_PERI_PAR_AO_BASE = IO_PHYS + 0x0003C000, 42 PERI_PAR_AO_BASE = IO_PHYS + 0x00040000, 43 FMEM_AO_BASE = IO_PHYS + 0x00042000, 44 DEVAPC_FMEM_AO_BASE = IO_PHYS + 0x00044000, 45 DBG_TRACKER_BASE = IO_PHYS + 0x00208000, 46 PERI_TRACKER_BASE = IO_PHYS + 0x00218000, 47 EMI0_BASE = IO_PHYS + 0x00219000, 48 EMI1_BASE = IO_PHYS + 0x0021D000, 49 I2C0_DMA_BASE = IO_PHYS + 0x00220080, 50 I2C1_DMA_BASE = IO_PHYS + 0x00220100, 51 I2C2_DMA_BASE = IO_PHYS + 0x00220180, 52 I2C3_DMA_BASE = IO_PHYS + 0x00220280, 53 I2C4_DMA_BASE = IO_PHYS + 0x00220380, 54 I2C5_DMA_BASE = IO_PHYS + 0x00220480, 55 I2C6_DMA_BASE = IO_PHYS + 0x00220600, 56 DEVAPC_INFRA2_AO_BASE = IO_PHYS + 0x00228000, 57 DRAMC_CHA_AO_BASE = IO_PHYS + 0x00230000, 58 SUB_INFRACFG_AO_BASE = IO_PHYS + 0x0030E000, 59 INFRA_TRACKER_BASE = IO_PHYS + 0x00314000, 60 SSPM_SRAM_BASE = IO_PHYS + 0x00400000, 61 SSPM_CFG_BASE = IO_PHYS + 0x00440000, 62 SCP_CFG_BASE = IO_PHYS + 0x00700000, 63 SCP_ADSP_CFG_BASE = IO_PHYS + 0x00720000, 64 DPM_PM_SRAM_BASE = IO_PHYS + 0x00900000, 65 DPM_DM_SRAM_BASE = IO_PHYS + 0x00920000, 66 DPM_CFG_BASE = IO_PHYS + 0x00940000, 67 DPM_PM_SRAM_BASE2 = IO_PHYS + 0x00A00000, 68 DPM_DM_SRAM_BASE2 = IO_PHYS + 0x00A20000, 69 DPM_CFG_BASE2 = IO_PHYS + 0x00A40000, 70 AUDIO_BASE = IO_PHYS + 0x00B10000, 71 UART0_BASE = IO_PHYS + 0x01001100, 72 UART1_BASE = IO_PHYS + 0x01001200, 73 UART2_BASE = IO_PHYS + 0x01001300, 74 UART3_BASE = IO_PHYS + 0x01001400, 75 AUXADC_BASE = IO_PHYS + 0x01002000, 76 PERICFG_AO_BASE = IO_PHYS + 0x01003000, 77 SPI0_BASE = IO_PHYS + 0x0100A000, 78 SPI1_BASE = IO_PHYS + 0x01010000, 79 SPI2_BASE = IO_PHYS + 0x01012000, 80 SPI3_BASE = IO_PHYS + 0x01013000, 81 SPI4_BASE = IO_PHYS + 0x01018000, 82 SPI5_BASE = IO_PHYS + 0x01019000, 83 SSUSB_IPPC_BASE = IO_PHYS + 0x01203E00, 84 MSDC0_BASE = IO_PHYS + 0x01230000, 85 MSDC1_BASE = IO_PHYS + 0x01240000, 86 I2C0_BASE = IO_PHYS + 0x01280000, 87 I2C2_BASE = IO_PHYS + 0x01281000, 88 I2C3_BASE = IO_PHYS + 0x01282000, 89 SFLASH_REG_BASE = IO_PHYS + 0x0132C000, 90 IOCFG_RM_BASE = IO_PHYS + 0x01C00000, 91 MIPITX_BASE = IO_PHYS + 0x01C80000, 92 I2C1_BASE = IO_PHYS + 0x01E00000, 93 I2C4_BASE = IO_PHYS + 0x01E01000, 94 IOCFG_LT_BASE = IO_PHYS + 0x01E10000, 95 IOCFG_LM_BASE = IO_PHYS + 0x01E20000, 96 SSUSB_SIF_BASE = IO_PHYS + 0x01E40300, 97 IOCFG_RT_BASE = IO_PHYS + 0x01EA0000, 98 MSDC1_TOP_BASE = IO_PHYS + 0x01EB0000, 99 I2C5_BASE = IO_PHYS + 0x01EC0000, 100 I2C6_BASE = IO_PHYS + 0x01EC1000, 101 EFUSE_BASE = IO_PHYS + 0x01F20000, 102 MSDC0_TOP_BASE = IO_PHYS + 0x01F50000, 103 DISP_OVL0_BASE = IO_PHYS + 0x0C000000, 104 DISP_RDMA0_BASE = IO_PHYS + 0x0C002000, 105 DISP_COLOR0_BASE = IO_PHYS + 0x0C003000, 106 DISP_CCORR0_BASE = IO_PHYS + 0x0C004000, 107 DISP_AAL0_BASE = IO_PHYS + 0x0C005000, 108 DISP_GAMMA0_BASE = IO_PHYS + 0x0C006000, 109 DISP_DITHER0_BASE = IO_PHYS + 0x0C007000, 110 DSI0_BASE = IO_PHYS + 0x0C008000, 111 DISP_OVL1_BASE = IO_PHYS + 0x0C00A000, 112 DP_INTF0_BASE = IO_PHYS + 0x0C015000, 113 DISP_MUTEX_BASE = IO_PHYS + 0x0C016000, 114 DISP_POSTMASK0_BASE = IO_PHYS + 0x0C01A000, 115 VDOSYS0_BASE = IO_PHYS + 0x0C01D000, 116 SMI_LARB0 = IO_PHYS + 0x0C022000, 117 EDP_BASE = IO_PHYS + 0x0C500000, 118 }; 119 #endif 120