1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _BROADWELL_PM_H_ 4 #define _BROADWELL_PM_H_ 5 6 #include <acpi/acpi.h> 7 8 /* ACPI_BASE_ADDRESS / PMBASE */ 9 10 #define PM1_STS 0x00 11 #define WAK_STS (1 << 15) 12 #define PCIEXPWAK_STS (1 << 14) 13 #define PRBTNOR_STS (1 << 11) 14 #define RTC_STS (1 << 10) 15 #define PWRBTN_STS (1 << 8) 16 #define GBL_STS (1 << 5) 17 #define BM_STS (1 << 4) 18 #define TMROF_STS (1 << 0) 19 #define PM1_EN 0x02 20 #define PCIEXPWAK_DIS (1 << 14) 21 #define RTC_EN (1 << 10) 22 #define PWRBTN_EN (1 << 8) 23 #define GBL_EN (1 << 5) 24 #define TMROF_EN (1 << 0) 25 #define PM1_CNT 0x04 26 #define GBL_RLS (1 << 2) 27 #define BM_RLD (1 << 1) 28 #define SCI_EN (1 << 0) 29 #define PM1_TMR 0x08 30 #define SMI_EN 0x30 31 #define XHCI_SMI_EN (1 << 31) 32 #define ME_SMI_EN (1 << 30) 33 #define GPIO_UNLOCK_SMI_EN (1 << 27) 34 #define INTEL_USB2_EN (1 << 18) 35 #define LEGACY_USB2_EN (1 << 17) 36 #define PERIODIC_EN (1 << 14) 37 #define TCO_EN (1 << 13) 38 #define MCSMI_EN (1 << 11) 39 #define BIOS_RLS (1 << 7) 40 #define SWSMI_TMR_EN (1 << 6) 41 #define APMC_EN (1 << 5) 42 #define SLP_SMI_EN (1 << 4) 43 #define LEGACY_USB_EN (1 << 3) 44 #define BIOS_EN (1 << 2) 45 #define EOS (1 << 1) 46 #define GBL_SMI_EN (1 << 0) 47 #define SMI_STS 0x34 48 #define UPWRC 0x3c 49 #define UPWRC_WS (1 << 8) 50 #define UPWRC_WE (1 << 1) 51 #define UPWRC_SMI (1 << 0) 52 #define GPE_CNTL 0x42 53 #define SWGPE_CTRL (1 << 1) 54 #define DEVACT_STS 0x44 55 #define PM2_CNT 0x50 56 57 #if CONFIG(TCO_SPACE_NOT_YET_SPLIT) 58 #define TCO1_CNT 0x60 59 #define TCO_TMR_HLT (1 << 11) 60 #define TCO1_STS 0x64 61 #define DMISCI_STS (1 << 9) 62 #define TCO2_STS 0x66 63 #define TCO2_STS_SECOND_TO (1 << 1) 64 #endif 65 66 #define GPE0_REG_MAX 4 67 #define GPE0_REG_SIZE 32 68 #define GPE0_STS(x) (0x80 + ((x) * 4)) 69 #define GPE_31_0 0 /* 0x80/0x90 = GPE[31:0] */ 70 #define GPE_63_32 1 /* 0x84/0x94 = GPE[63:32] */ 71 #define GPE_94_64 2 /* 0x88/0x98 = GPE[94:64] */ 72 #define GPE_STD 3 /* 0x8c/0x9c = Standard GPE */ 73 #define WADT_STS (1 << 18) 74 #define GP27_STS (1 << 16) 75 #define PME_B0_STS (1 << 13) 76 #define ME_SCI_STS (1 << 12) 77 #define PME_STS (1 << 11) 78 #define BATLOW_STS (1 << 10) 79 #define PCI_EXP_STS (1 << 9) 80 #define SMB_WAK_STS (1 << 7) 81 #define TCOSCI_STS (1 << 6) 82 #define SWGPE_STS (1 << 2) 83 #define HOT_PLUG_STS (1 << 1) 84 #define GPE0_EN(x) (0x90 + ((x) * 4)) 85 #define WADT_en (1 << 18) 86 #define GP27_EN (1 << 16) 87 #define PME_B0_EN (1 << 13) 88 #define ME_SCI_EN (1 << 12) 89 #define PME_EN (1 << 11) 90 #define BATLOW_EN (1 << 10) 91 #define PCI_EXP_EN (1 << 9) 92 #define TCOSCI_EN (1 << 6) 93 #define SWGPE_EN (1 << 2) 94 #define HOT_PLUG_EN (1 << 1) 95 96 #define MAINBOARD_POWER_OFF 0 97 #define MAINBOARD_POWER_ON 1 98 #define MAINBOARD_POWER_KEEP 2 99 100 struct chipset_power_state { 101 uint16_t pm1_sts; 102 uint16_t pm1_en; 103 uint32_t pm1_cnt; 104 uint16_t tco1_sts; 105 uint16_t tco2_sts; 106 uint32_t gpe0_sts[4]; 107 uint32_t gpe0_en[4]; 108 uint16_t gen_pmcon1; 109 uint16_t gen_pmcon2; 110 uint16_t gen_pmcon3; 111 int prev_sleep_state; 112 uint16_t hsio_version; 113 uint16_t hsio_checksum; 114 }; 115 116 /* PM1_CNT */ 117 void enable_pm1_control(uint32_t mask); 118 void disable_pm1_control(uint32_t mask); 119 120 /* PM1 */ 121 uint16_t clear_pm1_status(void); 122 void enable_pm1(uint16_t events); 123 uint32_t clear_smi_status(void); 124 125 /* SMI */ 126 void enable_smi(uint32_t mask); 127 void disable_smi(uint32_t mask); 128 129 /* ALT_GP_SMI */ 130 uint32_t clear_alt_smi_status(void); 131 void enable_alt_smi(uint32_t mask); 132 133 /* TCO */ 134 uint32_t clear_tco_status(void); 135 void enable_tco_sci(void); 136 137 /* GPE0 */ 138 uint32_t clear_gpe_status(void); 139 void clear_gpe_enable(void); 140 void enable_all_gpe(uint32_t set1, uint32_t set2, uint32_t set3, uint32_t set4); 141 void disable_all_gpe(void); 142 void enable_gpe(uint32_t mask); 143 void disable_gpe(uint32_t mask); 144 145 /* STM Support */ 146 uint16_t get_pmbase(void); 147 148 #endif 149