1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_GPIO_H 4 #define __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_GPIO_H 5 6 #include <types.h> 7 8 #define GPIO(p, b, i) ((gpio_t){.port = p, .bank = GPIO_##b, .idx = i}) 9 10 struct rockchip_gpio_regs { 11 u32 swporta_dr; 12 u32 swporta_ddr; 13 u32 reserved0[(0x30 - 0x08) / 4]; 14 u32 inten; 15 u32 intmask; 16 u32 inttype_level; 17 u32 int_polarity; 18 u32 int_status; 19 u32 int_rawstatus; 20 u32 debounce; 21 u32 porta_eoi; 22 u32 ext_porta; 23 u32 reserved1[(0x60 - 0x54) / 4]; 24 u32 ls_sync; 25 }; 26 check_member(rockchip_gpio_regs, ls_sync, 0x60); 27 28 typedef union { 29 u32 raw; 30 struct { 31 union { 32 struct { 33 u32 num : 5; 34 u32 reserved1 : 27; 35 }; 36 struct { 37 u32 idx : 3; 38 u32 bank : 2; 39 u32 port : 4; 40 u32 reserved2 : 23; 41 }; 42 }; 43 }; 44 } gpio_t; 45 46 enum { 47 GPIO_A = 0, 48 GPIO_B, 49 GPIO_C, 50 GPIO_D, 51 }; 52 53 extern struct rockchip_gpio_regs *gpio_port[]; 54 55 /* Check if the gpio port is a pmu gpio */ 56 int is_pmu_gpio(gpio_t gpio); 57 58 /* Return the io addr of gpio register */ 59 void *gpio_grf_reg(gpio_t gpio); 60 61 enum gpio_pull { 62 GPIO_PULLNONE = 0, 63 GPIO_PULLUP = 1, 64 GPIO_PULLDOWN = 2, 65 }; 66 67 enum gpio_dir { 68 GPIO_INPUT = 0, 69 GPIO_OUTPUT = 1, 70 }; 71 72 enum gpio_irq_type { 73 IRQ_TYPE_EDGE_RISING = 0, 74 IRQ_TYPE_EDGE_FALLING, 75 IRQ_TYPE_LEVEL_HIGH, 76 IRQ_TYPE_LEVEL_LOW, 77 }; 78 79 /* Setup and enable irq */ 80 void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, enum gpio_pull pull); 81 82 /* Check and clear irq status */ 83 int gpio_irq_status(gpio_t gpio); 84 85 /* The gpio pull bias setting may be different between SoCs */ 86 u32 gpio_get_pull_val(gpio_t gpio, enum gpio_pull pull); 87 88 #endif 89