1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef AMD_STONEYRIDGE_SOUTHBRIDGE_H 4 #define AMD_STONEYRIDGE_SOUTHBRIDGE_H 5 6 #include <types.h> 7 #include <device/device.h> 8 #include <device/pci_def.h> 9 #include <soc/iomap.h> 10 11 /* 12 * AcpiMmio Region 13 * - fixed addresses offset from 0xfed80000 14 */ 15 16 /* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */ 17 #define PM_PCI_CTRL 0x08 18 #define FORCE_SLPSTATE_RETRY BIT(25) 19 #define FORCE_STPCLK_RETRY BIT(24) 20 21 #define PWR_RESET_CFG 0x10 22 #define TOGGLE_ALL_PWR_GOOD BIT(1) 23 24 #define PM_SERIRQ_CONF 0x54 25 #define PM_SERIRQ_NUM_BITS_17 0x0000 26 #define PM_SERIRQ_NUM_BITS_18 0x0004 27 #define PM_SERIRQ_NUM_BITS_19 0x0008 28 #define PM_SERIRQ_NUM_BITS_20 0x000c 29 #define PM_SERIRQ_NUM_BITS_21 0x0010 30 #define PM_SERIRQ_NUM_BITS_22 0x0014 31 #define PM_SERIRQ_NUM_BITS_23 0x0018 32 #define PM_SERIRQ_NUM_BITS_24 0x001c 33 #define PM_SERIRQ_MODE BIT(6) 34 #define PM_SERIRQ_ENABLE BIT(7) 35 36 #define PM_EVT_BLK 0x60 37 #define WAK_STS BIT(15) /*AcpiPmEvtBlkx00 Pm1Status */ 38 #define PCIEXPWAK_STS BIT(14) 39 #define RTC_STS BIT(10) 40 #define PWRBTN_STS BIT(8) 41 #define GBL_STS BIT(5) 42 #define BM_STS BIT(4) 43 #define TIMER_STS BIT(0) 44 #define PCIEXPWAK_DIS BIT(14) /*AcpiPmEvtBlkx02 Pm1Enable */ 45 #define RTC_EN BIT(10) 46 #define PWRBTN_EN BIT(8) 47 #define GBL_EN BIT(5) 48 #define TIMER_STS BIT(0) 49 #define PM1_CNT_BLK 0x62 50 #define PM_TMR_BLK 0x64 51 #define PM_CPU_CTRL 0x66 52 #define PM_GPE0_BLK 0x68 53 #define PM_ACPI_SMI_CMD 0x6a 54 #define PM_ACPI_CONF 0x74 55 #define PM_ACPI_DECODE_STD BIT(0) 56 #define PM_ACPI_GLOBAL_EN BIT(1) 57 #define PM_ACPI_RTC_EN_EN BIT(2) 58 #define PM_ACPI_TIMER_EN_EN BIT(4) 59 #define PM_ACPI_MASK_ARB_DIS BIT(6) 60 #define PM_ACPI_BIOS_RLS BIT(7) 61 #define PM_ACPI_PWRBTNEN_EN BIT(8) 62 #define PM_ACPI_REDUCED_HW_EN BIT(9) 63 #define PM_ACPI_BLOCK_PCIE_PME BIT(24) 64 #define PM_ACPI_PCIE_WAK_MASK BIT(25) 65 #define PM_ACPI_WAKE_AS_GEVENT BIT(27) 66 #define PM_ACPI_NB_PME_GEVENT BIT(28) 67 #define PM_ACPI_RTC_WAKE_EN BIT(29) 68 #define PM_PCIB_CFG 0xea 69 #define PM_GENINT_DISABLE BIT(0) 70 #define PM_LPC_GATING 0xec 71 #define PM_LPC_AB_NO_BYPASS_EN BIT(2) 72 #define PM_LPC_A20_EN BIT(1) 73 #define PM_LPC_ENABLE BIT(0) 74 #define PM_USB_ENABLE 0xef 75 #define PM_USB_ALL_CONTROLLERS 0x7f 76 77 /* FCH MISC Registers 0xfed80e00 */ 78 #define GPP_CLK_CNTRL 0x00 79 #define GPP_CLK2_REQ_MAP_SHIFT 8 80 #define GPP_CLK2_REQ_MAP_MASK (0xf << GPP_CLK2_REQ_MAP_SHIFT) 81 #define GPP_CLK2_REQ_MAP_CLK_REQ2 3 82 #define GPP_CLK0_REQ_MAP_SHIFT 0 83 #define GPP_CLK0_REQ_MAP_MASK (0xf << GPP_CLK0_REQ_MAP_SHIFT) 84 #define GPP_CLK0_REQ_MAP_CLK_REQ0 1 85 #define MISC_CGPLL_CONFIG1 0x08 86 #define CG1PLL_SPREAD_SPECTRUM_ENABLE BIT(0) 87 #define MISC_CGPLL_CONFIG3 0x10 88 #define CG1PLL_REFDIV_SHIFT 0 89 #define CG1PLL_REFDIV_MASK (0x3ff << CG1PLL_REFDIV_SHIFT) 90 #define CG1PLL_FBDIV_SHIFT 10 91 #define CG1PLL_FBDIV_MASK (0xfff << CG1PLL_FBDIV_SHIFT) 92 #define MISC_CGPLL_CONFIG4 0x14 93 #define SS_STEP_SIZE_DSFRAC_SHIFT 0 94 #define SS_STEP_SIZE_DSFRAC_MASK (0xffff << SS_STEP_SIZE_DSFRAC_SHIFT) 95 #define SS_AMOUNT_DSFRAC_SHIFT 16 96 #define SS_AMOUNT_DSFRAC_MASK (0xffff << SS_AMOUNT_DSFRAC_SHIFT) 97 #define MISC_CGPLL_CONFIG5 0x18 98 #define SS_AMOUNT_NFRAC_SLIP_SHIFT 8 99 #define SS_AMOUNT_NFRAC_SLIP_MASK (0xf << SS_AMOUNT_NFRAC_SLIP_SHIFT) 100 #define MISC_CGPLL_CONFIG6 0x1c 101 #define CG1PLL_LF_MODE_SHIFT 9 102 #define CG1PLL_LF_MODE_MASK (0x1ff << CG1PLL_LF_MODE_SHIFT) 103 #define MISC_CLK_CNTL1 0x40 104 #define CG1PLL_FBDIV_TEST BIT(26) 105 #define OSCOUT1_CLK_OUTPUT_ENB BIT(2) /* 0 = Enabled, 1 = Disabled */ 106 #define OSCOUT2_CLK_OUTPUT_ENB BIT(7) /* 0 = Enabled, 1 = Disabled */ 107 108 /* XHCI_PM Registers: 0xfed81c00 */ 109 #define XHCI_PM_INDIRECT_INDEX 0x48 110 #define XHCI_PM_INDIRECT_DATA 0x4c 111 #define XHCI_OVER_CURRENT_CONTROL 0x30 112 #define USB_OC0 0 113 #define USB_OC1 1 114 #define USB_OC2 2 115 #define USB_OC3 3 116 #define USB_OC4 4 117 #define USB_OC5 5 118 #define USB_OC6 6 119 #define USB_OC7 7 120 #define USB_OC_DISABLE 0xf 121 #define USB_OC_DISABLE_ALL 0xffff 122 #define OC_PORT0_SHIFT 0 123 #define OC_PORT1_SHIFT 4 124 #define OC_PORT2_SHIFT 8 125 #define OC_PORT3_SHIFT 12 126 127 #define EHCI_OVER_CURRENT_CONTROL 0x70 128 #define EHCI_HUB_CONFIG4 0x90 129 #define DEBUG_PORT_SELECT_SHIFT 16 130 #define DEBUG_PORT_ENABLE BIT(18) 131 #define DEBUG_PORT_MASK (BIT(16) | BIT(17) | BIT(18)) 132 133 #define PM1_LIMIT 16 134 #define GPE0_LIMIT 28 135 #define TOTAL_BITS(a) (8 * sizeof(a)) 136 137 /* SATA Controller D11F0 */ 138 #define SATA_MISC_CONTROL_REG 0x40 139 #define SATA_MISC_SUBCLASS_WREN BIT(0) 140 /* Register in AHCIBaseAddress (BAR5 at D11F0x24) */ 141 #define SATA_CAPABILITIES_REG 0xfc 142 #define SATA_CAPABILITY_SPM BIT(12) 143 144 /* Platform Security Processor D8F0 */ 145 void soc_enable_psp_early(void); 146 147 #define PSP_MAILBOX_BAR PCI_BASE_ADDRESS_4 /* BKDG: "BAR3" */ 148 149 #define PSP_BAR_ENABLES 0x48 150 #define BAR3HIDE BIT(12) /* Bit to hide BAR3 addr */ 151 #define PSP_MAILBOX_BAR_EN BIT(4) 152 153 typedef struct aoac_devs { 154 unsigned int :5; 155 unsigned int ic0e:1; /* 5: I2C0 */ 156 unsigned int ic1e:1; /* 6: I2C1 */ 157 unsigned int ic2e:1; /* 7: I2C2 */ 158 unsigned int ic3e:1; /* 8: I2C3 */ 159 unsigned int :2; 160 unsigned int ut0e:1; /* 11: UART0 */ 161 unsigned int ut1e:1; /* 12: UART1 */ 162 unsigned int :2; 163 unsigned int st_e:1; /* 15: SATA */ 164 unsigned int :2; 165 unsigned int ehce:1; /* 18: EHCI */ 166 unsigned int :4; 167 unsigned int xhce:1; /* 23: xHCI */ 168 unsigned int sd_e:1; /* 24: SDIO */ 169 unsigned int :2; 170 unsigned int espi:1; /* 27: ESPI */ 171 unsigned int :4; 172 } __packed aoac_devs_t; 173 174 #define XHCI_FW_SIG_OFFSET 0xc 175 #define XHCI_FW_ADDR_OFFSET 0x6 176 #define XHCI_FW_SIZE_OFFSET 0x8 177 #define XHCI_FW_BOOTRAM_SIZE 0x8000 178 179 void bootblock_fch_early_init(void); 180 void bootblock_fch_init(void); 181 void fch_init(void *chip_info); 182 void fch_final(void *chip_info); 183 184 void fch_clk_output_48Mhz(u32 osc); 185 186 /* 187 * Call the mainboard to get the USB Over Current Map. The mainboard 188 * returns the map and 0 on Success or -1 on error or no map. There is 189 * a default weak function in usb.c if the mainboard doesn't have any 190 * over current support. 191 */ 192 int mainboard_get_xhci_oc_map(uint16_t *usb_oc_map); 193 int mainboard_get_ehci_oc_map(uint16_t *usb_oc_map); 194 195 #endif /* AMD_STONEYRIDGE_SOUTHBRIDGE_H */ 196