| /external/swiftshader/third_party/subzero/unittest/AssemblerX8632/ |
| D | XmmArith.cpp | 1412 #define TestImplSXmmReg(Dst, GPR, Inst, Size) \ in TEST_F() argument
1432 #define TestImplSRegXmm(GPR, Src, Inst, Size) \ in TEST_F() argument
1493 #define TestImplSRegAddr(GPR, Inst, Size) \ in TEST_F() argument
1513 #define TestImplSize(Dst, Src, GPR, Size) \ in TEST_F() argument
1527 #define TestImpl(Dst, Src, GPR) \ in TEST_F() argument
1847 #define TestPinsrXmmGPRImm(Dst, Value0, GPR, Value1, Imm, Size) \ in TEST_F() argument
1895 #define TestPinsrSize(Dst, GPR, Value1, Imm, Size) \ in TEST_F() argument
1934 #define TestPextrGPRXmmImm(GPR, Src, Value1, Imm, Size) \ in TEST_F() argument
1954 #define TestPextrSize(GPR, Src, Value1, Imm, Size) \ in TEST_F() argument
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| D | DataMov.cpp | 970 #define TestMovmskGPRXmm(GPR, Src, Value1, Expected, Inst) \ in TEST_F() argument
989 #define TestMovmsk(GPR, Src) \ in TEST_F() argument
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| /external/swiftshader/third_party/subzero/unittest/AssemblerX8664/ |
| D | XmmArith.cpp | 1485 #define TestImplSXmmReg(Dst, GPR, Inst, Size, IntType) \ in TEST_F() argument
1504 #define TestImplSRegXmm(GPR, Src, Inst, IntSize, Size) \ in TEST_F() argument
1564 #define TestImplSRegAddr(GPR, Inst, IntSize, Size) \ in TEST_F() argument
1584 #define TestImplSize(Dst, Src, GPR, Size) \ in TEST_F() argument
1602 #define TestImpl(Dst, Src, GPR) \ in TEST_F() argument
1950 #define TestPinsrXmmGPRImm(Dst, Value0, GPR, Value1, Imm, Size) \ in TEST_F() argument
1998 #define TestPinsrSize(Dst, GPR, Value1, Imm, Size) \ in TEST_F() argument
2045 #define TestPextrGPRXmmImm(GPR, Src, Value1, Imm, Size) \ in TEST_F() argument
2065 #define TestPextrSize(GPR, Src, Value1, Imm, Size) \ in TEST_F() argument
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| D | DataMov.cpp | 1358 #define TestMovmskGPRXmm(GPR, Src, Value1, Expected, Inst) \ in TEST_F() argument
1376 #define TestMovmsk(GPR, Src) \ in TEST_F() argument
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZMachineFunctionInfo.h | 48 void setVarArgsFirstGPR(unsigned GPR) { VarArgsFirstGPR = GPR; } in setVarArgsFirstGPR()
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/SystemZ/ |
| D | SystemZMachineFunctionInfo.h | 72 void setVarArgsFirstGPR(Register GPR) { VarArgsFirstGPR = GPR; } in setVarArgsFirstGPR()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZMachineFunctionInfo.h | 69 void setVarArgsFirstGPR(unsigned GPR) { VarArgsFirstGPR = GPR; } in setVarArgsFirstGPR()
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/ |
| D | MVETPAndVPTOptimisationsPass.cpp | 943 Register GPR = Copy->getOperand(1).getReg(); in ReplaceConstByVPNOTs() local
946 auto getImm = [&](Register GPR) -> unsigned { in ReplaceConstByVPNOTs()
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/ |
| D | HexagonGenPredicate.cpp | 426 RegisterSubReg GPR = MI->getOperand(i); in convertToPredForm() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonGenPredicate.cpp | 427 RegisterSubReg GPR = MI->getOperand(i); in convertToPredForm() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonGenPredicate.cpp | 407 Register GPR = MI->getOperand(i); in convertToPredForm() local
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| /external/kernel-headers/original/uapi/sound/ |
| D | emu10k1.h | 157 #define GPR(x) (FXGPREGBASE + (x)) /* free GPRs: x = 0x00 - 0xff */ macro
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 3148 static const MCPhysReg GPR[] = { in LowerFormalArguments_64SVR4() local
3584 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32; in LowerFormalArguments_Darwin() local
3973 static const MCPhysReg GPR[] = { in needStackSlotPassParameters() local
5029 static const MCPhysReg GPR[] = { in LowerCall_64SVR4() local
5748 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32; in LowerCall_Darwin() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 1910 enum RegType { GPR, FPR64, FPR128, PPR, ZPR } Type; enumerator
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 3763 static const MCPhysReg GPR[] = { in LowerFormalArguments_64SVR4() local
4193 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32; in LowerFormalArguments_Darwin() local
4601 static const MCPhysReg GPR[] = { in needStackSlotPassParameters() local
5861 static const MCPhysReg GPR[] = { in LowerCall_64SVR4() local
6605 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32; in LowerCall_Darwin() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 2501 enum RegType { GPR, FPR64, FPR128, PPR, ZPR } Type; enumerator
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| /external/mesa3d/src/nouveau/compiler/nak/ |
| D | ir.rs | 58 GPR = 0, enumerator
1408 GPR, enumerator
1467 GPR, enumerator
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 4304 static const MCPhysReg GPR[] = { in LowerFormalArguments_64SVR4() local
4764 static const MCPhysReg GPR[] = { in needStackSlotPassParameters() local
6014 static const MCPhysReg GPR[] = { in LowerCall_64SVR4() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 6751 const MCRegisterClass &GPR = MRI->getRegClass(ARM::GPRRegClassID); in fixupGNULDRDAlias() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 6991 const MCRegisterClass &GPR = MRI->getRegClass(ARM::GPRRegClassID); in fixupGNULDRDAlias() local
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 2737 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass); in LowerFormalArguments() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 3551 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass); in LowerFormalArguments() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 3978 Register GPR = TheMachineFunction.addLiveIn(Reg, &X86::GR64RegClass); in createVarArgAreaAndStoreRegisters() local
|