1 /* Copyright 2022 Advanced Micro Devices, Inc. 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: AMD 22 * 23 */ 24 #pragma once 25 26 #include "dpp.h" 27 #include "transform.h" 28 #include "reg_helper.h" 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 // Used to resolve corner case 35 #define DPP_SFRB(field_name, reg_name, post_fix) .field_name = reg_name##_##field_name##post_fix 36 37 #define DPP_REG_LIST_VPE10_COMMON(id) \ 38 SRIDFVL(VPCNVC_SURFACE_PIXEL_FORMAT, VPCNVC_CFG, id), \ 39 SRIDFVL(VPCNVC_FORMAT_CONTROL, VPCNVC_CFG, id), \ 40 SRIDFVL(VPCNVC_FCNV_FP_BIAS_R, VPCNVC_CFG, id), \ 41 SRIDFVL(VPCNVC_FCNV_FP_BIAS_G, VPCNVC_CFG, id), \ 42 SRIDFVL(VPCNVC_FCNV_FP_BIAS_B, VPCNVC_CFG, id), \ 43 SRIDFVL(VPCNVC_FCNV_FP_SCALE_R, VPCNVC_CFG, id), \ 44 SRIDFVL(VPCNVC_FCNV_FP_SCALE_G, VPCNVC_CFG, id), \ 45 SRIDFVL(VPCNVC_FCNV_FP_SCALE_B, VPCNVC_CFG, id), \ 46 SRIDFVL(VPCNVC_COLOR_KEYER_CONTROL, VPCNVC_CFG, id), \ 47 SRIDFVL(VPCNVC_COLOR_KEYER_ALPHA, VPCNVC_CFG, id), \ 48 SRIDFVL(VPCNVC_COLOR_KEYER_RED, VPCNVC_CFG, id), \ 49 SRIDFVL(VPCNVC_COLOR_KEYER_GREEN, VPCNVC_CFG, id), \ 50 SRIDFVL(VPCNVC_COLOR_KEYER_BLUE, VPCNVC_CFG, id), \ 51 SRIDFVL(VPCNVC_PRE_DEALPHA, VPCNVC_CFG, id), SRIDFVL(VPCNVC_PRE_CSC_MODE, VPCNVC_CFG, id), \ 52 SRIDFVL(VPCNVC_PRE_CSC_C11_C12, VPCNVC_CFG, id), \ 53 SRIDFVL(VPCNVC_PRE_CSC_C13_C14, VPCNVC_CFG, id), \ 54 SRIDFVL(VPCNVC_PRE_CSC_C21_C22, VPCNVC_CFG, id), \ 55 SRIDFVL(VPCNVC_PRE_CSC_C23_C24, VPCNVC_CFG, id), \ 56 SRIDFVL(VPCNVC_PRE_CSC_C31_C32, VPCNVC_CFG, id), \ 57 SRIDFVL(VPCNVC_PRE_CSC_C33_C34, VPCNVC_CFG, id), \ 58 SRIDFVL(VPCNVC_COEF_FORMAT, VPCNVC_CFG, id), SRIDFVL(VPCNVC_PRE_DEGAM, VPCNVC_CFG, id), \ 59 SRIDFVL(VPCNVC_PRE_REALPHA, VPCNVC_CFG, id), \ 60 SRIDFVL(VPDSCL_COEF_RAM_TAP_SELECT, VPDSCL, id), \ 61 SRIDFVL(VPDSCL_COEF_RAM_TAP_DATA, VPDSCL, id), SRIDFVL(VPDSCL_MODE, VPDSCL, id), \ 62 SRIDFVL(VPDSCL_TAP_CONTROL, VPDSCL, id), SRIDFVL(VPDSCL_CONTROL, VPDSCL, id), \ 63 SRIDFVL(VPDSCL_2TAP_CONTROL, VPDSCL, id), \ 64 SRIDFVL(VPDSCL_MANUAL_REPLICATE_CONTROL, VPDSCL, id), \ 65 SRIDFVL(VPDSCL_HORZ_FILTER_SCALE_RATIO, VPDSCL, id), \ 66 SRIDFVL(VPDSCL_HORZ_FILTER_INIT, VPDSCL, id), \ 67 SRIDFVL(VPDSCL_HORZ_FILTER_SCALE_RATIO_C, VPDSCL, id), \ 68 SRIDFVL(VPDSCL_HORZ_FILTER_INIT_C, VPDSCL, id), \ 69 SRIDFVL(VPDSCL_VERT_FILTER_SCALE_RATIO, VPDSCL, id), \ 70 SRIDFVL(VPDSCL_VERT_FILTER_INIT, VPDSCL, id), \ 71 SRIDFVL(VPDSCL_VERT_FILTER_SCALE_RATIO_C, VPDSCL, id), \ 72 SRIDFVL(VPDSCL_VERT_FILTER_INIT_C, VPDSCL, id), SRIDFVL(VPDSCL_BLACK_COLOR, VPDSCL, id), \ 73 SRIDFVL(VPDSCL_UPDATE, VPDSCL, id), SRIDFVL(VPDSCL_AUTOCAL, VPDSCL, id), \ 74 SRIDFVL(VPDSCL_EXT_OVERSCAN_LEFT_RIGHT, VPDSCL, id), \ 75 SRIDFVL(VPDSCL_EXT_OVERSCAN_TOP_BOTTOM, VPDSCL, id), SRIDFVL(VPOTG_H_BLANK, VPDSCL, id), \ 76 SRIDFVL(VPOTG_V_BLANK, VPDSCL, id), SRIDFVL(VPDSCL_RECOUT_START, VPDSCL, id), \ 77 SRIDFVL(VPDSCL_RECOUT_SIZE, VPDSCL, id), SRIDFVL(VPMPC_SIZE, VPDSCL, id), \ 78 SRIDFVL(VPLB_DATA_FORMAT, VPDSCL, id), SRIDFVL(VPLB_MEMORY_CTRL, VPDSCL, id), \ 79 SRIDFVL(VPLB_V_COUNTER, VPDSCL, id), SRIDFVL(VPDSCL_MEM_PWR_CTRL, VPDSCL, id), \ 80 SRIDFVL(VPDSCL_MEM_PWR_STATUS, VPDSCL, id), SRIDFVL(VPCM_CONTROL, VPCM, id), \ 81 SRIDFVL(VPCM_POST_CSC_CONTROL, VPCM, id), SRIDFVL(VPCM_POST_CSC_C11_C12, VPCM, id), \ 82 SRIDFVL(VPCM_POST_CSC_C13_C14, VPCM, id), SRIDFVL(VPCM_POST_CSC_C21_C22, VPCM, id), \ 83 SRIDFVL(VPCM_POST_CSC_C23_C24, VPCM, id), SRIDFVL(VPCM_POST_CSC_C31_C32, VPCM, id), \ 84 SRIDFVL(VPCM_POST_CSC_C33_C34, VPCM, id), \ 85 SRIDFVL(VPCM_BIAS_CR_R, VPCM, id), SRIDFVL(VPCM_BIAS_Y_G_CB_B, VPCM, id), \ 86 SRIDFVL(VPCM_GAMCOR_CONTROL, VPCM, id), SRIDFVL(VPCM_GAMCOR_LUT_INDEX, VPCM, id), \ 87 SRIDFVL(VPCM_GAMCOR_LUT_DATA, VPCM, id), SRIDFVL(VPCM_GAMCOR_LUT_CONTROL, VPCM, id), \ 88 SRIDFVL(VPCM_GAMCOR_RAMA_START_CNTL_B, VPCM, id), \ 89 SRIDFVL(VPCM_GAMCOR_RAMA_START_CNTL_G, VPCM, id), \ 90 SRIDFVL(VPCM_GAMCOR_RAMA_START_CNTL_R, VPCM, id), \ 91 SRIDFVL(VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B, VPCM, id), \ 92 SRIDFVL(VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G, VPCM, id), \ 93 SRIDFVL(VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R, VPCM, id), \ 94 SRIDFVL(VPCM_GAMCOR_RAMA_START_BASE_CNTL_B, VPCM, id), \ 95 SRIDFVL(VPCM_GAMCOR_RAMA_START_BASE_CNTL_G, VPCM, id), \ 96 SRIDFVL(VPCM_GAMCOR_RAMA_START_BASE_CNTL_R, VPCM, id), \ 97 SRIDFVL(VPCM_GAMCOR_RAMA_END_CNTL1_B, VPCM, id), \ 98 SRIDFVL(VPCM_GAMCOR_RAMA_END_CNTL2_B, VPCM, id), \ 99 SRIDFVL(VPCM_GAMCOR_RAMA_END_CNTL1_G, VPCM, id), \ 100 SRIDFVL(VPCM_GAMCOR_RAMA_END_CNTL2_G, VPCM, id), \ 101 SRIDFVL(VPCM_GAMCOR_RAMA_END_CNTL1_R, VPCM, id), \ 102 SRIDFVL(VPCM_GAMCOR_RAMA_END_CNTL2_R, VPCM, id), \ 103 SRIDFVL(VPCM_GAMCOR_RAMA_OFFSET_B, VPCM, id), \ 104 SRIDFVL(VPCM_GAMCOR_RAMA_OFFSET_G, VPCM, id), \ 105 SRIDFVL(VPCM_GAMCOR_RAMA_OFFSET_R, VPCM, id), \ 106 SRIDFVL(VPCM_GAMCOR_RAMA_REGION_0_1, VPCM, id), \ 107 SRIDFVL(VPCM_GAMCOR_RAMA_REGION_2_3, VPCM, id), \ 108 SRIDFVL(VPCM_GAMCOR_RAMA_REGION_4_5, VPCM, id), \ 109 SRIDFVL(VPCM_GAMCOR_RAMA_REGION_6_7, VPCM, id), \ 110 SRIDFVL(VPCM_GAMCOR_RAMA_REGION_8_9, VPCM, id), \ 111 SRIDFVL(VPCM_GAMCOR_RAMA_REGION_10_11, VPCM, id), \ 112 SRIDFVL(VPCM_GAMCOR_RAMA_REGION_12_13, VPCM, id), \ 113 SRIDFVL(VPCM_GAMCOR_RAMA_REGION_14_15, VPCM, id), \ 114 SRIDFVL(VPCM_GAMCOR_RAMA_REGION_16_17, VPCM, id), \ 115 SRIDFVL(VPCM_GAMCOR_RAMA_REGION_18_19, VPCM, id), \ 116 SRIDFVL(VPCM_GAMCOR_RAMA_REGION_20_21, VPCM, id), \ 117 SRIDFVL(VPCM_GAMCOR_RAMA_REGION_22_23, VPCM, id), \ 118 SRIDFVL(VPCM_GAMCOR_RAMA_REGION_24_25, VPCM, id), \ 119 SRIDFVL(VPCM_GAMCOR_RAMA_REGION_26_27, VPCM, id), \ 120 SRIDFVL(VPCM_GAMCOR_RAMA_REGION_28_29, VPCM, id), \ 121 SRIDFVL(VPCM_GAMCOR_RAMA_REGION_30_31, VPCM, id), \ 122 SRIDFVL(VPCM_GAMCOR_RAMA_REGION_32_33, VPCM, id), SRIDFVL(VPCM_HDR_MULT_COEF, VPCM, id), \ 123 SRIDFVL(VPCM_MEM_PWR_CTRL, VPCM, id), SRIDFVL(VPCM_MEM_PWR_STATUS, VPCM, id), \ 124 SRIDFVL(VPCM_DEALPHA, VPCM, id), SRIDFVL(VPCM_COEF_FORMAT, VPCM, id), \ 125 SRIDFVL(VPDPP_CONTROL, VPDPP_TOP, id), SRIDFVL(VPDPP_CRC_CTRL, VPDPP_TOP, id) 126 127 #define DPP_REG_LIST_VPE10(id) \ 128 DPP_REG_LIST_VPE10_COMMON(id), \ 129 SRIDFVL(VPCNVC_ALPHA_2BIT_LUT, VPCNVC_CFG, id), \ 130 SRIDFVL(VPCM_GAMUT_REMAP_CONTROL, VPCM, id), \ 131 SRIDFVL(VPCM_GAMUT_REMAP_C11_C12, VPCM, id), SRIDFVL(VPCM_GAMUT_REMAP_C13_C14, VPCM, id), \ 132 SRIDFVL(VPCM_GAMUT_REMAP_C21_C22, VPCM, id), SRIDFVL(VPCM_GAMUT_REMAP_C23_C24, VPCM, id), \ 133 SRIDFVL(VPCM_GAMUT_REMAP_C31_C32, VPCM, id), SRIDFVL(VPCM_GAMUT_REMAP_C33_C34, VPCM, id) 134 135 #define DPP_FIELD_LIST_VPE10_COMMON(post_fix) \ 136 SFRB(VPCNVC_SURFACE_PIXEL_FORMAT, VPCNVC_SURFACE_PIXEL_FORMAT, post_fix), \ 137 SFRB(FORMAT_EXPANSION_MODE, VPCNVC_FORMAT_CONTROL, post_fix), \ 138 SFRB(FORMAT_CNV16, VPCNVC_FORMAT_CONTROL, post_fix), \ 139 DPP_SFRB(FORMAT_CONTROL__ALPHA_EN, VPCNVC, post_fix), \ 140 SFRB(VPCNVC_BYPASS, VPCNVC_FORMAT_CONTROL, post_fix), \ 141 SFRB(VPCNVC_BYPASS_MSB_ALIGN, VPCNVC_FORMAT_CONTROL, post_fix), \ 142 SFRB(CLAMP_POSITIVE, VPCNVC_FORMAT_CONTROL, post_fix), \ 143 SFRB(CLAMP_POSITIVE_C, VPCNVC_FORMAT_CONTROL, post_fix), \ 144 SFRB(VPCNVC_UPDATE_PENDING, VPCNVC_FORMAT_CONTROL, post_fix), \ 145 SFRB(FCNV_FP_BIAS_R, VPCNVC_FCNV_FP_BIAS_R, post_fix), \ 146 SFRB(FCNV_FP_BIAS_G, VPCNVC_FCNV_FP_BIAS_G, post_fix), \ 147 SFRB(FCNV_FP_BIAS_B, VPCNVC_FCNV_FP_BIAS_B, post_fix), \ 148 SFRB(FCNV_FP_SCALE_R, VPCNVC_FCNV_FP_SCALE_R, post_fix), \ 149 SFRB(FCNV_FP_SCALE_G, VPCNVC_FCNV_FP_SCALE_G, post_fix), \ 150 SFRB(FCNV_FP_SCALE_B, VPCNVC_FCNV_FP_SCALE_B, post_fix), \ 151 SFRB(COLOR_KEYER_EN, VPCNVC_COLOR_KEYER_CONTROL, post_fix), \ 152 SFRB(COLOR_KEYER_MODE, VPCNVC_COLOR_KEYER_CONTROL, post_fix), \ 153 SFRB(COLOR_KEYER_ALPHA_LOW, VPCNVC_COLOR_KEYER_ALPHA, post_fix), \ 154 SFRB(COLOR_KEYER_ALPHA_HIGH, VPCNVC_COLOR_KEYER_ALPHA, post_fix), \ 155 SFRB(COLOR_KEYER_RED_LOW, VPCNVC_COLOR_KEYER_RED, post_fix), \ 156 SFRB(COLOR_KEYER_RED_HIGH, VPCNVC_COLOR_KEYER_RED, post_fix), \ 157 SFRB(COLOR_KEYER_GREEN_LOW, VPCNVC_COLOR_KEYER_GREEN, post_fix), \ 158 SFRB(COLOR_KEYER_GREEN_HIGH, VPCNVC_COLOR_KEYER_GREEN, post_fix), \ 159 SFRB(COLOR_KEYER_BLUE_LOW, VPCNVC_COLOR_KEYER_BLUE, post_fix), \ 160 SFRB(COLOR_KEYER_BLUE_HIGH, VPCNVC_COLOR_KEYER_BLUE, post_fix), \ 161 SFRB(PRE_DEALPHA_EN, VPCNVC_PRE_DEALPHA, post_fix), \ 162 SFRB(PRE_DEALPHA_ABLND_EN, VPCNVC_PRE_DEALPHA, post_fix), \ 163 SFRB(PRE_CSC_MODE, VPCNVC_PRE_CSC_MODE, post_fix), \ 164 SFRB(PRE_CSC_MODE_CURRENT, VPCNVC_PRE_CSC_MODE, post_fix), \ 165 SFRB(PRE_CSC_C11, VPCNVC_PRE_CSC_C11_C12, post_fix), \ 166 SFRB(PRE_CSC_C12, VPCNVC_PRE_CSC_C11_C12, post_fix), \ 167 SFRB(PRE_CSC_C13, VPCNVC_PRE_CSC_C13_C14, post_fix), \ 168 SFRB(PRE_CSC_C14, VPCNVC_PRE_CSC_C13_C14, post_fix), \ 169 SFRB(PRE_CSC_C21, VPCNVC_PRE_CSC_C21_C22, post_fix), \ 170 SFRB(PRE_CSC_C22, VPCNVC_PRE_CSC_C21_C22, post_fix), \ 171 SFRB(PRE_CSC_C23, VPCNVC_PRE_CSC_C23_C24, post_fix), \ 172 SFRB(PRE_CSC_C24, VPCNVC_PRE_CSC_C23_C24, post_fix), \ 173 SFRB(PRE_CSC_C31, VPCNVC_PRE_CSC_C31_C32, post_fix), \ 174 SFRB(PRE_CSC_C32, VPCNVC_PRE_CSC_C31_C32, post_fix), \ 175 SFRB(PRE_CSC_C33, VPCNVC_PRE_CSC_C33_C34, post_fix), \ 176 SFRB(PRE_CSC_C34, VPCNVC_PRE_CSC_C33_C34, post_fix), \ 177 SFRB(PRE_CSC_COEF_FORMAT, VPCNVC_COEF_FORMAT, post_fix), \ 178 SFRB(PRE_DEGAM_MODE, VPCNVC_PRE_DEGAM, post_fix), \ 179 SFRB(PRE_DEGAM_SELECT, VPCNVC_PRE_DEGAM, post_fix), \ 180 SFRB(PRE_REALPHA_EN, VPCNVC_PRE_REALPHA, post_fix), \ 181 SFRB(PRE_REALPHA_ABLND_EN, VPCNVC_PRE_REALPHA, post_fix), \ 182 SFRB(SCL_COEF_RAM_TAP_PAIR_IDX, VPDSCL_COEF_RAM_TAP_SELECT, post_fix), \ 183 SFRB(SCL_COEF_RAM_PHASE, VPDSCL_COEF_RAM_TAP_SELECT, post_fix), \ 184 SFRB(SCL_COEF_RAM_FILTER_TYPE, VPDSCL_COEF_RAM_TAP_SELECT, post_fix), \ 185 SFRB(SCL_COEF_RAM_EVEN_TAP_COEF, VPDSCL_COEF_RAM_TAP_DATA, post_fix), \ 186 SFRB(SCL_COEF_RAM_EVEN_TAP_COEF_EN, VPDSCL_COEF_RAM_TAP_DATA, post_fix), \ 187 SFRB(SCL_COEF_RAM_ODD_TAP_COEF, VPDSCL_COEF_RAM_TAP_DATA, post_fix), \ 188 SFRB(SCL_COEF_RAM_ODD_TAP_COEF_EN, VPDSCL_COEF_RAM_TAP_DATA, post_fix), \ 189 SFRB(VPDSCL_MODE, VPDSCL_MODE, post_fix), \ 190 SFRB(SCL_COEF_RAM_SELECT_CURRENT, VPDSCL_MODE, post_fix), \ 191 SFRB(SCL_CHROMA_COEF_MODE, VPDSCL_MODE, post_fix), \ 192 SFRB(SCL_ALPHA_COEF_MODE, VPDSCL_MODE, post_fix), \ 193 SFRB(SCL_COEF_RAM_SELECT_RD, VPDSCL_MODE, post_fix), \ 194 SFRB(SCL_V_NUM_TAPS, VPDSCL_TAP_CONTROL, post_fix), \ 195 SFRB(SCL_H_NUM_TAPS, VPDSCL_TAP_CONTROL, post_fix), \ 196 SFRB(SCL_V_NUM_TAPS_C, VPDSCL_TAP_CONTROL, post_fix), \ 197 SFRB(SCL_H_NUM_TAPS_C, VPDSCL_TAP_CONTROL, post_fix), \ 198 SFRB(SCL_BOUNDARY_MODE, VPDSCL_CONTROL, post_fix), \ 199 SFRB(SCL_H_2TAP_HARDCODE_COEF_EN, VPDSCL_2TAP_CONTROL, post_fix), \ 200 SFRB(SCL_H_2TAP_SHARP_EN, VPDSCL_2TAP_CONTROL, post_fix), \ 201 SFRB(SCL_H_2TAP_SHARP_FACTOR, VPDSCL_2TAP_CONTROL, post_fix), \ 202 SFRB(SCL_V_2TAP_HARDCODE_COEF_EN, VPDSCL_2TAP_CONTROL, post_fix), \ 203 SFRB(SCL_V_2TAP_SHARP_EN, VPDSCL_2TAP_CONTROL, post_fix), \ 204 SFRB(SCL_V_2TAP_SHARP_FACTOR, VPDSCL_2TAP_CONTROL, post_fix), \ 205 SFRB(SCL_V_MANUAL_REPLICATE_FACTOR, VPDSCL_MANUAL_REPLICATE_CONTROL, post_fix), \ 206 SFRB(SCL_H_MANUAL_REPLICATE_FACTOR, VPDSCL_MANUAL_REPLICATE_CONTROL, post_fix), \ 207 SFRB(SCL_H_SCALE_RATIO, VPDSCL_HORZ_FILTER_SCALE_RATIO, post_fix), \ 208 SFRB(SCL_H_INIT_FRAC, VPDSCL_HORZ_FILTER_INIT, post_fix), \ 209 SFRB(SCL_H_INIT_INT, VPDSCL_HORZ_FILTER_INIT, post_fix), \ 210 SFRB(SCL_H_SCALE_RATIO_C, VPDSCL_HORZ_FILTER_SCALE_RATIO_C, post_fix), \ 211 SFRB(SCL_H_INIT_FRAC_C, VPDSCL_HORZ_FILTER_INIT_C, post_fix), \ 212 SFRB(SCL_H_INIT_INT_C, VPDSCL_HORZ_FILTER_INIT_C, post_fix), \ 213 SFRB(SCL_V_SCALE_RATIO, VPDSCL_VERT_FILTER_SCALE_RATIO, post_fix), \ 214 SFRB(SCL_V_INIT_FRAC, VPDSCL_VERT_FILTER_INIT, post_fix), \ 215 SFRB(SCL_V_INIT_INT, VPDSCL_VERT_FILTER_INIT, post_fix), \ 216 SFRB(SCL_V_SCALE_RATIO_C, VPDSCL_VERT_FILTER_SCALE_RATIO_C, post_fix), \ 217 SFRB(SCL_V_INIT_FRAC_C, VPDSCL_VERT_FILTER_INIT_C, post_fix), \ 218 SFRB(SCL_V_INIT_INT_C, VPDSCL_VERT_FILTER_INIT_C, post_fix), \ 219 SFRB(SCL_BLACK_COLOR_RGB_Y, VPDSCL_BLACK_COLOR, post_fix), \ 220 SFRB(SCL_BLACK_COLOR_CBCR, VPDSCL_BLACK_COLOR, post_fix), \ 221 SFRB(SCL_UPDATE_PENDING, VPDSCL_UPDATE, post_fix), \ 222 SFRB(AUTOCAL_MODE, VPDSCL_AUTOCAL, post_fix), \ 223 SFRB(EXT_OVERSCAN_RIGHT, VPDSCL_EXT_OVERSCAN_LEFT_RIGHT, post_fix), \ 224 SFRB(EXT_OVERSCAN_LEFT, VPDSCL_EXT_OVERSCAN_LEFT_RIGHT, post_fix), \ 225 SFRB(EXT_OVERSCAN_BOTTOM, VPDSCL_EXT_OVERSCAN_TOP_BOTTOM, post_fix), \ 226 SFRB(EXT_OVERSCAN_TOP, VPDSCL_EXT_OVERSCAN_TOP_BOTTOM, post_fix), \ 227 SFRB(OTG_H_BLANK_START, VPOTG_H_BLANK, post_fix), \ 228 SFRB(OTG_H_BLANK_END, VPOTG_H_BLANK, post_fix), \ 229 SFRB(OTG_V_BLANK_START, VPOTG_V_BLANK, post_fix), \ 230 SFRB(OTG_V_BLANK_END, VPOTG_V_BLANK, post_fix), \ 231 SFRB(RECOUT_START_X, VPDSCL_RECOUT_START, post_fix), \ 232 SFRB(RECOUT_START_Y, VPDSCL_RECOUT_START, post_fix), \ 233 SFRB(RECOUT_WIDTH, VPDSCL_RECOUT_SIZE, post_fix), \ 234 SFRB(RECOUT_HEIGHT, VPDSCL_RECOUT_SIZE, post_fix), \ 235 SFRB(VPMPC_WIDTH, VPMPC_SIZE, post_fix), SFRB(VPMPC_HEIGHT, VPMPC_SIZE, post_fix), \ 236 SFRB(ALPHA_EN, VPLB_DATA_FORMAT, post_fix), \ 237 SFRB(LB_MAX_PARTITIONS, VPLB_MEMORY_CTRL, post_fix), \ 238 SFRB(LB_NUM_PARTITIONS, VPLB_MEMORY_CTRL, post_fix), \ 239 SFRB(LB_NUM_PARTITIONS_C, VPLB_MEMORY_CTRL, post_fix), \ 240 SFRB(V_COUNTER, VPLB_V_COUNTER, post_fix), SFRB(V_COUNTER_C, VPLB_V_COUNTER, post_fix), \ 241 SFRB(LUT_MEM_PWR_FORCE, VPDSCL_MEM_PWR_CTRL, post_fix), \ 242 SFRB(LUT_MEM_PWR_DIS, VPDSCL_MEM_PWR_CTRL, post_fix), \ 243 SFRB(LB_G1_MEM_PWR_FORCE, VPDSCL_MEM_PWR_CTRL, post_fix), \ 244 SFRB(LB_G1_MEM_PWR_DIS, VPDSCL_MEM_PWR_CTRL, post_fix), \ 245 SFRB(LB_G2_MEM_PWR_FORCE, VPDSCL_MEM_PWR_CTRL, post_fix), \ 246 SFRB(LB_G2_MEM_PWR_DIS, VPDSCL_MEM_PWR_CTRL, post_fix), \ 247 SFRB(LB_MEM_PWR_MODE, VPDSCL_MEM_PWR_CTRL, post_fix), \ 248 SFRB(LUT_MEM_PWR_STATE, VPDSCL_MEM_PWR_STATUS, post_fix), \ 249 SFRB(LB_G1_MEM_PWR_STATE, VPDSCL_MEM_PWR_STATUS, post_fix), \ 250 SFRB(LB_G2_MEM_PWR_STATE, VPDSCL_MEM_PWR_STATUS, post_fix), \ 251 SFRB(VPCM_BYPASS, VPCM_CONTROL, post_fix), \ 252 SFRB(VPCM_UPDATE_PENDING, VPCM_CONTROL, post_fix), \ 253 SFRB(VPCM_POST_CSC_MODE, VPCM_POST_CSC_CONTROL, post_fix), \ 254 SFRB(VPCM_POST_CSC_MODE_CURRENT, VPCM_POST_CSC_CONTROL, post_fix), \ 255 SFRB(VPCM_POST_CSC_C11, VPCM_POST_CSC_C11_C12, post_fix), \ 256 SFRB(VPCM_POST_CSC_C12, VPCM_POST_CSC_C11_C12, post_fix), \ 257 SFRB(VPCM_POST_CSC_C13, VPCM_POST_CSC_C13_C14, post_fix), \ 258 SFRB(VPCM_POST_CSC_C14, VPCM_POST_CSC_C13_C14, post_fix), \ 259 SFRB(VPCM_POST_CSC_C21, VPCM_POST_CSC_C21_C22, post_fix), \ 260 SFRB(VPCM_POST_CSC_C22, VPCM_POST_CSC_C21_C22, post_fix), \ 261 SFRB(VPCM_POST_CSC_C23, VPCM_POST_CSC_C23_C24, post_fix), \ 262 SFRB(VPCM_POST_CSC_C24, VPCM_POST_CSC_C23_C24, post_fix), \ 263 SFRB(VPCM_POST_CSC_C31, VPCM_POST_CSC_C31_C32, post_fix), \ 264 SFRB(VPCM_POST_CSC_C32, VPCM_POST_CSC_C31_C32, post_fix), \ 265 SFRB(VPCM_POST_CSC_C33, VPCM_POST_CSC_C33_C34, post_fix), \ 266 SFRB(VPCM_POST_CSC_C34, VPCM_POST_CSC_C33_C34, post_fix), \ 267 SFRB(VPCM_BIAS_CR_R, VPCM_BIAS_CR_R, post_fix), \ 268 SFRB(VPCM_BIAS_Y_G, VPCM_BIAS_Y_G_CB_B, post_fix), \ 269 SFRB(VPCM_BIAS_CB_B, VPCM_BIAS_Y_G_CB_B, post_fix), \ 270 SFRB(VPCM_GAMCOR_MODE, VPCM_GAMCOR_CONTROL, post_fix), \ 271 SFRB(VPCM_GAMCOR_PWL_DISABLE, VPCM_GAMCOR_CONTROL, post_fix), \ 272 SFRB(VPCM_GAMCOR_MODE_CURRENT, VPCM_GAMCOR_CONTROL, post_fix), \ 273 SFRB(VPCM_GAMCOR_SELECT_CURRENT, VPCM_GAMCOR_CONTROL, post_fix), \ 274 SFRB(VPCM_GAMCOR_LUT_INDEX, VPCM_GAMCOR_LUT_INDEX, post_fix), \ 275 SFRB(VPCM_GAMCOR_LUT_DATA, VPCM_GAMCOR_LUT_DATA, post_fix), \ 276 SFRB(VPCM_GAMCOR_LUT_WRITE_COLOR_MASK, VPCM_GAMCOR_LUT_CONTROL, post_fix), \ 277 SFRB(VPCM_GAMCOR_LUT_READ_COLOR_SEL, VPCM_GAMCOR_LUT_CONTROL, post_fix), \ 278 SFRB(VPCM_GAMCOR_LUT_READ_DBG, VPCM_GAMCOR_LUT_CONTROL, post_fix), \ 279 SFRB(VPCM_GAMCOR_LUT_HOST_SEL, VPCM_GAMCOR_LUT_CONTROL, post_fix), \ 280 SFRB(VPCM_GAMCOR_LUT_CONFIG_MODE, VPCM_GAMCOR_LUT_CONTROL, post_fix), \ 281 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION_START_B, VPCM_GAMCOR_RAMA_START_CNTL_B, post_fix), \ 282 SFRB( \ 283 VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B, VPCM_GAMCOR_RAMA_START_CNTL_B, post_fix), \ 284 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION_START_G, VPCM_GAMCOR_RAMA_START_CNTL_G, post_fix), \ 285 SFRB( \ 286 VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G, VPCM_GAMCOR_RAMA_START_CNTL_G, post_fix), \ 287 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION_START_R, VPCM_GAMCOR_RAMA_START_CNTL_R, post_fix), \ 288 SFRB( \ 289 VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R, VPCM_GAMCOR_RAMA_START_CNTL_R, post_fix), \ 290 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B, VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B, \ 291 post_fix), \ 292 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G, VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G, \ 293 post_fix), \ 294 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R, VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R, \ 295 post_fix), \ 296 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_B, VPCM_GAMCOR_RAMA_START_BASE_CNTL_B, \ 297 post_fix), \ 298 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_G, VPCM_GAMCOR_RAMA_START_BASE_CNTL_G, \ 299 post_fix), \ 300 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_R, VPCM_GAMCOR_RAMA_START_BASE_CNTL_R, \ 301 post_fix), \ 302 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_B, VPCM_GAMCOR_RAMA_END_CNTL1_B, post_fix), \ 303 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION_END_B, VPCM_GAMCOR_RAMA_END_CNTL2_B, post_fix), \ 304 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B, VPCM_GAMCOR_RAMA_END_CNTL2_B, post_fix), \ 305 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_G, VPCM_GAMCOR_RAMA_END_CNTL1_G, post_fix), \ 306 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION_END_G, VPCM_GAMCOR_RAMA_END_CNTL2_G, post_fix), \ 307 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G, VPCM_GAMCOR_RAMA_END_CNTL2_G, post_fix), \ 308 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_R, VPCM_GAMCOR_RAMA_END_CNTL1_R, post_fix), \ 309 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION_END_R, VPCM_GAMCOR_RAMA_END_CNTL2_R, post_fix), \ 310 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R, VPCM_GAMCOR_RAMA_END_CNTL2_R, post_fix), \ 311 SFRB(VPCM_GAMCOR_RAMA_OFFSET_B, VPCM_GAMCOR_RAMA_OFFSET_B, post_fix), \ 312 SFRB(VPCM_GAMCOR_RAMA_OFFSET_G, VPCM_GAMCOR_RAMA_OFFSET_G, post_fix), \ 313 SFRB(VPCM_GAMCOR_RAMA_OFFSET_R, VPCM_GAMCOR_RAMA_OFFSET_R, post_fix), \ 314 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_0_1, post_fix), \ 315 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_0_1, post_fix), \ 316 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_0_1, post_fix), \ 317 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_0_1, post_fix), \ 318 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_2_3, post_fix), \ 319 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_2_3, post_fix), \ 320 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_2_3, post_fix), \ 321 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_2_3, post_fix), \ 322 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_4_5, post_fix), \ 323 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_4_5, post_fix), \ 324 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_4_5, post_fix), \ 325 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_4_5, post_fix), \ 326 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_6_7, post_fix), \ 327 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_6_7, post_fix), \ 328 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_6_7, post_fix), \ 329 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_6_7, post_fix), \ 330 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_8_9, post_fix), \ 331 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_8_9, post_fix), \ 332 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_8_9, post_fix), \ 333 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_8_9, post_fix), \ 334 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_10_11, post_fix), \ 335 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_10_11, post_fix), \ 336 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_10_11, post_fix), \ 337 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_10_11, post_fix), \ 338 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_12_13, post_fix), \ 339 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_12_13, post_fix), \ 340 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_12_13, post_fix), \ 341 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_12_13, post_fix), \ 342 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_14_15, post_fix), \ 343 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_14_15, post_fix), \ 344 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_14_15, post_fix), \ 345 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_14_15, post_fix), \ 346 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_16_17, post_fix), \ 347 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_16_17, post_fix), \ 348 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_16_17, post_fix), \ 349 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_16_17, post_fix), \ 350 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_18_19, post_fix), \ 351 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_18_19, post_fix), \ 352 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_18_19, post_fix), \ 353 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_18_19, post_fix), \ 354 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_20_21, post_fix), \ 355 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_20_21, post_fix), \ 356 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_20_21, post_fix), \ 357 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_20_21, post_fix), \ 358 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_22_23, post_fix), \ 359 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_22_23, post_fix), \ 360 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_22_23, post_fix), \ 361 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_22_23, post_fix), \ 362 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_24_25, post_fix), \ 363 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_24_25, post_fix), \ 364 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_24_25, post_fix), \ 365 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_24_25, post_fix), \ 366 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_26_27, post_fix), \ 367 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_26_27, post_fix), \ 368 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_26_27, post_fix), \ 369 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_26_27, post_fix), \ 370 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_28_29, post_fix), \ 371 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_28_29, post_fix), \ 372 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_28_29, post_fix), \ 373 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_28_29, post_fix), \ 374 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_30_31, post_fix), \ 375 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_30_31, post_fix), \ 376 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_30_31, post_fix), \ 377 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_30_31, post_fix), \ 378 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_32_33, post_fix), \ 379 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_32_33, post_fix), \ 380 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET, VPCM_GAMCOR_RAMA_REGION_32_33, post_fix), \ 381 SFRB(VPCM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS, VPCM_GAMCOR_RAMA_REGION_32_33, post_fix), \ 382 SFRB(VPCM_HDR_MULT_COEF, VPCM_HDR_MULT_COEF, post_fix), \ 383 SFRB(GAMCOR_MEM_PWR_FORCE, VPCM_MEM_PWR_CTRL, post_fix), \ 384 SFRB(GAMCOR_MEM_PWR_DIS, VPCM_MEM_PWR_CTRL, post_fix), \ 385 SFRB(GAMCOR_MEM_PWR_STATE, VPCM_MEM_PWR_STATUS, post_fix), \ 386 SFRB(VPCM_DEALPHA_EN, VPCM_DEALPHA, post_fix), \ 387 SFRB(VPCM_DEALPHA_ABLND, VPCM_DEALPHA, post_fix), \ 388 SFRB(VPCM_BIAS_FORMAT, VPCM_COEF_FORMAT, post_fix), \ 389 SFRB(VPCM_POST_CSC_COEF_FORMAT, VPCM_COEF_FORMAT, post_fix), \ 390 SFRB(VPECLK_G_GATE_DISABLE, VPDPP_CONTROL, post_fix), \ 391 SFRB(VPECLK_G_VPDSCL_GATE_DISABLE, VPDPP_CONTROL, post_fix), \ 392 SFRB(VPDPP_FGCG_REP_DIS, VPDPP_CONTROL, post_fix), \ 393 SFRB(VPDPP_CRC_EN, VPDPP_CRC_CTRL, post_fix), \ 394 SFRB(VPDPP_CRC_CONT_EN, VPDPP_CRC_CTRL, post_fix), \ 395 SFRB(VPDPP_CRC_420_COMP_SEL, VPDPP_CRC_CTRL, post_fix), \ 396 SFRB(VPDPP_CRC_SRC_SEL, VPDPP_CRC_CTRL, post_fix), \ 397 SFRB(VPDPP_CRC_PIX_FORMAT_SEL, VPDPP_CRC_CTRL, post_fix), \ 398 SFRB(VPDPP_CRC_MASK, VPDPP_CRC_CTRL, post_fix) 399 400 #define DPP_FIELD_LIST_VPE10(post_fix) \ 401 DPP_FIELD_LIST_VPE10_COMMON(post_fix), \ 402 SFRB(ALPHA_2BIT_LUT0, VPCNVC_ALPHA_2BIT_LUT, post_fix), \ 403 SFRB(ALPHA_2BIT_LUT1, VPCNVC_ALPHA_2BIT_LUT, post_fix), \ 404 SFRB(ALPHA_2BIT_LUT2, VPCNVC_ALPHA_2BIT_LUT, post_fix), \ 405 SFRB(ALPHA_2BIT_LUT3, VPCNVC_ALPHA_2BIT_LUT, post_fix), \ 406 SFRB(VPCM_GAMUT_REMAP_MODE, VPCM_GAMUT_REMAP_CONTROL, post_fix), \ 407 SFRB(VPCM_GAMUT_REMAP_MODE_CURRENT, VPCM_GAMUT_REMAP_CONTROL, post_fix), \ 408 SFRB(VPCM_GAMUT_REMAP_C11, VPCM_GAMUT_REMAP_C11_C12, post_fix), \ 409 SFRB(VPCM_GAMUT_REMAP_C12, VPCM_GAMUT_REMAP_C11_C12, post_fix), \ 410 SFRB(VPCM_GAMUT_REMAP_C13, VPCM_GAMUT_REMAP_C13_C14, post_fix), \ 411 SFRB(VPCM_GAMUT_REMAP_C14, VPCM_GAMUT_REMAP_C13_C14, post_fix), \ 412 SFRB(VPCM_GAMUT_REMAP_C21, VPCM_GAMUT_REMAP_C21_C22, post_fix), \ 413 SFRB(VPCM_GAMUT_REMAP_C22, VPCM_GAMUT_REMAP_C21_C22, post_fix), \ 414 SFRB(VPCM_GAMUT_REMAP_C23, VPCM_GAMUT_REMAP_C23_C24, post_fix), \ 415 SFRB(VPCM_GAMUT_REMAP_C24, VPCM_GAMUT_REMAP_C23_C24, post_fix), \ 416 SFRB(VPCM_GAMUT_REMAP_C31, VPCM_GAMUT_REMAP_C31_C32, post_fix), \ 417 SFRB(VPCM_GAMUT_REMAP_C32, VPCM_GAMUT_REMAP_C31_C32, post_fix), \ 418 SFRB(VPCM_GAMUT_REMAP_C33, VPCM_GAMUT_REMAP_C33_C34, post_fix), \ 419 SFRB(VPCM_GAMUT_REMAP_C34, VPCM_GAMUT_REMAP_C33_C34, post_fix), \ 420 SFRB(VPCM_GAMUT_REMAP_COEF_FORMAT, VPCM_COEF_FORMAT, post_fix), \ 421 SFRB(MEMORY_CONFIG, VPLB_MEMORY_CTRL, post_fix), \ 422 SFRB(VPECLK_G_DYN_GATE_DISABLE, VPDPP_CONTROL, post_fix), \ 423 SFRB(VPECLK_R_GATE_DISABLE, VPDPP_CONTROL, post_fix), \ 424 SFRB(DISPCLK_R_GATE_DISABLE, VPDPP_CONTROL, post_fix), \ 425 SFRB(DISPCLK_G_GATE_DISABLE, VPDPP_CONTROL, post_fix), \ 426 SFRB(VPDPP_TEST_CLK_SEL, VPDPP_CONTROL, post_fix), \ 427 SFRB(VPDPP_CLOCK_ENABLE, VPDPP_CONTROL, post_fix) 428 429 430 #define DPP_REG_VARIABLE_LIST_VPE10_COMMON \ 431 reg_id_val VPCNVC_SURFACE_PIXEL_FORMAT; \ 432 reg_id_val VPCNVC_FORMAT_CONTROL; \ 433 reg_id_val VPCNVC_FCNV_FP_BIAS_R; \ 434 reg_id_val VPCNVC_FCNV_FP_BIAS_G; \ 435 reg_id_val VPCNVC_FCNV_FP_BIAS_B; \ 436 reg_id_val VPCNVC_FCNV_FP_SCALE_R; \ 437 reg_id_val VPCNVC_FCNV_FP_SCALE_G; \ 438 reg_id_val VPCNVC_FCNV_FP_SCALE_B; \ 439 reg_id_val VPCNVC_COLOR_KEYER_CONTROL; \ 440 reg_id_val VPCNVC_COLOR_KEYER_ALPHA; \ 441 reg_id_val VPCNVC_COLOR_KEYER_RED; \ 442 reg_id_val VPCNVC_COLOR_KEYER_GREEN; \ 443 reg_id_val VPCNVC_COLOR_KEYER_BLUE; \ 444 reg_id_val VPCNVC_PRE_DEALPHA; \ 445 reg_id_val VPCNVC_PRE_CSC_MODE; \ 446 reg_id_val VPCNVC_PRE_CSC_C11_C12; \ 447 reg_id_val VPCNVC_PRE_CSC_C13_C14; \ 448 reg_id_val VPCNVC_PRE_CSC_C21_C22; \ 449 reg_id_val VPCNVC_PRE_CSC_C23_C24; \ 450 reg_id_val VPCNVC_PRE_CSC_C31_C32; \ 451 reg_id_val VPCNVC_PRE_CSC_C33_C34; \ 452 reg_id_val VPCNVC_COEF_FORMAT; \ 453 reg_id_val VPCNVC_PRE_DEGAM; \ 454 reg_id_val VPCNVC_PRE_REALPHA; \ 455 reg_id_val VPDSCL_COEF_RAM_TAP_SELECT; \ 456 reg_id_val VPDSCL_COEF_RAM_TAP_DATA; \ 457 reg_id_val VPDSCL_MODE; \ 458 reg_id_val VPDSCL_TAP_CONTROL; \ 459 reg_id_val VPDSCL_CONTROL; \ 460 reg_id_val VPDSCL_2TAP_CONTROL; \ 461 reg_id_val VPDSCL_MANUAL_REPLICATE_CONTROL; \ 462 reg_id_val VPDSCL_HORZ_FILTER_SCALE_RATIO; \ 463 reg_id_val VPDSCL_HORZ_FILTER_INIT; \ 464 reg_id_val VPDSCL_HORZ_FILTER_SCALE_RATIO_C; \ 465 reg_id_val VPDSCL_HORZ_FILTER_INIT_C; \ 466 reg_id_val VPDSCL_VERT_FILTER_SCALE_RATIO; \ 467 reg_id_val VPDSCL_VERT_FILTER_INIT; \ 468 reg_id_val VPDSCL_VERT_FILTER_SCALE_RATIO_C; \ 469 reg_id_val VPDSCL_VERT_FILTER_INIT_C; \ 470 reg_id_val VPDSCL_BLACK_COLOR; \ 471 reg_id_val VPDSCL_UPDATE; \ 472 reg_id_val VPDSCL_AUTOCAL; \ 473 reg_id_val VPDSCL_EXT_OVERSCAN_LEFT_RIGHT; \ 474 reg_id_val VPDSCL_EXT_OVERSCAN_TOP_BOTTOM; \ 475 reg_id_val VPOTG_H_BLANK; \ 476 reg_id_val VPOTG_V_BLANK; \ 477 reg_id_val VPDSCL_RECOUT_START; \ 478 reg_id_val VPDSCL_RECOUT_SIZE; \ 479 reg_id_val VPMPC_SIZE; \ 480 reg_id_val VPLB_DATA_FORMAT; \ 481 reg_id_val VPLB_MEMORY_CTRL; \ 482 reg_id_val VPLB_V_COUNTER; \ 483 reg_id_val VPDSCL_MEM_PWR_CTRL; \ 484 reg_id_val VPDSCL_MEM_PWR_STATUS; \ 485 reg_id_val VPCM_CONTROL; \ 486 reg_id_val VPCM_POST_CSC_CONTROL; \ 487 reg_id_val VPCM_POST_CSC_C11_C12; \ 488 reg_id_val VPCM_POST_CSC_C13_C14; \ 489 reg_id_val VPCM_POST_CSC_C21_C22; \ 490 reg_id_val VPCM_POST_CSC_C23_C24; \ 491 reg_id_val VPCM_POST_CSC_C31_C32; \ 492 reg_id_val VPCM_POST_CSC_C33_C34; \ 493 reg_id_val VPCM_BIAS_CR_R; \ 494 reg_id_val VPCM_BIAS_Y_G_CB_B; \ 495 reg_id_val VPCM_GAMCOR_CONTROL; \ 496 reg_id_val VPCM_GAMCOR_LUT_INDEX; \ 497 reg_id_val VPCM_GAMCOR_LUT_DATA; \ 498 reg_id_val VPCM_GAMCOR_LUT_CONTROL; \ 499 reg_id_val VPCM_GAMCOR_RAMA_START_CNTL_B; \ 500 reg_id_val VPCM_GAMCOR_RAMA_START_CNTL_G; \ 501 reg_id_val VPCM_GAMCOR_RAMA_START_CNTL_R; \ 502 reg_id_val VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B; \ 503 reg_id_val VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G; \ 504 reg_id_val VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R; \ 505 reg_id_val VPCM_GAMCOR_RAMA_START_BASE_CNTL_B; \ 506 reg_id_val VPCM_GAMCOR_RAMA_START_BASE_CNTL_G; \ 507 reg_id_val VPCM_GAMCOR_RAMA_START_BASE_CNTL_R; \ 508 reg_id_val VPCM_GAMCOR_RAMA_END_CNTL1_B; \ 509 reg_id_val VPCM_GAMCOR_RAMA_END_CNTL2_B; \ 510 reg_id_val VPCM_GAMCOR_RAMA_END_CNTL1_G; \ 511 reg_id_val VPCM_GAMCOR_RAMA_END_CNTL2_G; \ 512 reg_id_val VPCM_GAMCOR_RAMA_END_CNTL1_R; \ 513 reg_id_val VPCM_GAMCOR_RAMA_END_CNTL2_R; \ 514 reg_id_val VPCM_GAMCOR_RAMA_OFFSET_B; \ 515 reg_id_val VPCM_GAMCOR_RAMA_OFFSET_G; \ 516 reg_id_val VPCM_GAMCOR_RAMA_OFFSET_R; \ 517 reg_id_val VPCM_GAMCOR_RAMA_REGION_0_1; \ 518 reg_id_val VPCM_GAMCOR_RAMA_REGION_2_3; \ 519 reg_id_val VPCM_GAMCOR_RAMA_REGION_4_5; \ 520 reg_id_val VPCM_GAMCOR_RAMA_REGION_6_7; \ 521 reg_id_val VPCM_GAMCOR_RAMA_REGION_8_9; \ 522 reg_id_val VPCM_GAMCOR_RAMA_REGION_10_11; \ 523 reg_id_val VPCM_GAMCOR_RAMA_REGION_12_13; \ 524 reg_id_val VPCM_GAMCOR_RAMA_REGION_14_15; \ 525 reg_id_val VPCM_GAMCOR_RAMA_REGION_16_17; \ 526 reg_id_val VPCM_GAMCOR_RAMA_REGION_18_19; \ 527 reg_id_val VPCM_GAMCOR_RAMA_REGION_20_21; \ 528 reg_id_val VPCM_GAMCOR_RAMA_REGION_22_23; \ 529 reg_id_val VPCM_GAMCOR_RAMA_REGION_24_25; \ 530 reg_id_val VPCM_GAMCOR_RAMA_REGION_26_27; \ 531 reg_id_val VPCM_GAMCOR_RAMA_REGION_28_29; \ 532 reg_id_val VPCM_GAMCOR_RAMA_REGION_30_31; \ 533 reg_id_val VPCM_GAMCOR_RAMA_REGION_32_33; \ 534 reg_id_val VPCM_HDR_MULT_COEF; \ 535 reg_id_val VPCM_MEM_PWR_CTRL; \ 536 reg_id_val VPCM_MEM_PWR_STATUS; \ 537 reg_id_val VPCM_DEALPHA; \ 538 reg_id_val VPCM_COEF_FORMAT; \ 539 reg_id_val VPDPP_CONTROL; \ 540 reg_id_val VPDPP_CRC_CTRL; 541 542 #define DPP_REG_VARIABLE_LIST_VPE10 \ 543 DPP_REG_VARIABLE_LIST_VPE10_COMMON \ 544 reg_id_val VPCNVC_ALPHA_2BIT_LUT; \ 545 reg_id_val VPCM_GAMUT_REMAP_CONTROL; \ 546 reg_id_val VPCM_GAMUT_REMAP_C11_C12; \ 547 reg_id_val VPCM_GAMUT_REMAP_C13_C14; \ 548 reg_id_val VPCM_GAMUT_REMAP_C21_C22; \ 549 reg_id_val VPCM_GAMUT_REMAP_C23_C24; \ 550 reg_id_val VPCM_GAMUT_REMAP_C31_C32; \ 551 reg_id_val VPCM_GAMUT_REMAP_C33_C34; 552 553 #define DPP_FIELD_VARIABLE_LIST_VPE10(type) \ 554 type VPCNVC_SURFACE_PIXEL_FORMAT; \ 555 type FORMAT_EXPANSION_MODE; \ 556 type FORMAT_CNV16; \ 557 type FORMAT_CONTROL__ALPHA_EN; \ 558 type VPCNVC_BYPASS; \ 559 type VPCNVC_BYPASS_MSB_ALIGN; \ 560 type CLAMP_POSITIVE; \ 561 type CLAMP_POSITIVE_C; \ 562 type VPCNVC_UPDATE_PENDING; \ 563 type FCNV_FP_BIAS_R; \ 564 type FCNV_FP_BIAS_G; \ 565 type FCNV_FP_BIAS_B; \ 566 type FCNV_FP_SCALE_R; \ 567 type FCNV_FP_SCALE_G; \ 568 type FCNV_FP_SCALE_B; \ 569 type COLOR_KEYER_EN; \ 570 type COLOR_KEYER_MODE; \ 571 type COLOR_KEYER_ALPHA_LOW; \ 572 type COLOR_KEYER_ALPHA_HIGH; \ 573 type COLOR_KEYER_RED_LOW; \ 574 type COLOR_KEYER_RED_HIGH; \ 575 type COLOR_KEYER_GREEN_LOW; \ 576 type COLOR_KEYER_GREEN_HIGH; \ 577 type COLOR_KEYER_BLUE_LOW; \ 578 type COLOR_KEYER_BLUE_HIGH; \ 579 type ALPHA_2BIT_LUT0; \ 580 type ALPHA_2BIT_LUT1; \ 581 type ALPHA_2BIT_LUT2; \ 582 type ALPHA_2BIT_LUT3; \ 583 type PRE_DEALPHA_EN; \ 584 type PRE_DEALPHA_ABLND_EN; \ 585 type PRE_CSC_MODE; \ 586 type PRE_CSC_MODE_CURRENT; \ 587 type PRE_CSC_C11; \ 588 type PRE_CSC_C12; \ 589 type PRE_CSC_C13; \ 590 type PRE_CSC_C14; \ 591 type PRE_CSC_C21; \ 592 type PRE_CSC_C22; \ 593 type PRE_CSC_C23; \ 594 type PRE_CSC_C24; \ 595 type PRE_CSC_C31; \ 596 type PRE_CSC_C32; \ 597 type PRE_CSC_C33; \ 598 type PRE_CSC_C34; \ 599 type PRE_CSC_COEF_FORMAT; \ 600 type PRE_DEGAM_MODE; \ 601 type PRE_DEGAM_SELECT; \ 602 type PRE_REALPHA_EN; \ 603 type PRE_REALPHA_ABLND_EN; \ 604 type SCL_COEF_RAM_TAP_PAIR_IDX; \ 605 type SCL_COEF_RAM_PHASE; \ 606 type SCL_COEF_RAM_FILTER_TYPE; \ 607 type SCL_COEF_RAM_EVEN_TAP_COEF; \ 608 type SCL_COEF_RAM_EVEN_TAP_COEF_EN; \ 609 type SCL_COEF_RAM_ODD_TAP_COEF; \ 610 type SCL_COEF_RAM_ODD_TAP_COEF_EN; \ 611 type VPDSCL_MODE; \ 612 type SCL_COEF_RAM_SELECT_CURRENT; \ 613 type SCL_CHROMA_COEF_MODE; \ 614 type SCL_ALPHA_COEF_MODE; \ 615 type SCL_COEF_RAM_SELECT_RD; \ 616 type SCL_V_NUM_TAPS; \ 617 type SCL_H_NUM_TAPS; \ 618 type SCL_V_NUM_TAPS_C; \ 619 type SCL_H_NUM_TAPS_C; \ 620 type SCL_BOUNDARY_MODE; \ 621 type SCL_H_2TAP_HARDCODE_COEF_EN; \ 622 type SCL_H_2TAP_SHARP_EN; \ 623 type SCL_H_2TAP_SHARP_FACTOR; \ 624 type SCL_V_2TAP_HARDCODE_COEF_EN; \ 625 type SCL_V_2TAP_SHARP_EN; \ 626 type SCL_V_2TAP_SHARP_FACTOR; \ 627 type SCL_V_MANUAL_REPLICATE_FACTOR; \ 628 type SCL_H_MANUAL_REPLICATE_FACTOR; \ 629 type SCL_H_SCALE_RATIO; \ 630 type SCL_H_INIT_FRAC; \ 631 type SCL_H_INIT_INT; \ 632 type SCL_H_SCALE_RATIO_C; \ 633 type SCL_H_INIT_FRAC_C; \ 634 type SCL_H_INIT_INT_C; \ 635 type SCL_V_SCALE_RATIO; \ 636 type SCL_V_INIT_FRAC; \ 637 type SCL_V_INIT_INT; \ 638 type SCL_V_SCALE_RATIO_C; \ 639 type SCL_V_INIT_FRAC_C; \ 640 type SCL_V_INIT_INT_C; \ 641 type SCL_BLACK_COLOR_RGB_Y; \ 642 type SCL_BLACK_COLOR_CBCR; \ 643 type SCL_UPDATE_PENDING; \ 644 type AUTOCAL_MODE; \ 645 type EXT_OVERSCAN_RIGHT; \ 646 type EXT_OVERSCAN_LEFT; \ 647 type EXT_OVERSCAN_BOTTOM; \ 648 type EXT_OVERSCAN_TOP; \ 649 type OTG_H_BLANK_START; \ 650 type OTG_H_BLANK_END; \ 651 type OTG_V_BLANK_START; \ 652 type OTG_V_BLANK_END; \ 653 type RECOUT_START_X; \ 654 type RECOUT_START_Y; \ 655 type RECOUT_WIDTH; \ 656 type RECOUT_HEIGHT; \ 657 type VPMPC_WIDTH; \ 658 type VPMPC_HEIGHT; \ 659 type ALPHA_EN; \ 660 type MEMORY_CONFIG; \ 661 type LB_MAX_PARTITIONS; \ 662 type LB_NUM_PARTITIONS; \ 663 type LB_NUM_PARTITIONS_C; \ 664 type V_COUNTER; \ 665 type V_COUNTER_C; \ 666 type LUT_MEM_PWR_FORCE; \ 667 type LUT_MEM_PWR_DIS; \ 668 type LB_G1_MEM_PWR_FORCE; \ 669 type LB_G1_MEM_PWR_DIS; \ 670 type LB_G2_MEM_PWR_FORCE; \ 671 type LB_G2_MEM_PWR_DIS; \ 672 type LB_MEM_PWR_MODE; \ 673 type LUT_MEM_PWR_STATE; \ 674 type LB_G1_MEM_PWR_STATE; \ 675 type LB_G2_MEM_PWR_STATE; \ 676 type VPCM_BYPASS; \ 677 type VPCM_UPDATE_PENDING; \ 678 type VPCM_POST_CSC_MODE; \ 679 type VPCM_POST_CSC_MODE_CURRENT; \ 680 type VPCM_POST_CSC_C11; \ 681 type VPCM_POST_CSC_C12; \ 682 type VPCM_POST_CSC_C13; \ 683 type VPCM_POST_CSC_C14; \ 684 type VPCM_POST_CSC_C21; \ 685 type VPCM_POST_CSC_C22; \ 686 type VPCM_POST_CSC_C23; \ 687 type VPCM_POST_CSC_C24; \ 688 type VPCM_POST_CSC_C31; \ 689 type VPCM_POST_CSC_C32; \ 690 type VPCM_POST_CSC_C33; \ 691 type VPCM_POST_CSC_C34; \ 692 type VPCM_GAMUT_REMAP_MODE; \ 693 type VPCM_GAMUT_REMAP_MODE_CURRENT; \ 694 type VPCM_GAMUT_REMAP_C11; \ 695 type VPCM_GAMUT_REMAP_C12; \ 696 type VPCM_GAMUT_REMAP_C13; \ 697 type VPCM_GAMUT_REMAP_C14; \ 698 type VPCM_GAMUT_REMAP_C21; \ 699 type VPCM_GAMUT_REMAP_C22; \ 700 type VPCM_GAMUT_REMAP_C23; \ 701 type VPCM_GAMUT_REMAP_C24; \ 702 type VPCM_GAMUT_REMAP_C31; \ 703 type VPCM_GAMUT_REMAP_C32; \ 704 type VPCM_GAMUT_REMAP_C33; \ 705 type VPCM_GAMUT_REMAP_C34; \ 706 type VPCM_BIAS_CR_R; \ 707 type VPCM_BIAS_Y_G; \ 708 type VPCM_BIAS_CB_B; \ 709 type VPCM_GAMCOR_MODE; \ 710 type VPCM_GAMCOR_PWL_DISABLE; \ 711 type VPCM_GAMCOR_MODE_CURRENT; \ 712 type VPCM_GAMCOR_SELECT_CURRENT; \ 713 type VPCM_GAMCOR_LUT_INDEX; \ 714 type VPCM_GAMCOR_LUT_DATA; \ 715 type VPCM_GAMCOR_LUT_WRITE_COLOR_MASK; \ 716 type VPCM_GAMCOR_LUT_READ_COLOR_SEL; \ 717 type VPCM_GAMCOR_LUT_READ_DBG; \ 718 type VPCM_GAMCOR_LUT_HOST_SEL; \ 719 type VPCM_GAMCOR_LUT_CONFIG_MODE; \ 720 type VPCM_GAMCOR_RAMA_EXP_REGION_START_B; \ 721 type VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B; \ 722 type VPCM_GAMCOR_RAMA_EXP_REGION_START_G; \ 723 type VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G; \ 724 type VPCM_GAMCOR_RAMA_EXP_REGION_START_R; \ 725 type VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R; \ 726 type VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B; \ 727 type VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G; \ 728 type VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R; \ 729 type VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_B; \ 730 type VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_G; \ 731 type VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_R; \ 732 type VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_B; \ 733 type VPCM_GAMCOR_RAMA_EXP_REGION_END_B; \ 734 type VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B; \ 735 type VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_G; \ 736 type VPCM_GAMCOR_RAMA_EXP_REGION_END_G; \ 737 type VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G; \ 738 type VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_R; \ 739 type VPCM_GAMCOR_RAMA_EXP_REGION_END_R; \ 740 type VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R; \ 741 type VPCM_GAMCOR_RAMA_OFFSET_B; \ 742 type VPCM_GAMCOR_RAMA_OFFSET_G; \ 743 type VPCM_GAMCOR_RAMA_OFFSET_R; \ 744 type VPCM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET; \ 745 type VPCM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS; \ 746 type VPCM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET; \ 747 type VPCM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS; \ 748 type VPCM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET; \ 749 type VPCM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS; \ 750 type VPCM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET; \ 751 type VPCM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS; \ 752 type VPCM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET; \ 753 type VPCM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS; \ 754 type VPCM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET; \ 755 type VPCM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS; \ 756 type VPCM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET; \ 757 type VPCM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS; \ 758 type VPCM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET; \ 759 type VPCM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS; \ 760 type VPCM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET; \ 761 type VPCM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS; \ 762 type VPCM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET; \ 763 type VPCM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS; \ 764 type VPCM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET; \ 765 type VPCM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS; \ 766 type VPCM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET; \ 767 type VPCM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS; \ 768 type VPCM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET; \ 769 type VPCM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS; \ 770 type VPCM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET; \ 771 type VPCM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS; \ 772 type VPCM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET; \ 773 type VPCM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS; \ 774 type VPCM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET; \ 775 type VPCM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS; \ 776 type VPCM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET; \ 777 type VPCM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS; \ 778 type VPCM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET; \ 779 type VPCM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS; \ 780 type VPCM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET; \ 781 type VPCM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS; \ 782 type VPCM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET; \ 783 type VPCM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS; \ 784 type VPCM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET; \ 785 type VPCM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS; \ 786 type VPCM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET; \ 787 type VPCM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS; \ 788 type VPCM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET; \ 789 type VPCM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS; \ 790 type VPCM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET; \ 791 type VPCM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS; \ 792 type VPCM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET; \ 793 type VPCM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS; \ 794 type VPCM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET; \ 795 type VPCM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS; \ 796 type VPCM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET; \ 797 type VPCM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS; \ 798 type VPCM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET; \ 799 type VPCM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS; \ 800 type VPCM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET; \ 801 type VPCM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS; \ 802 type VPCM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET; \ 803 type VPCM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS; \ 804 type VPCM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET; \ 805 type VPCM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS; \ 806 type VPCM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET; \ 807 type VPCM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS; \ 808 type VPCM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET; \ 809 type VPCM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS; \ 810 type VPCM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET; \ 811 type VPCM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS; \ 812 type VPCM_HDR_MULT_COEF; \ 813 type GAMCOR_MEM_PWR_FORCE; \ 814 type GAMCOR_MEM_PWR_DIS; \ 815 type GAMCOR_MEM_PWR_STATE; \ 816 type VPCM_DEALPHA_EN; \ 817 type VPCM_DEALPHA_ABLND; \ 818 type VPCM_BIAS_FORMAT; \ 819 type VPCM_POST_CSC_COEF_FORMAT; \ 820 type VPCM_GAMUT_REMAP_COEF_FORMAT; \ 821 type VPDPP_CLOCK_ENABLE; \ 822 type VPECLK_G_GATE_DISABLE; \ 823 type VPECLK_G_DYN_GATE_DISABLE; \ 824 type VPECLK_G_VPDSCL_GATE_DISABLE; \ 825 type VPECLK_R_GATE_DISABLE; \ 826 type DISPCLK_R_GATE_DISABLE; \ 827 type DISPCLK_G_GATE_DISABLE; \ 828 type VPDPP_FGCG_REP_DIS; \ 829 type VPDPP_TEST_CLK_SEL; \ 830 type VPDPP_CRC_EN; \ 831 type VPDPP_CRC_CONT_EN; \ 832 type VPDPP_CRC_420_COMP_SEL; \ 833 type VPDPP_CRC_SRC_SEL; \ 834 type VPDPP_CRC_PIX_FORMAT_SEL; \ 835 type VPDPP_CRC_MASK; 836 837 #define IDENTITY_RATIO(ratio) (vpe_fixpt_u3d19(ratio) == (1 << 19)) 838 839 struct vpe10_dpp_registers { 840 DPP_REG_VARIABLE_LIST_VPE10 841 }; 842 843 struct vpe10_dpp_shift { 844 DPP_FIELD_VARIABLE_LIST_VPE10(uint8_t) 845 }; 846 847 struct vpe10_dpp_mask { 848 DPP_FIELD_VARIABLE_LIST_VPE10(uint32_t) 849 }; 850 851 struct vpe10_dpp { 852 struct dpp base; // base class, must be the 1st field 853 struct vpe10_dpp_registers *regs; 854 const struct vpe10_dpp_shift *shift; 855 const struct vpe10_dpp_mask *mask; 856 }; 857 858 void vpe10_construct_dpp(struct vpe_priv *vpe_priv, struct dpp *dpp); 859 860 bool vpe10_dpp_get_optimal_number_of_taps( 861 struct vpe_rect *src_rect, struct vpe_rect *dst_rect, struct vpe_scaling_taps *taps); 862 863 void vpe10_dscl_calc_lb_num_partitions(const struct scaler_data *scl_data, 864 enum lb_memory_config lb_config, uint32_t *num_part_y, uint32_t *num_part_c); 865 866 /***** share register programming *****/ 867 void vpe10_dpp_program_cnv( 868 struct dpp *dpp, enum vpe_surface_pixel_format format, enum vpe_expansion_mode mode); 869 870 void vpe10_dpp_cnv_program_pre_dgam(struct dpp *dpp, enum color_transfer_func tr); 871 872 void vpe10_dpp_program_cnv_bias_scale(struct dpp *dpp, struct bias_and_scale *bias_and_scale); 873 874 void vpe10_dpp_build_keyer_params( 875 struct dpp *dpp, const struct stream_ctx *stream_ctx, struct cnv_keyer_params *keyer_params); 876 877 void vpe10_dpp_cnv_program_alpha_keyer( 878 struct dpp *dpp, const struct cnv_keyer_params *keyer_params); 879 880 void vpe10_dpp_program_input_transfer_func(struct dpp *dpp, struct transfer_func *input_tf); 881 882 void vpe10_dpp_program_gamut_remap(struct dpp *dpp, struct colorspace_transform *gamut_remap); 883 884 /*program post scaler scs block in dpp CM*/ 885 void vpe10_dpp_program_post_csc(struct dpp *dpp, enum color_space color_space, 886 enum input_csc_select input_select, struct vpe_csc_matrix *input_cs); 887 888 void vpe10_dpp_set_hdr_multiplier(struct dpp *dpp, uint32_t multiplier); 889 890 /*Program Scaler*/ 891 void vpe10_dpp_set_segment_scaler(struct dpp *dpp, const struct scaler_data *scl_data); 892 893 void vpe10_dpp_set_frame_scaler(struct dpp *dpp, const struct scaler_data *scl_data); 894 895 /*Scalar helper functions*/ 896 enum vpe10_coef_filter_type_sel { 897 SCL_COEF_LUMA_VERT_FILTER = 0, 898 SCL_COEF_LUMA_HORZ_FILTER = 1, 899 SCL_COEF_CHROMA_VERT_FILTER = 2, 900 SCL_COEF_CHROMA_HORZ_FILTER = 3, 901 SCL_COEF_ALPHA_VERT_FILTER = 4, 902 SCL_COEF_ALPHA_HORZ_FILTER = 5, 903 }; 904 905 enum vpe10_dscl_autocal_mode { 906 AUTOCAL_MODE_OFF = 0, 907 908 /* Autocal calculate the scaling ratio and initial phase and the 909 * DSCL_MODE_SEL must be set to 1 910 */ 911 AUTOCAL_MODE_AUTOSCALE = 1, 912 /* Autocal perform auto centering without replication and the 913 * DSCL_MODE_SEL must be set to 0 914 */ 915 AUTOCAL_MODE_AUTOCENTER = 2, 916 /* Autocal perform auto centering and auto replication and the 917 * DSCL_MODE_SEL must be set to 0 918 */ 919 AUTOCAL_MODE_AUTOREPLICATE = 3 920 }; 921 922 enum vpe10_dscl_mode_sel { 923 DSCL_MODE_SCALING_444_BYPASS = 0, 924 DSCL_MODE_SCALING_444_RGB_ENABLE = 1, 925 DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2, 926 DSCL_MODE_SCALING_420_YCBCR_ENABLE = 3, 927 DSCL_MODE_SCALING_420_LUMA_BYPASS = 4, 928 DSCL_MODE_SCALING_420_CHROMA_BYPASS = 5, 929 DSCL_MODE_DSCL_BYPASS = 6 930 }; 931 void vpe10_dpp_dscl_set_h_blank(struct dpp *dpp, uint16_t start, uint16_t end); 932 933 void vpe10_dpp_dscl_set_v_blank(struct dpp *dpp, uint16_t start, uint16_t end); 934 935 void vpe10_dpp_power_on_dscl(struct dpp *dpp, bool power_on); 936 937 void vpe10_dpp_dscl_set_lb(struct dpp *dpp, const struct line_buffer_params *lb_params, 938 enum lb_memory_config mem_size_config); 939 940 void vpe10_dpp_dscl_set_scale_ratio(struct dpp *dpp, const struct scaler_data *data); 941 942 void vpe10_dpp_dscl_set_taps(struct dpp *dpp, const struct scaler_data *scl_data); 943 944 void vpe10_dpp_dscl_set_scl_filter(struct dpp *dpp, const struct scaler_data *scl_data, 945 enum vpe10_dscl_mode_sel scl_mode, bool chroma_coef_mode); 946 947 void vpe10_dpp_dscl_set_dscl_mode(struct dpp *dpp, enum vpe10_dscl_mode_sel dscl_mode); 948 949 enum vpe10_dscl_mode_sel vpe10_dpp_dscl_get_dscl_mode(const struct scaler_data *data); 950 951 void vpe10_dpp_dscl_set_scaler_filter(struct dpp *dpp, uint32_t taps, 952 enum vpe10_coef_filter_type_sel filter_type, const uint16_t *filter); 953 954 bool vpe10_dpp_dscl_is_ycbcr(const enum vpe_surface_pixel_format format); 955 956 void vpe10_dpp_program_gamcor_lut(struct dpp *dpp, const struct pwl_params *params); 957 958 uint32_t vpe10_get_line_buffer_size(void); 959 960 bool vpe10_dpp_validate_number_of_taps(struct dpp *dpp, struct scaler_data *scl_data); 961 962 void vpe10_dpp_program_crc(struct dpp *dpp, bool enable); 963 #ifdef __cplusplus 964 } 965 #endif 966