1 /* 2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef ARCH_H 9 #define ARCH_H 10 11 #include <lib/utils_def.h> 12 13 /******************************************************************************* 14 * MIDR bit definitions 15 ******************************************************************************/ 16 #define MIDR_IMPL_MASK U(0xff) 17 #define MIDR_IMPL_SHIFT U(0x18) 18 #define MIDR_VAR_SHIFT U(20) 19 #define MIDR_VAR_BITS U(4) 20 #define MIDR_VAR_MASK U(0xf) 21 #define MIDR_REV_SHIFT U(0) 22 #define MIDR_REV_BITS U(4) 23 #define MIDR_REV_MASK U(0xf) 24 #define MIDR_PN_MASK U(0xfff) 25 #define MIDR_PN_SHIFT U(0x4) 26 27 /* Extracts the CPU part number from MIDR for checking CPU match */ 28 #define EXTRACT_PARTNUM(x) ((x >> MIDR_PN_SHIFT) & MIDR_PN_MASK) 29 30 /******************************************************************************* 31 * MPIDR macros 32 ******************************************************************************/ 33 #define MPIDR_MT_MASK (ULL(1) << 24) 34 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 35 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 36 #define MPIDR_AFFINITY_BITS U(8) 37 #define MPIDR_AFFLVL_MASK ULL(0xff) 38 #define MPIDR_AFF0_SHIFT U(0) 39 #define MPIDR_AFF1_SHIFT U(8) 40 #define MPIDR_AFF2_SHIFT U(16) 41 #define MPIDR_AFF3_SHIFT U(32) 42 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 43 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) 44 #define MPIDR_AFFLVL_SHIFT U(3) 45 #define MPIDR_AFFLVL0 ULL(0x0) 46 #define MPIDR_AFFLVL1 ULL(0x1) 47 #define MPIDR_AFFLVL2 ULL(0x2) 48 #define MPIDR_AFFLVL3 ULL(0x3) 49 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 50 #define MPIDR_AFFLVL0_VAL(mpidr) \ 51 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 52 #define MPIDR_AFFLVL1_VAL(mpidr) \ 53 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 54 #define MPIDR_AFFLVL2_VAL(mpidr) \ 55 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 56 #define MPIDR_AFFLVL3_VAL(mpidr) \ 57 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) 58 /* 59 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 60 * add one while using this macro to define array sizes. 61 * TODO: Support only the first 3 affinity levels for now. 62 */ 63 #define MPIDR_MAX_AFFLVL U(2) 64 65 #define MPID_MASK (MPIDR_MT_MASK | \ 66 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ 67 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ 68 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ 69 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 70 71 #define MPIDR_AFF_ID(mpid, n) \ 72 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 73 74 /* 75 * An invalid MPID. This value can be used by functions that return an MPID to 76 * indicate an error. 77 */ 78 #define INVALID_MPID U(0xFFFFFFFF) 79 80 /******************************************************************************* 81 * Definitions for Exception vector offsets 82 ******************************************************************************/ 83 #define CURRENT_EL_SP0 0x0 84 #define CURRENT_EL_SPX 0x200 85 #define LOWER_EL_AARCH64 0x400 86 #define LOWER_EL_AARCH32 0x600 87 88 #define SYNC_EXCEPTION 0x0 89 #define IRQ_EXCEPTION 0x80 90 #define FIQ_EXCEPTION 0x100 91 #define SERROR_EXCEPTION 0x180 92 93 /******************************************************************************* 94 * Definitions for CPU system register interface to GICv3 95 ******************************************************************************/ 96 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 97 #define ICC_SGI1R S3_0_C12_C11_5 98 #define ICC_ASGI1R S3_0_C12_C11_6 99 #define ICC_SRE_EL1 S3_0_C12_C12_5 100 #define ICC_SRE_EL2 S3_4_C12_C9_5 101 #define ICC_SRE_EL3 S3_6_C12_C12_5 102 #define ICC_CTLR_EL1 S3_0_C12_C12_4 103 #define ICC_CTLR_EL3 S3_6_C12_C12_4 104 #define ICC_PMR_EL1 S3_0_C4_C6_0 105 #define ICC_RPR_EL1 S3_0_C12_C11_3 106 #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 107 #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 108 #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 109 #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 110 #define ICC_IAR0_EL1 S3_0_c12_c8_0 111 #define ICC_IAR1_EL1 S3_0_c12_c12_0 112 #define ICC_EOIR0_EL1 S3_0_c12_c8_1 113 #define ICC_EOIR1_EL1 S3_0_c12_c12_1 114 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 115 116 /******************************************************************************* 117 * Definitions for EL2 system registers for save/restore routine 118 ******************************************************************************/ 119 #define CNTPOFF_EL2 S3_4_C14_C0_6 120 #define HDFGRTR2_EL2 S3_4_C3_C1_0 121 #define HDFGWTR2_EL2 S3_4_C3_C1_1 122 #define HFGRTR2_EL2 S3_4_C3_C1_2 123 #define HFGWTR2_EL2 S3_4_C3_C1_3 124 #define HDFGRTR_EL2 S3_4_C3_C1_4 125 #define HDFGWTR_EL2 S3_4_C3_C1_5 126 #define HAFGRTR_EL2 S3_4_C3_C1_6 127 #define HFGITR2_EL2 S3_4_C3_C1_7 128 #define HFGITR_EL2 S3_4_C1_C1_6 129 #define HFGRTR_EL2 S3_4_C1_C1_4 130 #define HFGWTR_EL2 S3_4_C1_C1_5 131 #define ICH_HCR_EL2 S3_4_C12_C11_0 132 #define ICH_VMCR_EL2 S3_4_C12_C11_7 133 #define MPAMVPM0_EL2 S3_4_C10_C6_0 134 #define MPAMVPM1_EL2 S3_4_C10_C6_1 135 #define MPAMVPM2_EL2 S3_4_C10_C6_2 136 #define MPAMVPM3_EL2 S3_4_C10_C6_3 137 #define MPAMVPM4_EL2 S3_4_C10_C6_4 138 #define MPAMVPM5_EL2 S3_4_C10_C6_5 139 #define MPAMVPM6_EL2 S3_4_C10_C6_6 140 #define MPAMVPM7_EL2 S3_4_C10_C6_7 141 #define MPAMVPMV_EL2 S3_4_C10_C4_1 142 #define VNCR_EL2 S3_4_C2_C2_0 143 #define PMSCR_EL2 S3_4_C9_C9_0 144 #define TFSR_EL2 S3_4_C5_C6_0 145 #define CONTEXTIDR_EL2 S3_4_C13_C0_1 146 #define TTBR1_EL2 S3_4_C2_C0_1 147 148 /******************************************************************************* 149 * Generic timer memory mapped registers & offsets 150 ******************************************************************************/ 151 #define CNTCR_OFF U(0x000) 152 #define CNTCV_OFF U(0x008) 153 #define CNTFID_OFF U(0x020) 154 155 #define CNTCR_EN (U(1) << 0) 156 #define CNTCR_HDBG (U(1) << 1) 157 #define CNTCR_FCREQ(x) ((x) << 8) 158 159 /******************************************************************************* 160 * System register bit definitions 161 ******************************************************************************/ 162 /* CLIDR definitions */ 163 #define LOUIS_SHIFT U(21) 164 #define LOC_SHIFT U(24) 165 #define CTYPE_SHIFT(n) U(3 * (n - 1)) 166 #define CLIDR_FIELD_WIDTH U(3) 167 168 /* CSSELR definitions */ 169 #define LEVEL_SHIFT U(1) 170 171 /* Data cache set/way op type defines */ 172 #define DCISW U(0x0) 173 #define DCCISW U(0x1) 174 #if ERRATA_A53_827319 175 #define DCCSW DCCISW 176 #else 177 #define DCCSW U(0x2) 178 #endif 179 180 #define ID_REG_FIELD_MASK ULL(0xf) 181 182 /* ID_AA64PFR0_EL1 definitions */ 183 #define ID_AA64PFR0_EL0_SHIFT U(0) 184 #define ID_AA64PFR0_EL1_SHIFT U(4) 185 #define ID_AA64PFR0_EL2_SHIFT U(8) 186 #define ID_AA64PFR0_EL3_SHIFT U(12) 187 188 #define ID_AA64PFR0_AMU_SHIFT U(44) 189 #define ID_AA64PFR0_AMU_MASK ULL(0xf) 190 #define ID_AA64PFR0_AMU_V1 ULL(0x1) 191 #define ID_AA64PFR0_AMU_V1P1 U(0x2) 192 193 #define ID_AA64PFR0_ELX_MASK ULL(0xf) 194 195 #define ID_AA64PFR0_GIC_SHIFT U(24) 196 #define ID_AA64PFR0_GIC_WIDTH U(4) 197 #define ID_AA64PFR0_GIC_MASK ULL(0xf) 198 199 #define ID_AA64PFR0_SVE_SHIFT U(32) 200 #define ID_AA64PFR0_SVE_MASK ULL(0xf) 201 #define ID_AA64PFR0_SVE_LENGTH U(4) 202 #define SVE_IMPLEMENTED ULL(0x1) 203 204 #define ID_AA64PFR0_SEL2_SHIFT U(36) 205 #define ID_AA64PFR0_SEL2_MASK ULL(0xf) 206 207 #define ID_AA64PFR0_MPAM_SHIFT U(40) 208 #define ID_AA64PFR0_MPAM_MASK ULL(0xf) 209 210 #define ID_AA64PFR0_DIT_SHIFT U(48) 211 #define ID_AA64PFR0_DIT_MASK ULL(0xf) 212 #define ID_AA64PFR0_DIT_LENGTH U(4) 213 #define DIT_IMPLEMENTED ULL(1) 214 215 #define ID_AA64PFR0_CSV2_SHIFT U(56) 216 #define ID_AA64PFR0_CSV2_MASK ULL(0xf) 217 #define ID_AA64PFR0_CSV2_LENGTH U(4) 218 #define CSV2_2_IMPLEMENTED ULL(0x2) 219 #define CSV2_3_IMPLEMENTED ULL(0x3) 220 221 #define ID_AA64PFR0_FEAT_RME_SHIFT U(52) 222 #define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf) 223 #define ID_AA64PFR0_FEAT_RME_LENGTH U(4) 224 #define RME_NOT_IMPLEMENTED ULL(0) 225 226 #define ID_AA64PFR0_RAS_SHIFT U(28) 227 #define ID_AA64PFR0_RAS_MASK ULL(0xf) 228 #define ID_AA64PFR0_RAS_LENGTH U(4) 229 230 /* Exception level handling */ 231 #define EL_IMPL_NONE ULL(0) 232 #define EL_IMPL_A64ONLY ULL(1) 233 #define EL_IMPL_A64_A32 ULL(2) 234 235 /* ID_AA64DFR0_EL1.DebugVer definitions */ 236 #define ID_AA64DFR0_DEBUGVER_SHIFT U(0) 237 #define ID_AA64DFR0_DEBUGVER_MASK ULL(0xf) 238 #define DEBUGVER_V8P9_IMPLEMENTED ULL(0xb) 239 240 /* ID_AA64DFR0_EL1.TraceVer definitions */ 241 #define ID_AA64DFR0_TRACEVER_SHIFT U(4) 242 #define ID_AA64DFR0_TRACEVER_MASK ULL(0xf) 243 #define ID_AA64DFR0_TRACEVER_LENGTH U(4) 244 245 #define ID_AA64DFR0_TRACEFILT_SHIFT U(40) 246 #define ID_AA64DFR0_TRACEFILT_MASK U(0xf) 247 #define ID_AA64DFR0_TRACEFILT_LENGTH U(4) 248 #define TRACEFILT_IMPLEMENTED ULL(1) 249 250 #define ID_AA64DFR0_PMUVER_LENGTH U(4) 251 #define ID_AA64DFR0_PMUVER_SHIFT U(8) 252 #define ID_AA64DFR0_PMUVER_MASK U(0xf) 253 #define ID_AA64DFR0_PMUVER_PMUV3 U(1) 254 #define ID_AA64DFR0_PMUVER_PMUV3P8 U(8) 255 #define ID_AA64DFR0_PMUVER_IMP_DEF U(0xf) 256 257 /* ID_AA64DFR0_EL1.SEBEP definitions */ 258 #define ID_AA64DFR0_SEBEP_SHIFT U(24) 259 #define ID_AA64DFR0_SEBEP_MASK ULL(0xf) 260 #define SEBEP_IMPLEMENTED ULL(1) 261 262 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ 263 #define ID_AA64DFR0_PMS_SHIFT U(32) 264 #define ID_AA64DFR0_PMS_MASK ULL(0xf) 265 #define SPE_IMPLEMENTED ULL(0x1) 266 #define SPE_NOT_IMPLEMENTED ULL(0x0) 267 268 /* ID_AA64DFR0_EL1.TraceBuffer definitions */ 269 #define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44) 270 #define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf) 271 #define TRACEBUFFER_IMPLEMENTED ULL(1) 272 273 /* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */ 274 #define ID_AA64DFR0_MTPMU_SHIFT U(48) 275 #define ID_AA64DFR0_MTPMU_MASK ULL(0xf) 276 #define MTPMU_IMPLEMENTED ULL(1) 277 #define MTPMU_NOT_IMPLEMENTED ULL(15) 278 279 /* ID_AA64DFR0_EL1.BRBE definitions */ 280 #define ID_AA64DFR0_BRBE_SHIFT U(52) 281 #define ID_AA64DFR0_BRBE_MASK ULL(0xf) 282 #define BRBE_IMPLEMENTED ULL(1) 283 284 /* ID_AA64DFR1_EL1 definitions */ 285 #define ID_AA64DFR1_EBEP_SHIFT U(48) 286 #define ID_AA64DFR1_EBEP_MASK ULL(0xf) 287 #define EBEP_IMPLEMENTED ULL(1) 288 289 /* ID_AA64ISAR0_EL1 definitions */ 290 #define ID_AA64ISAR0_RNDR_SHIFT U(60) 291 #define ID_AA64ISAR0_RNDR_MASK ULL(0xf) 292 293 /* ID_AA64ISAR1_EL1 definitions */ 294 #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 295 296 #define ID_AA64ISAR1_LS64_SHIFT U(60) 297 #define ID_AA64ISAR1_LS64_MASK ULL(0xf) 298 #define LS64_ACCDATA_IMPLEMENTED ULL(0x3) 299 #define LS64_V_IMPLEMENTED ULL(0x2) 300 #define LS64_IMPLEMENTED ULL(0x1) 301 #define LS64_NOT_IMPLEMENTED ULL(0x0) 302 303 #define ID_AA64ISAR1_SB_SHIFT U(36) 304 #define ID_AA64ISAR1_SB_MASK ULL(0xf) 305 #define SB_IMPLEMENTED ULL(0x1) 306 #define SB_NOT_IMPLEMENTED ULL(0x0) 307 308 #define ID_AA64ISAR1_GPI_SHIFT U(28) 309 #define ID_AA64ISAR1_GPI_MASK ULL(0xf) 310 #define ID_AA64ISAR1_GPA_SHIFT U(24) 311 #define ID_AA64ISAR1_GPA_MASK ULL(0xf) 312 313 #define ID_AA64ISAR1_API_SHIFT U(8) 314 #define ID_AA64ISAR1_API_MASK ULL(0xf) 315 #define ID_AA64ISAR1_APA_SHIFT U(4) 316 #define ID_AA64ISAR1_APA_MASK ULL(0xf) 317 318 /* ID_AA64ISAR2_EL1 definitions */ 319 #define ID_AA64ISAR2_EL1 S3_0_C0_C6_2 320 321 /* ID_AA64PFR2_EL1 definitions */ 322 #define ID_AA64PFR2_EL1 S3_0_C0_C4_2 323 324 #define ID_AA64ISAR2_GPA3_SHIFT U(8) 325 #define ID_AA64ISAR2_GPA3_MASK ULL(0xf) 326 327 #define ID_AA64ISAR2_APA3_SHIFT U(12) 328 #define ID_AA64ISAR2_APA3_MASK ULL(0xf) 329 330 /* ID_AA64MMFR0_EL1 definitions */ 331 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) 332 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) 333 334 #define PARANGE_0000 U(32) 335 #define PARANGE_0001 U(36) 336 #define PARANGE_0010 U(40) 337 #define PARANGE_0011 U(42) 338 #define PARANGE_0100 U(44) 339 #define PARANGE_0101 U(48) 340 #define PARANGE_0110 U(52) 341 #define PARANGE_0111 U(56) 342 343 #define ID_AA64MMFR0_EL1_ECV_SHIFT U(60) 344 #define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf) 345 #define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2) 346 #define ECV_IMPLEMENTED ULL(0x1) 347 348 #define ID_AA64MMFR0_EL1_FGT_SHIFT U(56) 349 #define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf) 350 #define FGT2_IMPLEMENTED ULL(0x2) 351 #define FGT_IMPLEMENTED ULL(0x1) 352 #define FGT_NOT_IMPLEMENTED ULL(0x0) 353 354 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) 355 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) 356 357 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) 358 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) 359 360 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) 361 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) 362 #define TGRAN16_IMPLEMENTED ULL(0x1) 363 364 /* ID_AA64MMFR1_EL1 definitions */ 365 #define ID_AA64MMFR1_EL1_TWED_SHIFT U(32) 366 #define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf) 367 #define TWED_IMPLEMENTED ULL(0x1) 368 369 #define ID_AA64MMFR1_EL1_PAN_SHIFT U(20) 370 #define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf) 371 #define PAN_IMPLEMENTED ULL(0x1) 372 #define PAN2_IMPLEMENTED ULL(0x2) 373 #define PAN3_IMPLEMENTED ULL(0x3) 374 375 #define ID_AA64MMFR1_EL1_VHE_SHIFT U(8) 376 #define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf) 377 378 #define ID_AA64MMFR1_EL1_HCX_SHIFT U(40) 379 #define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf) 380 #define HCX_IMPLEMENTED ULL(0x1) 381 382 /* ID_AA64MMFR2_EL1 definitions */ 383 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 384 385 #define ID_AA64MMFR2_EL1_ST_SHIFT U(28) 386 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) 387 388 #define ID_AA64MMFR2_EL1_CCIDX_SHIFT U(20) 389 #define ID_AA64MMFR2_EL1_CCIDX_MASK ULL(0xf) 390 #define ID_AA64MMFR2_EL1_CCIDX_LENGTH U(4) 391 392 #define ID_AA64MMFR2_EL1_UAO_SHIFT U(4) 393 #define ID_AA64MMFR2_EL1_UAO_MASK ULL(0xf) 394 395 #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) 396 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) 397 398 #define ID_AA64MMFR2_EL1_NV_SHIFT U(24) 399 #define ID_AA64MMFR2_EL1_NV_MASK ULL(0xf) 400 #define NV2_IMPLEMENTED ULL(0x2) 401 402 /* ID_AA64MMFR3_EL1 definitions */ 403 #define ID_AA64MMFR3_EL1 S3_0_C0_C7_3 404 405 #define ID_AA64MMFR3_EL1_D128_SHIFT U(32) 406 #define ID_AA64MMFR3_EL1_D128_MASK ULL(0xf) 407 #define D128_IMPLEMENTED ULL(0x1) 408 409 #define ID_AA64MMFR3_EL1_S2POE_SHIFT U(20) 410 #define ID_AA64MMFR3_EL1_S2POE_MASK ULL(0xf) 411 412 #define ID_AA64MMFR3_EL1_S1POE_SHIFT U(16) 413 #define ID_AA64MMFR3_EL1_S1POE_MASK ULL(0xf) 414 415 #define ID_AA64MMFR3_EL1_S2PIE_SHIFT U(12) 416 #define ID_AA64MMFR3_EL1_S2PIE_MASK ULL(0xf) 417 418 #define ID_AA64MMFR3_EL1_S1PIE_SHIFT U(8) 419 #define ID_AA64MMFR3_EL1_S1PIE_MASK ULL(0xf) 420 421 #define ID_AA64MMFR3_EL1_SCTLR2_SHIFT U(4) 422 #define ID_AA64MMFR3_EL1_SCTLR2_MASK ULL(0xf) 423 #define SCTLR2_IMPLEMENTED ULL(1) 424 425 #define ID_AA64MMFR3_EL1_TCRX_SHIFT U(0) 426 #define ID_AA64MMFR3_EL1_TCRX_MASK ULL(0xf) 427 428 /* ID_AA64PFR1_EL1 definitions */ 429 430 #define ID_AA64PFR1_EL1_BT_SHIFT U(0) 431 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) 432 #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ 433 434 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) 435 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) 436 #define SSBS_NOT_IMPLEMENTED ULL(0) /* No architectural SSBS support */ 437 438 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) 439 #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) 440 441 #define ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT U(28) 442 #define ID_AA64PFR1_EL1_RNDR_TRAP_MASK U(0xf) 443 444 #define ID_AA64PFR1_EL1_NMI_SHIFT U(36) 445 #define ID_AA64PFR1_EL1_NMI_MASK ULL(0xf) 446 #define NMI_IMPLEMENTED ULL(1) 447 448 #define ID_AA64PFR1_EL1_GCS_SHIFT U(44) 449 #define ID_AA64PFR1_EL1_GCS_MASK ULL(0xf) 450 #define GCS_IMPLEMENTED ULL(1) 451 452 #define ID_AA64PFR1_EL1_THE_SHIFT U(48) 453 #define ID_AA64PFR1_EL1_THE_MASK ULL(0xf) 454 #define THE_IMPLEMENTED ULL(1) 455 456 #define RNG_TRAP_IMPLEMENTED ULL(0x1) 457 458 /* ID_AA64PFR2_EL1 definitions */ 459 #define ID_AA64PFR2_EL1_MTEPERM_SHIFT U(0) 460 #define ID_AA64PFR2_EL1_MTEPERM_MASK ULL(0xf) 461 462 #define ID_AA64PFR2_EL1_MTESTOREONLY_SHIFT U(4) 463 #define ID_AA64PFR2_EL1_MTESTOREONLY_MASK ULL(0xf) 464 465 #define ID_AA64PFR2_EL1_MTEFAR_SHIFT U(8) 466 #define ID_AA64PFR2_EL1_MTEFAR_MASK ULL(0xf) 467 468 #define VDISR_EL2 S3_4_C12_C1_1 469 #define VSESR_EL2 S3_4_C5_C2_3 470 471 /* Memory Tagging Extension is not implemented */ 472 #define MTE_UNIMPLEMENTED U(0) 473 /* FEAT_MTE: MTE instructions accessible at EL0 are implemented */ 474 #define MTE_IMPLEMENTED_EL0 U(1) 475 /* FEAT_MTE2: Full MTE is implemented */ 476 #define MTE_IMPLEMENTED_ELX U(2) 477 /* 478 * FEAT_MTE3: MTE is implemented with support for 479 * asymmetric Tag Check Fault handling 480 */ 481 #define MTE_IMPLEMENTED_ASY U(3) 482 483 #define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16) 484 #define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf) 485 486 #define ID_AA64PFR1_EL1_SME_SHIFT U(24) 487 #define ID_AA64PFR1_EL1_SME_MASK ULL(0xf) 488 #define ID_AA64PFR1_EL1_SME_WIDTH U(4) 489 #define SME_IMPLEMENTED ULL(0x1) 490 #define SME2_IMPLEMENTED ULL(0x2) 491 #define SME_NOT_IMPLEMENTED ULL(0x0) 492 493 /* ID_PFR1_EL1 definitions */ 494 #define ID_PFR1_VIRTEXT_SHIFT U(12) 495 #define ID_PFR1_VIRTEXT_MASK U(0xf) 496 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 497 & ID_PFR1_VIRTEXT_MASK) 498 499 /* SCTLR definitions */ 500 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 501 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 502 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 503 504 #define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \ 505 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11)) 506 507 #define SCTLR_AARCH32_EL1_RES1 \ 508 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ 509 (U(1) << 4) | (U(1) << 3)) 510 511 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 512 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 513 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 514 515 #define SCTLR_M_BIT (ULL(1) << 0) 516 #define SCTLR_A_BIT (ULL(1) << 1) 517 #define SCTLR_C_BIT (ULL(1) << 2) 518 #define SCTLR_SA_BIT (ULL(1) << 3) 519 #define SCTLR_SA0_BIT (ULL(1) << 4) 520 #define SCTLR_CP15BEN_BIT (ULL(1) << 5) 521 #define SCTLR_nAA_BIT (ULL(1) << 6) 522 #define SCTLR_ITD_BIT (ULL(1) << 7) 523 #define SCTLR_SED_BIT (ULL(1) << 8) 524 #define SCTLR_UMA_BIT (ULL(1) << 9) 525 #define SCTLR_EnRCTX_BIT (ULL(1) << 10) 526 #define SCTLR_EOS_BIT (ULL(1) << 11) 527 #define SCTLR_I_BIT (ULL(1) << 12) 528 #define SCTLR_EnDB_BIT (ULL(1) << 13) 529 #define SCTLR_DZE_BIT (ULL(1) << 14) 530 #define SCTLR_UCT_BIT (ULL(1) << 15) 531 #define SCTLR_NTWI_BIT (ULL(1) << 16) 532 #define SCTLR_NTWE_BIT (ULL(1) << 18) 533 #define SCTLR_WXN_BIT (ULL(1) << 19) 534 #define SCTLR_TSCXT_BIT (ULL(1) << 20) 535 #define SCTLR_IESB_BIT (ULL(1) << 21) 536 #define SCTLR_EIS_BIT (ULL(1) << 22) 537 #define SCTLR_SPAN_BIT (ULL(1) << 23) 538 #define SCTLR_E0E_BIT (ULL(1) << 24) 539 #define SCTLR_EE_BIT (ULL(1) << 25) 540 #define SCTLR_UCI_BIT (ULL(1) << 26) 541 #define SCTLR_EnDA_BIT (ULL(1) << 27) 542 #define SCTLR_nTLSMD_BIT (ULL(1) << 28) 543 #define SCTLR_LSMAOE_BIT (ULL(1) << 29) 544 #define SCTLR_EnIB_BIT (ULL(1) << 30) 545 #define SCTLR_EnIA_BIT (ULL(1) << 31) 546 #define SCTLR_BT0_BIT (ULL(1) << 35) 547 #define SCTLR_BT1_BIT (ULL(1) << 36) 548 #define SCTLR_BT_BIT (ULL(1) << 36) 549 #define SCTLR_ITFSB_BIT (ULL(1) << 37) 550 #define SCTLR_TCF0_SHIFT U(38) 551 #define SCTLR_TCF0_MASK ULL(3) 552 #define SCTLR_ENTP2_BIT (ULL(1) << 60) 553 #define SCTLR_SPINTMASK_BIT (ULL(1) << 62) 554 555 /* Tag Check Faults in EL0 have no effect on the PE */ 556 #define SCTLR_TCF0_NO_EFFECT U(0) 557 /* Tag Check Faults in EL0 cause a synchronous exception */ 558 #define SCTLR_TCF0_SYNC U(1) 559 /* Tag Check Faults in EL0 are asynchronously accumulated */ 560 #define SCTLR_TCF0_ASYNC U(2) 561 /* 562 * Tag Check Faults in EL0 cause a synchronous exception on reads, 563 * and are asynchronously accumulated on writes 564 */ 565 #define SCTLR_TCF0_SYNCR_ASYNCW U(3) 566 567 #define SCTLR_TCF_SHIFT U(40) 568 #define SCTLR_TCF_MASK ULL(3) 569 570 /* Tag Check Faults in EL1 have no effect on the PE */ 571 #define SCTLR_TCF_NO_EFFECT U(0) 572 /* Tag Check Faults in EL1 cause a synchronous exception */ 573 #define SCTLR_TCF_SYNC U(1) 574 /* Tag Check Faults in EL1 are asynchronously accumulated */ 575 #define SCTLR_TCF_ASYNC U(2) 576 /* 577 * Tag Check Faults in EL1 cause a synchronous exception on reads, 578 * and are asynchronously accumulated on writes 579 */ 580 #define SCTLR_TCF_SYNCR_ASYNCW U(3) 581 582 #define SCTLR_ATA0_BIT (ULL(1) << 42) 583 #define SCTLR_ATA_BIT (ULL(1) << 43) 584 #define SCTLR_DSSBS_SHIFT U(44) 585 #define SCTLR_DSSBS_BIT (ULL(1) << SCTLR_DSSBS_SHIFT) 586 #define SCTLR_TWEDEn_BIT (ULL(1) << 45) 587 #define SCTLR_TWEDEL_SHIFT U(46) 588 #define SCTLR_TWEDEL_MASK ULL(0xf) 589 #define SCTLR_EnASR_BIT (ULL(1) << 54) 590 #define SCTLR_EnAS0_BIT (ULL(1) << 55) 591 #define SCTLR_EnALS_BIT (ULL(1) << 56) 592 #define SCTLR_EPAN_BIT (ULL(1) << 57) 593 #define SCTLR_RESET_VAL SCTLR_EL3_RES1 594 595 /* CPACR_EL1 definitions */ 596 #define CPACR_EL1_FPEN(x) ((x) << 20) 597 #define CPACR_EL1_FP_TRAP_EL0 UL(0x1) 598 #define CPACR_EL1_FP_TRAP_ALL UL(0x2) 599 #define CPACR_EL1_FP_TRAP_NONE UL(0x3) 600 #define CPACR_EL1_SMEN_SHIFT U(24) 601 #define CPACR_EL1_SMEN_MASK ULL(0x3) 602 603 /* SCR definitions */ 604 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) 605 #define SCR_NSE_SHIFT U(62) 606 #define SCR_FGTEN2_BIT (UL(1) << 59) 607 #define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT) 608 #define SCR_GPF_BIT (UL(1) << 48) 609 #define SCR_D128En_BIT (UL(1) << 47) 610 #define SCR_TWEDEL_SHIFT U(30) 611 #define SCR_TWEDEL_MASK ULL(0xf) 612 #define SCR_PIEN_BIT (UL(1) << 45) 613 #define SCR_SCTLR2En_BIT (UL(1) << 44) 614 #define SCR_TCR2EN_BIT (UL(1) << 43) 615 #define SCR_RCWMASKEn_BIT (UL(1) << 42) 616 #define SCR_ENTP2_SHIFT U(41) 617 #define SCR_ENTP2_BIT (UL(1) << SCR_ENTP2_SHIFT) 618 #define SCR_TRNDR_BIT (UL(1) << 40) 619 #define SCR_GCSEn_BIT (UL(1) << 39) 620 #define SCR_HXEn_BIT (UL(1) << 38) 621 #define SCR_ADEn_BIT (UL(1) << 37) 622 #define SCR_EnAS0_BIT (UL(1) << 36) 623 #define SCR_AMVOFFEN_SHIFT U(35) 624 #define SCR_AMVOFFEN_BIT (UL(1) << SCR_AMVOFFEN_SHIFT) 625 #define SCR_TWEDEn_BIT (UL(1) << 29) 626 #define SCR_ECVEN_BIT (UL(1) << 28) 627 #define SCR_FGTEN_BIT (UL(1) << 27) 628 #define SCR_ATA_BIT (UL(1) << 26) 629 #define SCR_EnSCXT_BIT (UL(1) << 25) 630 #define SCR_FIEN_BIT (UL(1) << 21) 631 #define SCR_EEL2_BIT (UL(1) << 18) 632 #define SCR_API_BIT (UL(1) << 17) 633 #define SCR_APK_BIT (UL(1) << 16) 634 #define SCR_TERR_BIT (UL(1) << 15) 635 #define SCR_TWE_BIT (UL(1) << 13) 636 #define SCR_TWI_BIT (UL(1) << 12) 637 #define SCR_ST_BIT (UL(1) << 11) 638 #define SCR_RW_BIT (UL(1) << 10) 639 #define SCR_SIF_BIT (UL(1) << 9) 640 #define SCR_HCE_BIT (UL(1) << 8) 641 #define SCR_SMD_BIT (UL(1) << 7) 642 #define SCR_EA_BIT (UL(1) << 3) 643 #define SCR_FIQ_BIT (UL(1) << 2) 644 #define SCR_IRQ_BIT (UL(1) << 1) 645 #define SCR_NS_BIT (UL(1) << 0) 646 #define SCR_VALID_BIT_MASK U(0x24000002F8F) 647 #define SCR_RESET_VAL SCR_RES1_BITS 648 649 /* MDCR_EL3 definitions */ 650 #define MDCR_EBWE_BIT (ULL(1) << 43) 651 #define MDCR_E3BREC (ULL(1) << 38) 652 #define MDCR_E3BREW (ULL(1) << 37) 653 #define MDCR_EnPMSN_BIT (ULL(1) << 36) 654 #define MDCR_MPMX_BIT (ULL(1) << 35) 655 #define MDCR_MCCD_BIT (ULL(1) << 34) 656 #define MDCR_SBRBE_SHIFT U(32) 657 #define MDCR_SBRBE_MASK ULL(0x3) 658 #define MDCR_NSTB(x) ((x) << 24) 659 #define MDCR_NSTB_EL1 ULL(0x3) 660 #define MDCR_NSTBE_BIT (ULL(1) << 26) 661 #define MDCR_MTPME_BIT (ULL(1) << 28) 662 #define MDCR_TDCC_BIT (ULL(1) << 27) 663 #define MDCR_SCCD_BIT (ULL(1) << 23) 664 #define MDCR_EPMAD_BIT (ULL(1) << 21) 665 #define MDCR_EDAD_BIT (ULL(1) << 20) 666 #define MDCR_TTRF_BIT (ULL(1) << 19) 667 #define MDCR_STE_BIT (ULL(1) << 18) 668 #define MDCR_SPME_BIT (ULL(1) << 17) 669 #define MDCR_SDD_BIT (ULL(1) << 16) 670 #define MDCR_SPD32(x) ((x) << 14) 671 #define MDCR_SPD32_LEGACY ULL(0x0) 672 #define MDCR_SPD32_DISABLE ULL(0x2) 673 #define MDCR_SPD32_ENABLE ULL(0x3) 674 #define MDCR_NSPB(x) ((x) << 12) 675 #define MDCR_NSPB_EL1 ULL(0x3) 676 #define MDCR_NSPBE_BIT (ULL(1) << 11) 677 #define MDCR_TDOSA_BIT (ULL(1) << 10) 678 #define MDCR_TDA_BIT (ULL(1) << 9) 679 #define MDCR_TPM_BIT (ULL(1) << 6) 680 #define MDCR_EL3_RESET_VAL MDCR_MTPME_BIT 681 682 /* MDCR_EL2 definitions */ 683 #define MDCR_EL2_MTPME (U(1) << 28) 684 #define MDCR_EL2_HLP_BIT (U(1) << 26) 685 #define MDCR_EL2_E2TB(x) ((x) << 24) 686 #define MDCR_EL2_E2TB_EL1 U(0x3) 687 #define MDCR_EL2_HCCD_BIT (U(1) << 23) 688 #define MDCR_EL2_TTRF (U(1) << 19) 689 #define MDCR_EL2_HPMD_BIT (U(1) << 17) 690 #define MDCR_EL2_TPMS (U(1) << 14) 691 #define MDCR_EL2_E2PB(x) ((x) << 12) 692 #define MDCR_EL2_E2PB_EL1 U(0x3) 693 #define MDCR_EL2_TDRA_BIT (U(1) << 11) 694 #define MDCR_EL2_TDOSA_BIT (U(1) << 10) 695 #define MDCR_EL2_TDA_BIT (U(1) << 9) 696 #define MDCR_EL2_TDE_BIT (U(1) << 8) 697 #define MDCR_EL2_HPME_BIT (U(1) << 7) 698 #define MDCR_EL2_TPM_BIT (U(1) << 6) 699 #define MDCR_EL2_TPMCR_BIT (U(1) << 5) 700 #define MDCR_EL2_HPMN_MASK U(0x1f) 701 #define MDCR_EL2_RESET_VAL U(0x0) 702 703 /* HSTR_EL2 definitions */ 704 #define HSTR_EL2_RESET_VAL U(0x0) 705 #define HSTR_EL2_T_MASK U(0xff) 706 707 /* CNTHP_CTL_EL2 definitions */ 708 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) 709 #define CNTHP_CTL_RESET_VAL U(0x0) 710 711 /* VTTBR_EL2 definitions */ 712 #define VTTBR_RESET_VAL ULL(0x0) 713 #define VTTBR_VMID_MASK ULL(0xff) 714 #define VTTBR_VMID_SHIFT U(48) 715 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 716 #define VTTBR_BADDR_SHIFT U(0) 717 718 /* HCR definitions */ 719 #define HCR_RESET_VAL ULL(0x0) 720 #define HCR_AMVOFFEN_SHIFT U(51) 721 #define HCR_AMVOFFEN_BIT (ULL(1) << HCR_AMVOFFEN_SHIFT) 722 #define HCR_TEA_BIT (ULL(1) << 47) 723 #define HCR_API_BIT (ULL(1) << 41) 724 #define HCR_APK_BIT (ULL(1) << 40) 725 #define HCR_E2H_BIT (ULL(1) << 34) 726 #define HCR_HCD_BIT (ULL(1) << 29) 727 #define HCR_TGE_BIT (ULL(1) << 27) 728 #define HCR_RW_SHIFT U(31) 729 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) 730 #define HCR_TWE_BIT (ULL(1) << 14) 731 #define HCR_TWI_BIT (ULL(1) << 13) 732 #define HCR_AMO_BIT (ULL(1) << 5) 733 #define HCR_IMO_BIT (ULL(1) << 4) 734 #define HCR_FMO_BIT (ULL(1) << 3) 735 736 /* ISR definitions */ 737 #define ISR_A_SHIFT U(8) 738 #define ISR_I_SHIFT U(7) 739 #define ISR_F_SHIFT U(6) 740 741 /* CNTHCTL_EL2 definitions */ 742 #define CNTHCTL_RESET_VAL U(0x0) 743 #define EVNTEN_BIT (U(1) << 2) 744 #define EL1PCEN_BIT (U(1) << 1) 745 #define EL1PCTEN_BIT (U(1) << 0) 746 747 /* CNTKCTL_EL1 definitions */ 748 #define EL0PTEN_BIT (U(1) << 9) 749 #define EL0VTEN_BIT (U(1) << 8) 750 #define EL0PCTEN_BIT (U(1) << 0) 751 #define EL0VCTEN_BIT (U(1) << 1) 752 #define EVNTEN_BIT (U(1) << 2) 753 #define EVNTDIR_BIT (U(1) << 3) 754 #define EVNTI_SHIFT U(4) 755 #define EVNTI_MASK U(0xf) 756 757 /* CPTR_EL3 definitions */ 758 #define TCPAC_BIT (U(1) << 31) 759 #define TAM_SHIFT U(30) 760 #define TAM_BIT (U(1) << TAM_SHIFT) 761 #define TTA_BIT (U(1) << 20) 762 #define ESM_BIT (U(1) << 12) 763 #define TFP_BIT (U(1) << 10) 764 #define CPTR_EZ_BIT (U(1) << 8) 765 #define CPTR_EL3_RESET_VAL ((TCPAC_BIT | TAM_BIT | TTA_BIT | TFP_BIT) & \ 766 ~(CPTR_EZ_BIT | ESM_BIT)) 767 768 /* CPTR_EL2 definitions */ 769 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) 770 #define CPTR_EL2_TCPAC_BIT (U(1) << 31) 771 #define CPTR_EL2_TAM_SHIFT U(30) 772 #define CPTR_EL2_TAM_BIT (U(1) << CPTR_EL2_TAM_SHIFT) 773 #define CPTR_EL2_SMEN_MASK ULL(0x3) 774 #define CPTR_EL2_SMEN_SHIFT U(24) 775 #define CPTR_EL2_TTA_BIT (U(1) << 20) 776 #define CPTR_EL2_TSM_BIT (U(1) << 12) 777 #define CPTR_EL2_TFP_BIT (U(1) << 10) 778 #define CPTR_EL2_TZ_BIT (U(1) << 8) 779 #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 780 781 /* VTCR_EL2 definitions */ 782 #define VTCR_RESET_VAL U(0x0) 783 #define VTCR_EL2_MSA (U(1) << 31) 784 785 /* CPSR/SPSR definitions */ 786 #define DAIF_FIQ_BIT (U(1) << 0) 787 #define DAIF_IRQ_BIT (U(1) << 1) 788 #define DAIF_ABT_BIT (U(1) << 2) 789 #define DAIF_DBG_BIT (U(1) << 3) 790 #define SPSR_V_BIT (U(1) << 28) 791 #define SPSR_C_BIT (U(1) << 29) 792 #define SPSR_Z_BIT (U(1) << 30) 793 #define SPSR_N_BIT (U(1) << 31) 794 #define SPSR_DAIF_SHIFT U(6) 795 #define SPSR_DAIF_MASK U(0xf) 796 797 #define SPSR_AIF_SHIFT U(6) 798 #define SPSR_AIF_MASK U(0x7) 799 800 #define SPSR_E_SHIFT U(9) 801 #define SPSR_E_MASK U(0x1) 802 #define SPSR_E_LITTLE U(0x0) 803 #define SPSR_E_BIG U(0x1) 804 805 #define SPSR_T_SHIFT U(5) 806 #define SPSR_T_MASK U(0x1) 807 #define SPSR_T_ARM U(0x0) 808 #define SPSR_T_THUMB U(0x1) 809 810 #define SPSR_M_SHIFT U(4) 811 #define SPSR_M_MASK U(0x1) 812 #define SPSR_M_AARCH64 U(0x0) 813 #define SPSR_M_AARCH32 U(0x1) 814 #define SPSR_M_EL1H U(0x5) 815 #define SPSR_M_EL2H U(0x9) 816 817 #define SPSR_EL_SHIFT U(2) 818 #define SPSR_EL_WIDTH U(2) 819 820 #define SPSR_BTYPE_SHIFT_AARCH64 U(10) 821 #define SPSR_BTYPE_MASK_AARCH64 U(0x3) 822 #define SPSR_SSBS_SHIFT_AARCH64 U(12) 823 #define SPSR_SSBS_BIT_AARCH64 (ULL(1) << SPSR_SSBS_SHIFT_AARCH64) 824 #define SPSR_SSBS_SHIFT_AARCH32 U(23) 825 #define SPSR_SSBS_BIT_AARCH32 (ULL(1) << SPSR_SSBS_SHIFT_AARCH32) 826 #define SPSR_ALLINT_BIT_AARCH64 BIT_64(13) 827 #define SPSR_IL_BIT BIT_64(20) 828 #define SPSR_SS_BIT BIT_64(21) 829 #define SPSR_PAN_BIT BIT_64(22) 830 #define SPSR_UAO_BIT_AARCH64 BIT_64(23) 831 #define SPSR_DIT_BIT BIT(24) 832 #define SPSR_TCO_BIT_AARCH64 BIT_64(25) 833 #define SPSR_PM_BIT_AARCH64 BIT_64(32) 834 #define SPSR_PPEND_BIT BIT(33) 835 #define SPSR_EXLOCK_BIT_AARCH64 BIT_64(34) 836 #define SPSR_NZCV (SPSR_V_BIT | SPSR_C_BIT | SPSR_Z_BIT | SPSR_N_BIT) 837 838 #define DISABLE_ALL_EXCEPTIONS \ 839 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 840 #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) 841 842 /* 843 * RMR_EL3 definitions 844 */ 845 #define RMR_EL3_RR_BIT (U(1) << 1) 846 #define RMR_EL3_AA64_BIT (U(1) << 0) 847 848 /* 849 * HI-VECTOR address for AArch32 state 850 */ 851 #define HI_VECTOR_BASE U(0xFFFF0000) 852 853 /* 854 * TCR definitions 855 */ 856 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 857 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 858 #define TCR_EL1_IPS_SHIFT U(32) 859 #define TCR_EL2_PS_SHIFT U(16) 860 #define TCR_EL3_PS_SHIFT U(16) 861 862 #define TCR_TxSZ_MIN ULL(16) 863 #define TCR_TxSZ_MAX ULL(39) 864 #define TCR_TxSZ_MAX_TTST ULL(48) 865 866 #define TCR_T0SZ_SHIFT U(0) 867 #define TCR_T1SZ_SHIFT U(16) 868 869 /* (internal) physical address size bits in EL3/EL1 */ 870 #define TCR_PS_BITS_4GB ULL(0x0) 871 #define TCR_PS_BITS_64GB ULL(0x1) 872 #define TCR_PS_BITS_1TB ULL(0x2) 873 #define TCR_PS_BITS_4TB ULL(0x3) 874 #define TCR_PS_BITS_16TB ULL(0x4) 875 #define TCR_PS_BITS_256TB ULL(0x5) 876 877 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) 878 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) 879 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) 880 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) 881 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) 882 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) 883 884 #define TCR_RGN_INNER_NC (ULL(0x0) << 8) 885 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8) 886 #define TCR_RGN_INNER_WT (ULL(0x2) << 8) 887 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) 888 889 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10) 890 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) 891 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10) 892 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) 893 894 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) 895 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) 896 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) 897 898 #define TCR_RGN1_INNER_NC (ULL(0x0) << 24) 899 #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24) 900 #define TCR_RGN1_INNER_WT (ULL(0x2) << 24) 901 #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24) 902 903 #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26) 904 #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26) 905 #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26) 906 #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26) 907 908 #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28) 909 #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28) 910 #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28) 911 912 #define TCR_TG0_SHIFT U(14) 913 #define TCR_TG0_MASK ULL(3) 914 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) 915 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) 916 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) 917 918 #define TCR_TG1_SHIFT U(30) 919 #define TCR_TG1_MASK ULL(3) 920 #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT) 921 #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT) 922 #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT) 923 924 #define TCR_EPD0_BIT (ULL(1) << 7) 925 #define TCR_EPD1_BIT (ULL(1) << 23) 926 927 #define MODE_SP_SHIFT U(0x0) 928 #define MODE_SP_MASK U(0x1) 929 #define MODE_SP_EL0 U(0x0) 930 #define MODE_SP_ELX U(0x1) 931 932 #define MODE_RW_SHIFT U(0x4) 933 #define MODE_RW_MASK U(0x1) 934 #define MODE_RW_64 U(0x0) 935 #define MODE_RW_32 U(0x1) 936 937 #define MODE_EL_SHIFT U(0x2) 938 #define MODE_EL_MASK U(0x3) 939 #define MODE_EL_WIDTH U(0x2) 940 #define MODE_EL3 U(0x3) 941 #define MODE_EL2 U(0x2) 942 #define MODE_EL1 U(0x1) 943 #define MODE_EL0 U(0x0) 944 945 #define MODE32_SHIFT U(0) 946 #define MODE32_MASK U(0xf) 947 #define MODE32_usr U(0x0) 948 #define MODE32_fiq U(0x1) 949 #define MODE32_irq U(0x2) 950 #define MODE32_svc U(0x3) 951 #define MODE32_mon U(0x6) 952 #define MODE32_abt U(0x7) 953 #define MODE32_hyp U(0xa) 954 #define MODE32_und U(0xb) 955 #define MODE32_sys U(0xf) 956 957 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) 958 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 959 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) 960 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 961 962 #define SPSR_64(el, sp, daif) \ 963 (((MODE_RW_64 << MODE_RW_SHIFT) | \ 964 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ 965 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ 966 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \ 967 (~(SPSR_SSBS_BIT_AARCH64))) 968 969 #define SPSR_MODE32(mode, isa, endian, aif) \ 970 (((MODE_RW_32 << MODE_RW_SHIFT) | \ 971 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 972 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 973 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 974 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \ 975 (~(SPSR_SSBS_BIT_AARCH32))) 976 977 /* 978 * TTBR Definitions 979 */ 980 #define TTBR_CNP_BIT ULL(0x1) 981 982 /* 983 * CTR_EL0 definitions 984 */ 985 #define CTR_CWG_SHIFT U(24) 986 #define CTR_CWG_MASK U(0xf) 987 #define CTR_ERG_SHIFT U(20) 988 #define CTR_ERG_MASK U(0xf) 989 #define CTR_DMINLINE_SHIFT U(16) 990 #define CTR_DMINLINE_MASK U(0xf) 991 #define CTR_L1IP_SHIFT U(14) 992 #define CTR_L1IP_MASK U(0x3) 993 #define CTR_IMINLINE_SHIFT U(0) 994 #define CTR_IMINLINE_MASK U(0xf) 995 996 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 997 998 /* Physical timer control register bit fields shifts and masks */ 999 #define CNTP_CTL_ENABLE_SHIFT U(0) 1000 #define CNTP_CTL_IMASK_SHIFT U(1) 1001 #define CNTP_CTL_ISTATUS_SHIFT U(2) 1002 1003 #define CNTP_CTL_ENABLE_MASK U(1) 1004 #define CNTP_CTL_IMASK_MASK U(1) 1005 #define CNTP_CTL_ISTATUS_MASK U(1) 1006 1007 /* Physical timer control macros */ 1008 #define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT) 1009 #define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT) 1010 1011 /* Exception Syndrome register bits and bobs */ 1012 #define ESR_EC_SHIFT U(26) 1013 #define ESR_EC_MASK U(0x3f) 1014 #define ESR_EC_LENGTH U(6) 1015 #define ESR_ISS_SHIFT U(0) 1016 #define ESR_ISS_LENGTH U(25) 1017 #define ESR_IL_BIT (U(1) << 25) 1018 #define EC_UNKNOWN U(0x0) 1019 #define EC_WFE_WFI U(0x1) 1020 #define EC_AARCH32_CP15_MRC_MCR U(0x3) 1021 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) 1022 #define EC_AARCH32_CP14_MRC_MCR U(0x5) 1023 #define EC_AARCH32_CP14_LDC_STC U(0x6) 1024 #define EC_FP_SIMD U(0x7) 1025 #define EC_AARCH32_CP10_MRC U(0x8) 1026 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) 1027 #define EC_ILLEGAL U(0xe) 1028 #define EC_AARCH32_SVC U(0x11) 1029 #define EC_AARCH32_HVC U(0x12) 1030 #define EC_AARCH32_SMC U(0x13) 1031 #define EC_AARCH64_SVC U(0x15) 1032 #define EC_AARCH64_HVC U(0x16) 1033 #define EC_AARCH64_SMC U(0x17) 1034 #define EC_AARCH64_SYS U(0x18) 1035 #define EC_IMP_DEF_EL3 U(0x1f) 1036 #define EC_IABORT_LOWER_EL U(0x20) 1037 #define EC_IABORT_CUR_EL U(0x21) 1038 #define EC_PC_ALIGN U(0x22) 1039 #define EC_DABORT_LOWER_EL U(0x24) 1040 #define EC_DABORT_CUR_EL U(0x25) 1041 #define EC_SP_ALIGN U(0x26) 1042 #define EC_AARCH32_FP U(0x28) 1043 #define EC_AARCH64_FP U(0x2c) 1044 #define EC_SERROR U(0x2f) 1045 #define EC_BRK U(0x3c) 1046 1047 /* 1048 * External Abort bit in Instruction and Data Aborts synchronous exception 1049 * syndromes. 1050 */ 1051 #define ESR_ISS_EABORT_EA_BIT U(9) 1052 1053 #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) 1054 1055 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ 1056 #define RMR_RESET_REQUEST_SHIFT U(0x1) 1057 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) 1058 1059 /******************************************************************************* 1060 * Definitions of register offsets, fields and macros for CPU system 1061 * instructions. 1062 ******************************************************************************/ 1063 1064 #define TLBI_ADDR_SHIFT U(12) 1065 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) 1066 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 1067 1068 /******************************************************************************* 1069 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 1070 * system level implementation of the Generic Timer. 1071 ******************************************************************************/ 1072 #define CNTCTLBASE_CNTFRQ U(0x0) 1073 #define CNTNSAR U(0x4) 1074 #define CNTNSAR_NS_SHIFT(x) (x) 1075 1076 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 1077 #define CNTACR_RPCT_SHIFT U(0x0) 1078 #define CNTACR_RVCT_SHIFT U(0x1) 1079 #define CNTACR_RFRQ_SHIFT U(0x2) 1080 #define CNTACR_RVOFF_SHIFT U(0x3) 1081 #define CNTACR_RWVT_SHIFT U(0x4) 1082 #define CNTACR_RWPT_SHIFT U(0x5) 1083 1084 /******************************************************************************* 1085 * Definitions of register offsets and fields in the CNTBaseN Frame of the 1086 * system level implementation of the Generic Timer. 1087 ******************************************************************************/ 1088 /* Physical Count register. */ 1089 #define CNTPCT_LO U(0x0) 1090 /* Counter Frequency register. */ 1091 #define CNTBASEN_CNTFRQ U(0x10) 1092 /* Physical Timer CompareValue register. */ 1093 #define CNTP_CVAL_LO U(0x20) 1094 /* Physical Timer Control register. */ 1095 #define CNTP_CTL U(0x2c) 1096 1097 /* PMCR_EL0 definitions */ 1098 #define PMCR_EL0_RESET_VAL U(0x0) 1099 #define PMCR_EL0_N_SHIFT U(11) 1100 #define PMCR_EL0_N_MASK U(0x1f) 1101 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) 1102 #define PMCR_EL0_LP_BIT (U(1) << 7) 1103 #define PMCR_EL0_LC_BIT (U(1) << 6) 1104 #define PMCR_EL0_DP_BIT (U(1) << 5) 1105 #define PMCR_EL0_X_BIT (U(1) << 4) 1106 #define PMCR_EL0_D_BIT (U(1) << 3) 1107 #define PMCR_EL0_C_BIT (U(1) << 2) 1108 #define PMCR_EL0_P_BIT (U(1) << 1) 1109 #define PMCR_EL0_E_BIT (U(1) << 0) 1110 1111 /******************************************************************************* 1112 * Definitions for system register interface to SVE 1113 ******************************************************************************/ 1114 #define ZCR_EL3 S3_6_C1_C2_0 1115 #define ZCR_EL2 S3_4_C1_C2_0 1116 1117 /* ZCR_EL3 definitions */ 1118 #define ZCR_EL3_LEN_MASK U(0xf) 1119 1120 /* ZCR_EL2 definitions */ 1121 #define ZCR_EL2_LEN_MASK U(0xf) 1122 1123 /******************************************************************************* 1124 * Definitions for system register interface to SME as needed in EL3 1125 ******************************************************************************/ 1126 #define ID_AA64SMFR0_EL1 S3_0_C0_C4_5 1127 #define SMCR_EL3 S3_6_C1_C2_6 1128 1129 /* ID_AA64SMFR0_EL1 definitions */ 1130 #define ID_AA64SMFR0_EL1_SME_FA64_SHIFT U(63) 1131 #define ID_AA64SMFR0_EL1_SME_FA64_MASK U(0x1) 1132 #define SME_FA64_IMPLEMENTED U(0x1) 1133 #define ID_AA64SMFR0_EL1_SME_VER_SHIFT U(55) 1134 #define ID_AA64SMFR0_EL1_SME_VER_MASK ULL(0xf) 1135 #define SME_INST_IMPLEMENTED ULL(0x0) 1136 #define SME2_INST_IMPLEMENTED ULL(0x1) 1137 1138 /* SMCR_ELx definitions */ 1139 #define SMCR_ELX_LEN_SHIFT U(0) 1140 #define SMCR_ELX_LEN_MAX U(0x1ff) 1141 #define SMCR_ELX_FA64_BIT (U(1) << 31) 1142 #define SMCR_ELX_EZT0_BIT (U(1) << 30) 1143 1144 /******************************************************************************* 1145 * Definitions of MAIR encodings for device and normal memory 1146 ******************************************************************************/ 1147 /* 1148 * MAIR encodings for device memory attributes. 1149 */ 1150 #define MAIR_DEV_nGnRnE ULL(0x0) 1151 #define MAIR_DEV_nGnRE ULL(0x4) 1152 #define MAIR_DEV_nGRE ULL(0x8) 1153 #define MAIR_DEV_GRE ULL(0xc) 1154 1155 /* 1156 * MAIR encodings for normal memory attributes. 1157 * 1158 * Cache Policy 1159 * WT: Write Through 1160 * WB: Write Back 1161 * NC: Non-Cacheable 1162 * 1163 * Transient Hint 1164 * NTR: Non-Transient 1165 * TR: Transient 1166 * 1167 * Allocation Policy 1168 * RA: Read Allocate 1169 * WA: Write Allocate 1170 * RWA: Read and Write Allocate 1171 * NA: No Allocation 1172 */ 1173 #define MAIR_NORM_WT_TR_WA ULL(0x1) 1174 #define MAIR_NORM_WT_TR_RA ULL(0x2) 1175 #define MAIR_NORM_WT_TR_RWA ULL(0x3) 1176 #define MAIR_NORM_NC ULL(0x4) 1177 #define MAIR_NORM_WB_TR_WA ULL(0x5) 1178 #define MAIR_NORM_WB_TR_RA ULL(0x6) 1179 #define MAIR_NORM_WB_TR_RWA ULL(0x7) 1180 #define MAIR_NORM_WT_NTR_NA ULL(0x8) 1181 #define MAIR_NORM_WT_NTR_WA ULL(0x9) 1182 #define MAIR_NORM_WT_NTR_RA ULL(0xa) 1183 #define MAIR_NORM_WT_NTR_RWA ULL(0xb) 1184 #define MAIR_NORM_WB_NTR_NA ULL(0xc) 1185 #define MAIR_NORM_WB_NTR_WA ULL(0xd) 1186 #define MAIR_NORM_WB_NTR_RA ULL(0xe) 1187 #define MAIR_NORM_WB_NTR_RWA ULL(0xf) 1188 1189 #define MAIR_NORM_OUTER_SHIFT U(4) 1190 1191 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 1192 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 1193 1194 /* PAR_EL1 fields */ 1195 #define PAR_F_SHIFT U(0) 1196 #define PAR_F_MASK ULL(0x1) 1197 1198 #define PAR_D128_ADDR_MASK GENMASK(55, 12) /* 44-bits-wide page address */ 1199 #define PAR_ADDR_MASK GENMASK(51, 12) /* 40-bits-wide page address */ 1200 1201 /******************************************************************************* 1202 * Definitions for system register interface to SPE 1203 ******************************************************************************/ 1204 #define PMBLIMITR_EL1 S3_0_C9_C10_0 1205 1206 /******************************************************************************* 1207 * Definitions for system register interface, shifts and masks for MPAM 1208 ******************************************************************************/ 1209 #define MPAMIDR_EL1 S3_0_C10_C4_4 1210 #define MPAM2_EL2 S3_4_C10_C5_0 1211 #define MPAMHCR_EL2 S3_4_C10_C4_0 1212 #define MPAM3_EL3 S3_6_C10_C5_0 1213 1214 #define MPAMIDR_EL1_VPMR_MAX_SHIFT ULL(18) 1215 #define MPAMIDR_EL1_VPMR_MAX_MASK ULL(0x7) 1216 /******************************************************************************* 1217 * Definitions for system register interface to AMU for FEAT_AMUv1 1218 ******************************************************************************/ 1219 #define AMCR_EL0 S3_3_C13_C2_0 1220 #define AMCFGR_EL0 S3_3_C13_C2_1 1221 #define AMCGCR_EL0 S3_3_C13_C2_2 1222 #define AMUSERENR_EL0 S3_3_C13_C2_3 1223 #define AMCNTENCLR0_EL0 S3_3_C13_C2_4 1224 #define AMCNTENSET0_EL0 S3_3_C13_C2_5 1225 #define AMCNTENCLR1_EL0 S3_3_C13_C3_0 1226 #define AMCNTENSET1_EL0 S3_3_C13_C3_1 1227 1228 /* Activity Monitor Group 0 Event Counter Registers */ 1229 #define AMEVCNTR00_EL0 S3_3_C13_C4_0 1230 #define AMEVCNTR01_EL0 S3_3_C13_C4_1 1231 #define AMEVCNTR02_EL0 S3_3_C13_C4_2 1232 #define AMEVCNTR03_EL0 S3_3_C13_C4_3 1233 1234 /* Activity Monitor Group 0 Event Type Registers */ 1235 #define AMEVTYPER00_EL0 S3_3_C13_C6_0 1236 #define AMEVTYPER01_EL0 S3_3_C13_C6_1 1237 #define AMEVTYPER02_EL0 S3_3_C13_C6_2 1238 #define AMEVTYPER03_EL0 S3_3_C13_C6_3 1239 1240 /* Activity Monitor Group 1 Event Counter Registers */ 1241 #define AMEVCNTR10_EL0 S3_3_C13_C12_0 1242 #define AMEVCNTR11_EL0 S3_3_C13_C12_1 1243 #define AMEVCNTR12_EL0 S3_3_C13_C12_2 1244 #define AMEVCNTR13_EL0 S3_3_C13_C12_3 1245 #define AMEVCNTR14_EL0 S3_3_C13_C12_4 1246 #define AMEVCNTR15_EL0 S3_3_C13_C12_5 1247 #define AMEVCNTR16_EL0 S3_3_C13_C12_6 1248 #define AMEVCNTR17_EL0 S3_3_C13_C12_7 1249 #define AMEVCNTR18_EL0 S3_3_C13_C13_0 1250 #define AMEVCNTR19_EL0 S3_3_C13_C13_1 1251 #define AMEVCNTR1A_EL0 S3_3_C13_C13_2 1252 #define AMEVCNTR1B_EL0 S3_3_C13_C13_3 1253 #define AMEVCNTR1C_EL0 S3_3_C13_C13_4 1254 #define AMEVCNTR1D_EL0 S3_3_C13_C13_5 1255 #define AMEVCNTR1E_EL0 S3_3_C13_C13_6 1256 #define AMEVCNTR1F_EL0 S3_3_C13_C13_7 1257 1258 /* Activity Monitor Group 1 Event Type Registers */ 1259 #define AMEVTYPER10_EL0 S3_3_C13_C14_0 1260 #define AMEVTYPER11_EL0 S3_3_C13_C14_1 1261 #define AMEVTYPER12_EL0 S3_3_C13_C14_2 1262 #define AMEVTYPER13_EL0 S3_3_C13_C14_3 1263 #define AMEVTYPER14_EL0 S3_3_C13_C14_4 1264 #define AMEVTYPER15_EL0 S3_3_C13_C14_5 1265 #define AMEVTYPER16_EL0 S3_3_C13_C14_6 1266 #define AMEVTYPER17_EL0 S3_3_C13_C14_7 1267 #define AMEVTYPER18_EL0 S3_3_C13_C15_0 1268 #define AMEVTYPER19_EL0 S3_3_C13_C15_1 1269 #define AMEVTYPER1A_EL0 S3_3_C13_C15_2 1270 #define AMEVTYPER1B_EL0 S3_3_C13_C15_3 1271 #define AMEVTYPER1C_EL0 S3_3_C13_C15_4 1272 #define AMEVTYPER1D_EL0 S3_3_C13_C15_5 1273 #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 1274 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 1275 1276 /* AMCNTENSET0_EL0 definitions */ 1277 #define AMCNTENSET0_EL0_Pn_SHIFT U(0) 1278 #define AMCNTENSET0_EL0_Pn_MASK ULL(0xffff) 1279 1280 /* AMCNTENSET1_EL0 definitions */ 1281 #define AMCNTENSET1_EL0_Pn_SHIFT U(0) 1282 #define AMCNTENSET1_EL0_Pn_MASK ULL(0xffff) 1283 1284 /* AMCNTENCLR0_EL0 definitions */ 1285 #define AMCNTENCLR0_EL0_Pn_SHIFT U(0) 1286 #define AMCNTENCLR0_EL0_Pn_MASK ULL(0xffff) 1287 1288 /* AMCNTENCLR1_EL0 definitions */ 1289 #define AMCNTENCLR1_EL0_Pn_SHIFT U(0) 1290 #define AMCNTENCLR1_EL0_Pn_MASK ULL(0xffff) 1291 1292 /* AMCFGR_EL0 definitions */ 1293 #define AMCFGR_EL0_NCG_SHIFT U(28) 1294 #define AMCFGR_EL0_NCG_MASK U(0xf) 1295 #define AMCFGR_EL0_N_SHIFT U(0) 1296 #define AMCFGR_EL0_N_MASK U(0xff) 1297 1298 /* AMCGCR_EL0 definitions */ 1299 #define AMCGCR_EL0_CG0NC_SHIFT U(0) 1300 #define AMCGCR_EL0_CG0NC_MASK U(0xff) 1301 #define AMCGCR_EL0_CG1NC_SHIFT U(8) 1302 #define AMCGCR_EL0_CG1NC_MASK U(0xff) 1303 1304 /* MPAM register definitions */ 1305 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) 1306 #define MPAM3_EL3_TRAPLOWER_BIT (ULL(1) << 62) 1307 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) 1308 #define MPAM3_EL3_RESET_VAL MPAM3_EL3_TRAPLOWER_BIT 1309 1310 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) 1311 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) 1312 1313 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) 1314 1315 /******************************************************************************* 1316 * Definitions for system register interface to AMU for FEAT_AMUv1p1 1317 ******************************************************************************/ 1318 1319 /* Definition for register defining which virtual offsets are implemented. */ 1320 #define AMCG1IDR_EL0 S3_3_C13_C2_6 1321 #define AMCG1IDR_CTR_MASK ULL(0xffff) 1322 #define AMCG1IDR_CTR_SHIFT U(0) 1323 #define AMCG1IDR_VOFF_MASK ULL(0xffff) 1324 #define AMCG1IDR_VOFF_SHIFT U(16) 1325 1326 /* New bit added to AMCR_EL0 */ 1327 #define AMCR_CG1RZ_SHIFT U(17) 1328 #define AMCR_CG1RZ_BIT (ULL(0x1) << AMCR_CG1RZ_SHIFT) 1329 1330 /* 1331 * Definitions for virtual offset registers for architected activity monitor 1332 * event counters. 1333 * AMEVCNTVOFF01_EL2 intentionally left undefined, as it does not exist. 1334 */ 1335 #define AMEVCNTVOFF00_EL2 S3_4_C13_C8_0 1336 #define AMEVCNTVOFF02_EL2 S3_4_C13_C8_2 1337 #define AMEVCNTVOFF03_EL2 S3_4_C13_C8_3 1338 1339 /* 1340 * Definitions for virtual offset registers for auxiliary activity monitor event 1341 * counters. 1342 */ 1343 #define AMEVCNTVOFF10_EL2 S3_4_C13_C10_0 1344 #define AMEVCNTVOFF11_EL2 S3_4_C13_C10_1 1345 #define AMEVCNTVOFF12_EL2 S3_4_C13_C10_2 1346 #define AMEVCNTVOFF13_EL2 S3_4_C13_C10_3 1347 #define AMEVCNTVOFF14_EL2 S3_4_C13_C10_4 1348 #define AMEVCNTVOFF15_EL2 S3_4_C13_C10_5 1349 #define AMEVCNTVOFF16_EL2 S3_4_C13_C10_6 1350 #define AMEVCNTVOFF17_EL2 S3_4_C13_C10_7 1351 #define AMEVCNTVOFF18_EL2 S3_4_C13_C11_0 1352 #define AMEVCNTVOFF19_EL2 S3_4_C13_C11_1 1353 #define AMEVCNTVOFF1A_EL2 S3_4_C13_C11_2 1354 #define AMEVCNTVOFF1B_EL2 S3_4_C13_C11_3 1355 #define AMEVCNTVOFF1C_EL2 S3_4_C13_C11_4 1356 #define AMEVCNTVOFF1D_EL2 S3_4_C13_C11_5 1357 #define AMEVCNTVOFF1E_EL2 S3_4_C13_C11_6 1358 #define AMEVCNTVOFF1F_EL2 S3_4_C13_C11_7 1359 1360 /******************************************************************************* 1361 * Realm management extension register definitions 1362 ******************************************************************************/ 1363 #define GPCCR_EL3 S3_6_C2_C1_6 1364 #define GPTBR_EL3 S3_6_C2_C1_4 1365 1366 #define SCXTNUM_EL2 S3_4_C13_C0_7 1367 #define SCXTNUM_EL1 S3_0_C13_C0_7 1368 #define SCXTNUM_EL0 S3_3_C13_C0_7 1369 1370 /******************************************************************************* 1371 * RAS system registers 1372 ******************************************************************************/ 1373 #define DISR_EL1 S3_0_C12_C1_1 1374 #define DISR_A_BIT U(31) 1375 1376 #define ERRIDR_EL1 S3_0_C5_C3_0 1377 #define ERRIDR_MASK U(0xffff) 1378 1379 #define ERRSELR_EL1 S3_0_C5_C3_1 1380 1381 /* System register access to Standard Error Record registers */ 1382 #define ERXFR_EL1 S3_0_C5_C4_0 1383 #define ERXCTLR_EL1 S3_0_C5_C4_1 1384 #define ERXSTATUS_EL1 S3_0_C5_C4_2 1385 #define ERXADDR_EL1 S3_0_C5_C4_3 1386 #define ERXPFGF_EL1 S3_0_C5_C4_4 1387 #define ERXPFGCTL_EL1 S3_0_C5_C4_5 1388 #define ERXPFGCDN_EL1 S3_0_C5_C4_6 1389 #define ERXMISC0_EL1 S3_0_C5_C5_0 1390 #define ERXMISC1_EL1 S3_0_C5_C5_1 1391 1392 #define ERXCTLR_ED_SHIFT U(0) 1393 #define ERXCTLR_ED_BIT (U(1) << ERXCTLR_ED_SHIFT) 1394 #define ERXCTLR_UE_BIT (U(1) << 4) 1395 1396 #define ERXPFGCTL_UC_BIT (U(1) << 1) 1397 #define ERXPFGCTL_UEU_BIT (U(1) << 2) 1398 #define ERXPFGCTL_CDEN_BIT (U(1) << 31) 1399 1400 /******************************************************************************* 1401 * Armv8.3 Pointer Authentication Registers 1402 ******************************************************************************/ 1403 #define APIAKeyLo_EL1 S3_0_C2_C1_0 1404 #define APIAKeyHi_EL1 S3_0_C2_C1_1 1405 #define APIBKeyLo_EL1 S3_0_C2_C1_2 1406 #define APIBKeyHi_EL1 S3_0_C2_C1_3 1407 #define APDAKeyLo_EL1 S3_0_C2_C2_0 1408 #define APDAKeyHi_EL1 S3_0_C2_C2_1 1409 #define APDBKeyLo_EL1 S3_0_C2_C2_2 1410 #define APDBKeyHi_EL1 S3_0_C2_C2_3 1411 #define APGAKeyLo_EL1 S3_0_C2_C3_0 1412 #define APGAKeyHi_EL1 S3_0_C2_C3_1 1413 1414 /******************************************************************************* 1415 * Armv8.4 Data Independent Timing Registers 1416 ******************************************************************************/ 1417 #define DIT S3_3_C4_C2_5 1418 #define DIT_BIT BIT(24) 1419 1420 /******************************************************************************* 1421 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field 1422 ******************************************************************************/ 1423 #define SSBS S3_3_C4_C2_6 1424 1425 /******************************************************************************* 1426 * Armv8.5 - Memory Tagging Extension Registers 1427 ******************************************************************************/ 1428 #define TFSRE0_EL1 S3_0_C5_C6_1 1429 #define TFSR_EL1 S3_0_C5_C6_0 1430 #define RGSR_EL1 S3_0_C1_C0_5 1431 #define GCR_EL1 S3_0_C1_C0_6 1432 1433 #define GCR_EL1_RRND_BIT (UL(1) << 16) 1434 1435 /******************************************************************************* 1436 * Armv8.5 - Random Number Generator Registers 1437 ******************************************************************************/ 1438 #define RNDR S3_3_C2_C4_0 1439 #define RNDRRS S3_3_C2_C4_1 1440 1441 /******************************************************************************* 1442 * FEAT_HCX - Extended Hypervisor Configuration Register 1443 ******************************************************************************/ 1444 #define HCRX_EL2 S3_4_C1_C2_2 1445 #define HCRX_EL2_MSCEn_BIT (UL(1) << 11) 1446 #define HCRX_EL2_MCE2_BIT (UL(1) << 10) 1447 #define HCRX_EL2_CMOW_BIT (UL(1) << 9) 1448 #define HCRX_EL2_VFNMI_BIT (UL(1) << 8) 1449 #define HCRX_EL2_VINMI_BIT (UL(1) << 7) 1450 #define HCRX_EL2_TALLINT_BIT (UL(1) << 6) 1451 #define HCRX_EL2_SMPME_BIT (UL(1) << 5) 1452 #define HCRX_EL2_FGTnXS_BIT (UL(1) << 4) 1453 #define HCRX_EL2_FnXS_BIT (UL(1) << 3) 1454 #define HCRX_EL2_EnASR_BIT (UL(1) << 2) 1455 #define HCRX_EL2_EnALS_BIT (UL(1) << 1) 1456 #define HCRX_EL2_EnAS0_BIT (UL(1) << 0) 1457 #define HCRX_EL2_INIT_VAL ULL(0x0) 1458 1459 /******************************************************************************* 1460 * FEAT_FGT - Definitions for Fine-Grained Trap registers 1461 ******************************************************************************/ 1462 #define HFGITR_EL2_INIT_VAL ULL(0x180000000000000) 1463 #define HFGRTR_EL2_INIT_VAL ULL(0xC4000000000000) 1464 #define HFGWTR_EL2_INIT_VAL ULL(0xC4000000000000) 1465 1466 /******************************************************************************* 1467 * FEAT_TCR2 - Extended Translation Control Registers 1468 ******************************************************************************/ 1469 #define TCR2_EL1 S3_0_C2_C0_3 1470 #define TCR2_EL2 S3_4_C2_C0_3 1471 1472 /******************************************************************************* 1473 * Permission indirection and overlay Registers 1474 ******************************************************************************/ 1475 1476 #define PIRE0_EL1 S3_0_C10_C2_2 1477 #define PIRE0_EL2 S3_4_C10_C2_2 1478 #define PIR_EL1 S3_0_C10_C2_3 1479 #define PIR_EL2 S3_4_C10_C2_3 1480 #define POR_EL1 S3_0_C10_C2_4 1481 #define POR_EL2 S3_4_C10_C2_4 1482 #define S2PIR_EL2 S3_4_C10_C2_5 1483 #define S2POR_EL1 S3_0_C10_C2_5 1484 1485 /******************************************************************************* 1486 * FEAT_GCS - Guarded Control Stack Registers 1487 ******************************************************************************/ 1488 #define GCSCR_EL2 S3_4_C2_C5_0 1489 #define GCSPR_EL2 S3_4_C2_C5_1 1490 #define GCSCR_EL1 S3_0_C2_C5_0 1491 #define GCSCRE0_EL1 S3_0_C2_C5_2 1492 #define GCSPR_EL1 S3_0_C2_C5_1 1493 #define GCSPR_EL0 S3_3_C2_C5_1 1494 1495 #define GCSCR_EXLOCK_EN_BIT (UL(1) << 6) 1496 1497 /******************************************************************************* 1498 * FEAT_TRF - Trace Filter Control Registers 1499 ******************************************************************************/ 1500 #define TRFCR_EL2 S3_4_C1_C2_1 1501 #define TRFCR_EL1 S3_0_C1_C2_1 1502 1503 /******************************************************************************* 1504 * FEAT_THE - Translation Hardening Extension Registers 1505 ******************************************************************************/ 1506 #define RCWMASK_EL1 S3_0_C13_C0_6 1507 #define RCWSMASK_EL1 S3_0_C13_C0_3 1508 1509 /******************************************************************************* 1510 * FEAT_SCTLR2 - Extension to SCTLR_ELx Registers 1511 ******************************************************************************/ 1512 #define SCTLR2_EL2 S3_4_C1_C0_3 1513 #define SCTLR2_EL1 S3_0_C1_C0_3 1514 1515 /******************************************************************************* 1516 * FEAT_LS64_ACCDATA - LoadStore64B with status data 1517 ******************************************************************************/ 1518 #define ACCDATA_EL1 S3_0_C13_C0_5 1519 1520 /******************************************************************************* 1521 * Definitions for DynamicIQ Shared Unit registers 1522 ******************************************************************************/ 1523 #define CLUSTERPWRDN_EL1 S3_0_c15_c3_6 1524 1525 /* CLUSTERPWRDN_EL1 register definitions */ 1526 #define DSU_CLUSTER_PWR_OFF 0 1527 #define DSU_CLUSTER_PWR_ON 1 1528 #define DSU_CLUSTER_PWR_MASK U(1) 1529 #define DSU_CLUSTER_MEM_RET BIT(1) 1530 1531 /******************************************************************************* 1532 * Definitions for CPU Power/Performance Management registers 1533 ******************************************************************************/ 1534 1535 #define CPUPPMCR_EL3 S3_6_C15_C2_0 1536 #define CPUPPMCR_EL3_MPMMPINCTL_SHIFT UINT64_C(0) 1537 #define CPUPPMCR_EL3_MPMMPINCTL_MASK UINT64_C(0x1) 1538 1539 #define CPUMPMMCR_EL3 S3_6_C15_C2_1 1540 #define CPUMPMMCR_EL3_MPMM_EN_SHIFT UINT64_C(0) 1541 #define CPUMPMMCR_EL3_MPMM_EN_MASK UINT64_C(0x1) 1542 1543 /* alternative system register encoding for the "sb" speculation barrier */ 1544 #define SYSREG_SB S0_3_C3_C0_7 1545 1546 #define CLUSTERPMCR_EL1 S3_0_C15_C5_0 1547 #define CLUSTERPMCNTENSET_EL1 S3_0_C15_C5_1 1548 #define CLUSTERPMCCNTR_EL1 S3_0_C15_C6_0 1549 #define CLUSTERPMOVSSET_EL1 S3_0_C15_C5_3 1550 #define CLUSTERPMOVSCLR_EL1 S3_0_C15_C5_4 1551 #define CLUSTERPMSELR_EL1 S3_0_C15_C5_5 1552 #define CLUSTERPMXEVTYPER_EL1 S3_0_C15_C6_1 1553 #define CLUSTERPMXEVCNTR_EL1 S3_0_C15_C6_2 1554 1555 #define CLUSTERPMCR_E_BIT BIT(0) 1556 #define CLUSTERPMCR_N_SHIFT U(11) 1557 #define CLUSTERPMCR_N_MASK U(0x1f) 1558 1559 #endif /* ARCH_H */ 1560