1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _BROADWELL_SYSTEMAGENT_H_ 4 #define _BROADWELL_SYSTEMAGENT_H_ 5 6 #include <soc/iomap.h> 7 8 #define SA_IGD_OPROM_VENDEV 0x80860406 9 10 #define IGD_HASWELL_ULT_GT1 0x0a06 11 #define IGD_HASWELL_ULT_GT2 0x0a16 12 #define IGD_HASWELL_ULT_GT3 0x0a26 13 #define IGD_HASWELL_ULX_GT1 0x0a0e 14 #define IGD_HASWELL_ULX_GT2 0x0a1e 15 #define IGD_BROADWELL_U_GT1 0x1606 16 #define IGD_BROADWELL_U_GT2 0x1616 17 #define IGD_BROADWELL_U_GT3_15W 0x1626 18 #define IGD_BROADWELL_U_GT3_28W 0x162b 19 #define IGD_BROADWELL_Y_GT2 0x161e 20 #define IGD_BROADWELL_H_GT2 0x1612 21 #define IGD_BROADWELL_H_GT3 0x1622 22 23 #define MCH_BROADWELL_ID_U_Y 0x1604 24 #define MCH_BROADWELL_REV_D0 0x06 25 #define MCH_BROADWELL_REV_E0 0x08 26 #define MCH_BROADWELL_REV_F0 0x09 27 28 /* Device 0:0.0 PCI configuration space */ 29 30 #define EPBAR 0x40 31 #define MCHBAR 0x48 32 #define GGC 0x50 /* GMCH Graphics Control */ 33 #define DEVEN 0x54 /* Device Enable */ 34 #define DEVEN_D7EN (1 << 14) 35 #define DEVEN_D4EN (1 << 7) 36 #define DEVEN_D3EN (1 << 5) 37 #define DEVEN_D2EN (1 << 4) 38 #define DEVEN_D1F0EN (1 << 3) 39 #define DEVEN_D1F1EN (1 << 2) 40 #define DEVEN_D1F2EN (1 << 1) 41 #define DEVEN_D0EN (1 << 0) 42 #define DPR 0x5c 43 #define DPR_EPM (1 << 2) 44 #define DPR_PRS (1 << 1) 45 #define DPR_SIZE_MASK 0xff0 46 #define PCIEXBAR 0x60 47 #define DMIBAR 0x68 48 49 #define MESEG_BASE 0x70 /* Management Engine Base. */ 50 #define MESEG_LIMIT 0x78 /* Management Engine Limit. */ 51 52 #define PAM0 0x80 53 #define PAM1 0x81 54 #define PAM2 0x82 55 #define PAM3 0x83 56 #define PAM4 0x84 57 #define PAM5 0x85 58 #define PAM6 0x86 59 60 #define SMRAM 0x88 /* System Management RAM Control */ 61 #define D_OPEN (1 << 6) 62 #define D_CLS (1 << 5) 63 #define D_LCK (1 << 4) 64 #define G_SMRAME (1 << 3) 65 #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) 66 67 #define REMAPBASE 0x90 /* Remap base. */ 68 #define REMAPLIMIT 0x98 /* Remap limit. */ 69 #define TOM 0xa0 /* Top of DRAM in memory controller space. */ 70 #define TOUUD 0xa8 /* Top of Upper Usable DRAM */ 71 #define BDSM 0xb0 /* Base Data Stolen Memory */ 72 #define BGSM 0xb4 /* Base GTT Stolen Memory */ 73 #define TSEG 0xb8 /* TSEG base */ 74 #define TOLUD 0xbc /* Top of Low Used Memory */ 75 #define SKPAD 0xdc /* Scratchpad Data */ 76 77 #define CAPID0_A 0xe4 78 #define VTD_DISABLE (1 << 23) 79 80 #define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */ 81 #define DMAR_LCKDN (1 << 31) 82 #define PRSCAPDIS (1 << 2) 83 84 /* MCHBAR */ 85 #include <northbridge/intel/common/fixed_bars.h> 86 87 /* Memory controller characteristics */ 88 #define NUM_CHANNELS 2 89 90 #define MAD_CHNL 0x5000 91 #define MAD_DIMM(ch) (0x5004 + 4 * (ch)) 92 93 #define MRC_REVISION 0x5034 94 95 #define GFXVTBAR 0x5400 96 #define EDRAMBAR 0x5408 97 #define VTVC0BAR 0x5410 98 #define MCH_PAIR 0x5418 99 #define GDXCBAR 0x5420 100 101 #define MCH_DDR_POWER_LIMIT_LO 0x58e0 102 #define MCH_DDR_POWER_LIMIT_HI 0x58e4 103 104 #define MCH_PKG_POWER_LIMIT_LO 0x59a0 105 #define MCH_PKG_POWER_LIMIT_HI 0x59a4 106 107 /* PCODE MMIO communications live in the MCHBAR */ 108 #define BIOS_MAILBOX_DATA 0x5da0 109 110 #define BIOS_MAILBOX_INTERFACE 0x5da4 111 #define MAILBOX_RUN_BUSY (1 << 31) 112 #define MAILBOX_BIOS_CMD_READ_PCS 1 113 #define MAILBOX_BIOS_CMD_WRITE_PCS 2 114 #define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509 115 #define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909 116 #define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa 117 #define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb 118 #define MAILBOX_BIOS_CMD_READ_C9C10_VOLTAGE 0x26 119 #define MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE 0x27 120 121 /* Errors are returned back in bits 7:0 */ 122 #define MAILBOX_BIOS_ERROR_NONE 0 123 #define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1 124 #define MAILBOX_BIOS_ERROR_TIMEOUT 2 125 #define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3 126 #define MAILBOX_BIOS_ERROR_RESERVED 4 127 #define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5 128 #define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6 129 #define MAILBOX_BIOS_ERROR_VR_ERROR 7 130 131 #define BIOS_RESET_CPL 0x5da8 132 133 #define MC_BIOS_DATA 0x5e04 134 135 /* System Agent identification */ 136 u8 systemagent_revision(void); 137 138 #endif 139