| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/ |
| D | AArch64MIPeepholeOpt.cpp | 176 T &Imm1) -> std::optional<OpcodePair> { in visitAND()
183 Register NewDstReg) { in visitAND()
302 static bool splitAddSubImm(T Imm, unsigned RegSize, T &Imm0, T &Imm1) { in splitAddSubImm()
340 T &Imm1) -> std::optional<OpcodePair> { in visitADDSUB()
349 Register NewDstReg) { in visitADDSUB()
372 T &Imm1) -> std::optional<OpcodePair> { in visitADDSSUBS()
390 Register NewDstReg) { in visitADDSSUBS()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 195 void MipsTargetStreamer::emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2, in emitII()
243 unsigned Reg1, int16_t Imm0, int16_t Imm1, in emitRRIII()
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 204 void MipsTargetStreamer::emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2, in emitII()
252 unsigned Reg1, int16_t Imm0, int16_t Imm1, in emitRRIII()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCMIPeephole.cpp | 1289 int16_t Imm1 = 0, NewImm1 = 0, Imm2 = 0, NewImm2 = 0; in eliminateRedundantCompare() local
|
| D | PPCInstrInfo.cpp | 2223 static unsigned selectReg(int64_t Imm1, int64_t Imm2, unsigned CompareOpc, in selectReg()
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/PowerPC/ |
| D | PPCMIPeephole.cpp | 1417 int16_t Imm1 = 0, NewImm1 = 0, Imm2 = 0, NewImm2 = 0; in eliminateRedundantCompare() local
|
| D | PPCInstrInfo.cpp | 3222 static unsigned selectReg(int64_t Imm1, int64_t Imm2, unsigned CompareOpc, in selectReg()
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 158 void MipsTargetStreamer::emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2, in emitII()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | CombinerHelper.cpp | 1354 Register Imm1 = MI.getOperand(2).getReg(); in matchPtrAddImmedChain() local
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 2024 uint64_t Imm1, uint64_t Imm2) { in fastEmitInst_rii()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 1912 bool Op0IsKill, uint64_t Imm1, in fastEmitInst_rii()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 2146 bool Op0IsKill, uint64_t Imm1, in fastEmitInst_rii()
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/LoongArch/ |
| D | LoongArchISelLowering.cpp | 768 unsigned Imm1 = cast<ConstantSDNode>(Op2)->getZExtValue(); in lowerINTRINSIC_VOID() local
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/ |
| D | HexagonConstPropagation.cpp | 2603 bool Imm1 = Src1.isImm(), Imm2 = Src2.isImm(); in evaluateHexCompare2() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonConstPropagation.cpp | 2604 bool Imm1 = Src1.isImm(), Imm2 = Src2.isImm(); in evaluateHexCompare2() local
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/GlobalISel/ |
| D | CombinerHelper.cpp | 1362 Register Imm1 = MI.getOperand(2).getReg(); in matchPtrAddImmedChain() local
1441 Register Imm1 = MI.getOperand(2).getReg(); in matchShiftImmedChain() local
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 4451 int64_t Imm1, Imm2; in parseModImm() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 5245 int64_t Imm1, Imm2; in parseModImm() local
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 5450 int64_t Imm1, Imm2; in parseModImm() local
|