1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_MEDIATEK_MT8173_INFRACFG_H__ 4 #define __SOC_MEDIATEK_MT8173_INFRACFG_H__ 5 6 #include <soc/addressmap.h> 7 #include <types.h> 8 9 struct mt8173_infracfg_regs { 10 u32 top_ckmuxsel; 11 u8 reserved0[4]; 12 u32 top_ckdiv1; 13 u8 reserved1[4]; 14 u32 top_dcmctl; 15 u32 top_dcmdbc; 16 u8 reserved2[24]; 17 u32 infra_rst0; 18 u32 infra_rst1; 19 u8 reserved3[8]; 20 u32 infra_pdn0; 21 u32 infra_pdn1; 22 u32 infra_pdn_sta; 23 u8 reserved4[4]; 24 u32 infra_dcmctl; 25 u32 infra_dcmdbc; 26 u32 infra_dcmfsel; 27 u8 reserved5[20]; 28 u32 devapc_pdn0; 29 u32 devapc_pdn1; 30 u32 devapc_pdn_sta; 31 u8 reserved6[4]; 32 u32 trng_pdn0; 33 u32 trng_pdn1; 34 u32 trng_pdn_sta; 35 u8 reserved7[4]; 36 u32 infra_pdn_sen; 37 u8 reserved8[268]; 38 u32 infra_ao_mbist_delsel; 39 u32 infra_ao_mbist_bsel; 40 u32 infra_ao_mbist_cfg; 41 u32 infra_ao_mbist_fuse_sramrom; 42 u32 infra_ao_mbist_fuse_afe; 43 u32 infra_ao_mbist_holdb; 44 u32 infra_ao_mbist_mode; 45 u32 infra_ao_mbist_mon_sel; 46 u32 infra_ao_mbist_result; 47 u8 reserved9[44]; 48 u32 infra_ao_mbist_fuse_mon; 49 u8 reserved10[12]; 50 u32 topaxi_si0_ctl; 51 u32 topaxi_si1_ctl; 52 u8 reserved11[4]; 53 u32 infra_mci_si0_ctl; 54 u32 infra_mci_si1_ctl; 55 u32 infra_mci_si2_ctl; 56 u32 infra_mci_async_ctrl; 57 u32 infra_mci_cg_mfg_sec_sta; 58 u32 topaxi_prot_en; 59 u32 topaxi_prot_sta0; 60 u32 topaxi_prot_sta1; 61 u32 topaxi_axi_aslice_ctrl; 62 u32 infra_apb_async_sta; 63 u8 reserved12[12]; 64 u32 infra_mci_trans_con_read; 65 u32 infra_mci_trans_con_write; 66 u32 infra_mci_id_remap_con; 67 u32 infra_mci_emi_trans_con; 68 u8 reserved13[196]; 69 u32 cldma_map0; 70 u8 reserved14[232]; 71 u32 peri_cci_sideband_con; 72 u32 mfg_cci_sideband_con; 73 u8 reserved15[248]; 74 u32 infra_ao_dbg_con0; 75 u32 infra_ao_dbg_con1; 76 u32 infra_ao_dbg_con2; 77 u32 infra_ao_dbg_con3; 78 u8 reserved16[752]; 79 u32 sramrom_boot_addr; 80 u32 sramrom_sec_ctrl; 81 u32 sramrom_sec_addr; 82 u32 sramrom_fpc_boot_addr; 83 u32 sramrom_fpc_boot_con; 84 u8 reserved17[236]; 85 u32 infra_bonding; 86 u8 reserved18[252]; 87 u32 infra_ao_scpsys_apb_async_sta; 88 u32 infra_ao_md32_tx_apb_async_sta; 89 u32 infra_ao_md32_rx_apb_async_sta; 90 u32 infra_ao_cksys_apb_async_sta; 91 u8 reserved19[1264]; 92 u32 infra_misc; 93 u32 infra_acp; 94 }; 95 96 check_member(mt8173_infracfg_regs, infra_pdn0, 0x40); 97 check_member(mt8173_infracfg_regs, topaxi_prot_sta1, 0x228); 98 check_member(mt8173_infracfg_regs, infra_misc, 0xf00); 99 100 static struct mt8173_infracfg_regs *const mt8173_infracfg = 101 (void *)INFRACFG_AO_BASE; 102 103 enum { 104 INFRA_PMIC_WRAP_RST = 1 << 7, 105 L2C_SRAM_PDN = 1 << 7 106 }; 107 108 enum { 109 DDR_4GB_SUPPORT_EN = 1 << 13 110 }; 111 112 #endif /* __SOC_MEDIATEK_MT8173_INFRACFG_H__ */ 113