| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstructionSelector.cpp | 1704 unsigned LaneIdx = Offset / 64; in select() local
2902 Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const { in emitExtractVectorElt()
2986 unsigned LaneIdx = VRegAndVal->Value; in selectExtractElt() local
3119 unsigned LaneIdx = 1; in selectUnmergeValues() local
3866 unsigned LaneIdx, const RegisterBank &RB, in emitLaneInsert()
3917 unsigned LaneIdx = VRegAndVal->Value; in selectInsertElt() local
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| D | AArch64ISelDAGToDAG.cpp | 539 static bool checkHighLaneIndex(SDNode *DL, SDValue &LaneOp, int &LaneIdx) { in checkHighLaneIndex()
563 SDValue &LaneOp, int &LaneIdx) { in checkV64LaneV128()
583 int LaneIdx = -1; // Will hold the lane index. in tryMLAV64LaneV128() local
626 int LaneIdx; in tryMULLV64LaneV128() local
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| D | AArch64ISelLowering.cpp | 8079 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64); in LowerBUILD_VECTOR() local
8138 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64); in LowerBUILD_VECTOR() local
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 419 static bool checkHighLaneIndex(SDNode *DL, SDValue &LaneOp, int &LaneIdx) { in checkHighLaneIndex()
443 SDValue &LaneOp, int &LaneIdx) { in checkV64LaneV128()
463 int LaneIdx = -1; // Will hold the lane index. in tryMLAV64LaneV128() local
506 int LaneIdx; in tryMULLV64LaneV128() local
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| D | AArch64ISelLowering.cpp | 6383 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64); in LowerBUILD_VECTOR() local
6435 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64); in LowerBUILD_VECTOR() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/GISel/ |
| D | AArch64InstructionSelector.cpp | 2703 unsigned LaneIdx = Offset / 64; in select() local
4108 Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const { in emitExtractVectorElt()
4192 unsigned LaneIdx = VRegAndVal->Value.getSExtValue(); in selectExtractElt() local
4327 unsigned LaneIdx = 1; in selectUnmergeValues() local
5254 unsigned LaneIdx, const RegisterBank &RB, in emitLaneInsert()
5370 unsigned LaneIdx = VRegAndVal->Value.getSExtValue(); in selectInsertElt() local
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| D | AArch64PostLegalizerLowering.cpp | 693 auto LaneIdx = getSplatIndex(MI); in matchDupLane() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 809 static bool checkHighLaneIndex(SDNode *DL, SDValue &LaneOp, int &LaneIdx) { in checkHighLaneIndex()
833 SDValue &LaneOp, int &LaneIdx) { in checkV64LaneV128()
853 int LaneIdx = -1; // Will hold the lane index. in tryMLAV64LaneV128() local
896 int LaneIdx; in tryMULLV64LaneV128() local
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| D | AArch64ISelLowering.cpp | 12412 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64); in LowerBUILD_VECTOR() local
12491 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64); in LowerBUILD_VECTOR() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineSimplifyDemanded.cpp | 1695 unsigned LaneIdx = Lane * VWidthPerLane; in SimplifyDemandedVectorElts() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/ |
| D | X86InstCombineIntrinsic.cpp | 1978 unsigned LaneIdx = Lane * VWidthPerLane; in simplifyDemandedVectorEltsIntrinsic() local
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| D | X86ISelLowering.cpp | 7695 int LaneIdx = (Idx / NumEltsPerLane) * NumEltsPerLane; in getHorizDemandedElts() local
23589 unsigned LaneIdx = LExtIndex / NumEltsPerLane; in lowerAddSubToHorizontalOp() local
44669 unsigned LaneIdx = LaneOffset / Vec.getScalarValueSizeInBits(); in combineExtractWithShuffle() local
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 5845 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i32); in LowerBUILD_VECTOR() local
9803 SDValue LaneIdx = DAG.getConstant(Idx, dl, MVT::i32); in PerformARMBUILD_VECTORCombine() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 5513 int64_t LaneIdx; in parseSwizzleBroadcast() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 7408 int64_t LaneIdx; in parseSwizzleBroadcast() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 7374 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i32); in LowerBUILD_VECTOR() local
12927 SDValue LaneIdx = DAG.getConstant(Idx, dl, MVT::i32); in PerformARMBUILD_VECTORCombine() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 8099 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i32); in LowerBUILD_VECTOR() local
15205 SDValue LaneIdx = DAG.getConstant(Idx, dl, MVT::i32); in PerformARMBUILD_VECTORCombine() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 6573 int LaneIdx = (Idx / NumEltsPerLane) * NumEltsPerLane; in getHorizDemandedElts() local
20397 unsigned LaneIdx = LExtIndex / NumEltsPerLane; in lowerAddSubToHorizontalOp() local
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 7738 int LaneIdx = (Mask[l + i] % NumElts) - l; in lowerVectorShuffleAsByteRotate() local
|