1{ 2 "License": [ 3 "Copyright (C) 2023 The Android Open Source Project", 4 "", 5 "Licensed under the Apache License, Version 2.0 (the “License”);", 6 "you may not use this file except in compliance with the License.", 7 "You may obtain a copy of the License at", 8 "", 9 " http://www.apache.org/licenses/LICENSE-2.0", 10 "", 11 "Unless required by applicable law or agreed to in writing, software", 12 "distributed under the License is distributed on an “AS IS” BASIS,", 13 "WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.", 14 "See the License for the specific language governing permissions and", 15 "limitations under the License." 16 ], 17 "arch": "common_x86", 18 "insns": [ 19 { 20 "encodings": { 21 "Adcb": { "opcodes": [ "80", "2" ] }, 22 "Rclb": { "opcodes": [ "C0", "2" ] }, 23 "Rcrb": { "opcodes": [ "C0", "3" ] }, 24 "Sbbb": { "opcodes": [ "80", "3" ] } 25 }, 26 "args": [ 27 { "class": "GeneralReg8/Mem8", "usage": "use_def" }, 28 { "class": "Imm8" }, 29 { "class": "FLAGS", "usage": "use_def" } 30 ] 31 }, 32 { 33 "encodings": { 34 "Adcb": { "opcode": "12" }, 35 "Sbbb": { "opcode": "1A" } 36 }, 37 "args": [ 38 { "class": "GeneralReg8", "usage": "use_def" }, 39 { "class": "Mem8", "usage": "use" }, 40 { "class": "FLAGS", "usage": "use_def" } 41 ] 42 }, 43 { 44 "encodings": { 45 "Adcb": { "opcode": "10", "type": "reg_to_rm" }, 46 "Sbbb": { "opcode": "18", "type": "reg_to_rm" } 47 }, 48 "args": [ 49 { "class": "GeneralReg8/Mem8", "usage": "use_def" }, 50 { "class": "GeneralReg8", "usage": "use" }, 51 { "class": "FLAGS", "usage": "use_def" } 52 ] 53 }, 54 { 55 "encodings": { 56 "AdcbAccumulator": { "opcode": "14" }, 57 "SbbbAccumulator": { "opcode": "1C" } 58 }, 59 "args": [ 60 { "class": "AL", "usage": "use_def" }, 61 { "class": "Imm8" }, 62 { "class": "FLAGS", "usage": "use_def" } 63 ] 64 }, 65 { 66 "encodings": { 67 "Adcl": { "opcode": "13" }, 68 "Sbbl": { "opcode": "1B" } 69 }, 70 "args": [ 71 { "class": "GeneralReg32", "usage": "use_def" }, 72 { "class": "Mem32", "usage": "use" }, 73 { "class": "FLAGS", "usage": "use_def" } 74 ] 75 }, 76 { 77 "encodings": { 78 "Adcl": { "opcode": "11", "type": "reg_to_rm" }, 79 "Sbbl": { "opcode": "19", "type": "reg_to_rm", "dependency_breaking": "true" } 80 }, 81 "args": [ 82 { "class": "GeneralReg32/Mem32", "usage": "use_def" }, 83 { "class": "GeneralReg32", "usage": "use" }, 84 { "class": "FLAGS", "usage": "use_def" } 85 ] 86 }, 87 { 88 "encodings": { 89 "Adcl": { "opcodes": [ "81", "2" ] }, 90 "Sbbl": { "opcodes": [ "81", "3" ] } 91 }, 92 "args": [ 93 { "class": "GeneralReg32/Mem32", "usage": "use_def" }, 94 { "class": "Imm32" }, 95 { "class": "FLAGS", "usage": "use_def" } 96 ] 97 }, 98 { 99 "encodings": { 100 "AdclAccumulator": { "opcode": "15" }, 101 "SbblAccumulator": { "opcode": "1D" } 102 }, 103 "args": [ 104 { "class": "EAX", "usage": "use_def" }, 105 { "class": "Imm32" }, 106 { "class": "FLAGS", "usage": "use_def" } 107 ] 108 }, 109 { 110 "encodings": { 111 "AdclImm8": { "opcodes": [ "83", "2" ] }, 112 "Rcll": { "opcodes": [ "C1", "2" ] }, 113 "Rcrl": { "opcodes": [ "C1", "3" ] }, 114 "SbblImm8": { "opcodes": [ "83", "3" ] } 115 }, 116 "args": [ 117 { "class": "GeneralReg32/Mem32", "usage": "use_def" }, 118 { "class": "Imm8" }, 119 { "class": "FLAGS", "usage": "use_def" } 120 ] 121 }, 122 { 123 "encodings": { 124 "Adcw": { "opcodes": [ "66", "13" ] }, 125 "Sbbw": { "opcodes": [ "66", "1B" ] } 126 }, 127 "args": [ 128 { "class": "GeneralReg16", "usage": "use_def" }, 129 { "class": "Mem16", "usage": "use" }, 130 { "class": "FLAGS", "usage": "use_def" } 131 ] 132 }, 133 { 134 "encodings": { 135 "Adcw": { "opcodes": [ "66", "11" ], "type": "reg_to_rm" }, 136 "Sbbw": { "opcodes": [ "66", "19" ], "type": "reg_to_rm" } 137 }, 138 "args": [ 139 { "class": "GeneralReg16/Mem16", "usage": "use_def" }, 140 { "class": "GeneralReg16", "usage": "use" }, 141 { "class": "FLAGS", "usage": "use_def" } 142 ] 143 }, 144 { 145 "encodings": { 146 "Adcw": { "opcodes": [ "66", "81", "2" ] }, 147 "Sbbw": { "opcodes": [ "66", "81", "3" ] } 148 }, 149 "args": [ 150 { "class": "GeneralReg16/Mem16", "usage": "use_def" }, 151 { "class": "Imm16" }, 152 { "class": "FLAGS", "usage": "use_def" } 153 ] 154 }, 155 { 156 "encodings": { 157 "AdcwAccumulator": { "opcodes": [ "66", "15" ] }, 158 "SbbwAccumulator": { "opcodes": [ "66", "1D" ] } 159 }, 160 "args": [ 161 { "class": "AX", "usage": "use_def" }, 162 { "class": "Imm16" }, 163 { "class": "FLAGS", "usage": "use_def" } 164 ] 165 }, 166 { 167 "encodings": { 168 "AdcwImm8": { "opcodes": [ "66", "83", "2" ] }, 169 "Rclw": { "opcodes": [ "66", "C1", "2" ] }, 170 "Rcrw": { "opcodes": [ "66", "C1", "3" ] }, 171 "SbbwImm8": { "opcodes": [ "66", "83", "3" ] } 172 }, 173 "args": [ 174 { "class": "GeneralReg16/Mem16", "usage": "use_def" }, 175 { "class": "Imm8" }, 176 { "class": "FLAGS", "usage": "use_def" } 177 ] 178 }, 179 { 180 "encodings": { 181 "Addb": { "opcodes": [ "80", "0" ] }, 182 "Andb": { "opcodes": [ "80", "4" ] }, 183 "Orb": { "opcodes": [ "80", "1" ] }, 184 "Rolb": { "opcodes": [ "C0", "0" ] }, 185 "Rorb": { "opcodes": [ "C0", "1" ] }, 186 "Sarb": { "opcodes": [ "C0", "7" ] }, 187 "Shlb": { "opcodes": [ "C0", "4" ] }, 188 "Shrb": { "opcodes": [ "C0", "5" ] }, 189 "Subb": { "opcodes": [ "80", "5" ] }, 190 "Xorb": { "opcodes": [ "80", "6" ] } 191 }, 192 "args": [ 193 { "class": "GeneralReg8/Mem8", "usage": "use_def" }, 194 { "class": "Imm8" }, 195 { "class": "FLAGS", "usage": "def" } 196 ] 197 }, 198 { 199 "encodings": { 200 "Addb": { "opcode": "02" }, 201 "Andb": { "opcode": "22" }, 202 "Orb": { "opcode": "0A" }, 203 "Subb": { "opcode": "2A" }, 204 "Xorb": { "opcode": "32" } 205 }, 206 "args": [ 207 { "class": "GeneralReg8", "usage": "use_def" }, 208 { "class": "Mem8", "usage": "use" }, 209 { "class": "FLAGS", "usage": "def" } 210 ] 211 }, 212 { 213 "encodings": { 214 "Addb": { "opcode": "00", "type": "reg_to_rm" }, 215 "Andb": { "opcode": "20", "type": "reg_to_rm" }, 216 "Orb": { "opcode": "08", "type": "reg_to_rm" }, 217 "Subb": { "opcode": "28", "type": "reg_to_rm" }, 218 "Xorb": { "opcode": "30", "type": "reg_to_rm" } 219 }, 220 "args": [ 221 { "class": "GeneralReg8/Mem8", "usage": "use_def" }, 222 { "class": "GeneralReg8", "usage": "use" }, 223 { "class": "FLAGS", "usage": "def" } 224 ] 225 }, 226 { 227 "encodings": { 228 "AddbAccumulator": { "opcode": "04" }, 229 "AndbAccumulator": { "opcode": "24" }, 230 "OrbAccumulator": { "opcode": "0C" }, 231 "SubbAccumulator": { "opcode": "2C" }, 232 "XorbAccumulator": { "opcode": "34" } 233 }, 234 "args": [ 235 { "class": "AL", "usage": "use_def" }, 236 { "class": "Imm8" }, 237 { "class": "FLAGS", "usage": "def" } 238 ] 239 }, 240 { 241 "encodings": { 242 "Addl": { "opcode": "01", "type": "reg_to_rm" }, 243 "Andl": { "opcode": "21", "type": "reg_to_rm" }, 244 "Btcl": { "opcodes": [ "0F", "BB" ], "type": "reg_to_rm" }, 245 "Btrl": { "opcodes": [ "0F", "B3" ], "type": "reg_to_rm" }, 246 "Btsl": { "opcodes": [ "0F", "AB" ], "type": "reg_to_rm" }, 247 "Orl": { "opcode": "09", "type": "reg_to_rm" }, 248 "Subl": { "opcode": "29", "type": "reg_to_rm", "dependency_breaking": "true" }, 249 "Xorl": { "opcode": "31", "type": "reg_to_rm", "dependency_breaking": "true" } 250 }, 251 "args": [ 252 { "class": "GeneralReg32/Mem32", "usage": "use_def" }, 253 { "class": "GeneralReg32", "usage": "use" }, 254 { "class": "FLAGS", "usage": "def" } 255 ] 256 }, 257 { 258 "encodings": { 259 "Addl": { "opcode": "03" }, 260 "Andl": { "opcode": "23" }, 261 "Orl": { "opcode": "0B" }, 262 "Subl": { "opcode": "2B" }, 263 "Xorl": { "opcode": "33" } 264 }, 265 "args": [ 266 { "class": "GeneralReg32", "usage": "use_def" }, 267 { "class": "Mem32", "usage": "use" }, 268 { "class": "FLAGS", "usage": "def" } 269 ] 270 }, 271 { 272 "encodings": { 273 "Addl": { "opcodes": [ "81", "0" ] }, 274 "Andl": { "opcodes": [ "81", "4" ] }, 275 "Orl": { "opcodes": [ "81", "1" ] }, 276 "Subl": { "opcodes": [ "81", "5" ] }, 277 "Xorl": { "opcodes": [ "81", "6" ] } 278 }, 279 "args": [ 280 { "class": "GeneralReg32/Mem32", "usage": "use_def" }, 281 { "class": "Imm32" }, 282 { "class": "FLAGS", "usage": "def" } 283 ] 284 }, 285 { 286 "encodings": { 287 "AddlAccumulator": { "opcode": "05" }, 288 "AndlAccumulator": { "opcode": "25" }, 289 "OrlAccumulator": { "opcode": "0D" }, 290 "SublAccumulator": { "opcode": "2D" }, 291 "XorlAccumulator": { "opcode": "35" } 292 }, 293 "args": [ 294 { "class": "EAX", "usage": "use_def" }, 295 { "class": "Imm32" }, 296 { "class": "FLAGS", "usage": "def" } 297 ] 298 }, 299 { 300 "encodings": { 301 "AddlImm8": { "opcodes": [ "83", "0" ] }, 302 "AndlImm8": { "opcodes": [ "83", "4" ] }, 303 "Btcl": { "opcodes": [ "0F", "BA", "7" ] }, 304 "Btl": { "opcodes": [ "0F", "BA", "4" ] }, 305 "Btrl": { "opcodes": [ "0F", "BA", "6" ] }, 306 "Btsl": { "opcodes": [ "0F", "BA", "5" ] }, 307 "OrlImm8": { "opcodes": [ "83", "1" ] }, 308 "Roll": { "opcodes": [ "C1", "0" ] }, 309 "Rorl": { "opcodes": [ "C1", "1" ] }, 310 "Sarl": { "opcodes": [ "C1", "7" ] }, 311 "Shll": { "opcodes": [ "C1", "4" ] }, 312 "Shrl": { "opcodes": [ "C1", "5" ] }, 313 "SublImm8": { "opcodes": [ "83", "5" ] }, 314 "XorlImm8": { "opcodes": [ "83", "6" ] } 315 }, 316 "args": [ 317 { "class": "GeneralReg32/Mem32", "usage": "use_def" }, 318 { "class": "Imm8" }, 319 { "class": "FLAGS", "usage": "def" } 320 ] 321 }, 322 { 323 "encodings": { 324 "Addpd": { "opcodes": [ "66", "0F", "58" ] }, 325 "Addps": { "opcodes": [ "0F", "58" ] }, 326 "Aesdec": { "feature": "AES", "opcodes": [ "66", "0F", "38", "DE" ] }, 327 "Aesdeclast": { "feature": "AES", "opcodes": [ "66", "0F", "38", "DF" ] }, 328 "Aesenc": { "feature": "AES", "opcodes": [ "66", "0F", "38", "DC" ] }, 329 "Aesenclast": { "feature": "AES", "opcodes": [ "66", "0F", "38", "DD" ] }, 330 "Andpd": { "opcodes": [ "66", "0F", "54" ] }, 331 "Andps": { "opcodes": [ "0F", "54" ] }, 332 "Cmpeqpd": { "opcodes": [ "66", "0F", "C2", "00" ] }, 333 "Cmpeqps": { "opcodes": [ "0F", "C2", "00" ] }, 334 "Cmplepd": { "opcodes": [ "66", "0F", "C2", "02" ] }, 335 "Cmpleps": { "opcodes": [ "0F", "C2", "02" ] }, 336 "Cmpltpd": { "opcodes": [ "66", "0F", "C2", "01" ] }, 337 "Cmpltps": { "opcodes": [ "0F", "C2", "01" ] }, 338 "Cmpneqpd": { "opcodes": [ "66", "0F", "C2", "04" ] }, 339 "Cmpneqps": { "opcodes": [ "0F", "C2", "04" ] }, 340 "Cmpnlepd": { "opcodes": [ "66", "0F", "C2", "06" ] }, 341 "Cmpnleps": { "opcodes": [ "0F", "C2", "06" ] }, 342 "Cmpnltpd": { "opcodes": [ "66", "0F", "C2", "05" ] }, 343 "Cmpnltps": { "opcodes": [ "0F", "C2", "05" ] }, 344 "Cmpordpd": { "opcodes": [ "66", "0F", "C2", "07" ] }, 345 "Cmpordps": { "opcodes": [ "0F", "C2", "07" ] }, 346 "Cmpunordpd": { "opcodes": [ "66", "0F", "C2", "03" ] }, 347 "Cmpunordps": { "opcodes": [ "0F", "C2", "03" ] }, 348 "Divpd": { "opcodes": [ "66", "0F", "5E" ] }, 349 "Divps": { "opcodes": [ "0F", "5E" ] }, 350 "Haddpd": { "feature": "SSE3", "opcodes": [ "66", "0F", "7C" ] }, 351 "Haddps": { "feature": "SSE3", "opcodes": [ "F2", "0F", "7C" ] }, 352 "Maxpd": { "opcodes": [ "66", "0F", "5F" ] }, 353 "Maxps": { "opcodes": [ "0F", "5F" ] }, 354 "Minpd": { "opcodes": [ "66", "0F", "5D" ] }, 355 "Minps": { "opcodes": [ "0F", "5D" ] }, 356 "Mulpd": { "opcodes": [ "66", "0F", "59" ] }, 357 "Mulps": { "opcodes": [ "0F", "59" ] }, 358 "Orpd": { "opcodes": [ "66", "0F", "56" ] }, 359 "Orps": { "opcodes": [ "0F", "56" ] }, 360 "Packssdw": { "opcodes": [ "66", "0F", "6B" ] }, 361 "Packsswb": { "opcodes": [ "66", "0F", "63" ] }, 362 "Packusdw": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "2B" ] }, 363 "Packuswb": { "opcodes": [ "66", "0F", "67" ] }, 364 "Paddb": { "opcodes": [ "66", "0F", "FC" ] }, 365 "Paddd": { "opcodes": [ "66", "0F", "FE" ] }, 366 "Paddq": { "opcodes": [ "66", "0F", "D4" ] }, 367 "Paddsb": { "opcodes": [ "66", "0F", "EC" ] }, 368 "Paddsw": { "opcodes": [ "66", "0F", "ED" ] }, 369 "Paddusb": { "opcodes": [ "66", "0F", "DC" ] }, 370 "Paddusw": { "opcodes": [ "66", "0F", "DD" ] }, 371 "Paddw": { "opcodes": [ "66", "0F", "FD" ] }, 372 "Pand": { "opcodes": [ "66", "0F", "DB" ] }, 373 "Pandn": { "opcodes": [ "66", "0F", "DF" ], "dependency_breaking": "true" }, 374 "Pavgb": { "opcodes": [ "66", "0F", "E0" ] }, 375 "Pavgw": { "opcodes": [ "66", "0F", "E3" ] }, 376 "Pclmulhqhqdq": { "feature": "CLMUL", "opcodes": [ "66", "0F", "3A", "44", "11" ] }, 377 "Pclmulhqlqdq": { "feature": "CLMUL", "opcodes": [ "66", "0F", "3A", "44", "01" ] }, 378 "Pclmullqhqdq": { "feature": "CLMUL", "opcodes": [ "66", "0F", "3A", "44", "10" ] }, 379 "Pclmullqlqdq": { "feature": "CLMUL", "opcodes": [ "66", "0F", "3A", "44", "00" ] }, 380 "Pcmpeqb": { "opcodes": [ "66", "0F", "74" ], "dependency_breaking": "true" }, 381 "Pcmpeqd": { "opcodes": [ "66", "0F", "76" ], "dependency_breaking": "true" }, 382 "Pcmpeqq": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "29" ], "dependency_breaking": "true" }, 383 "Pcmpeqw": { "opcodes": [ "66", "0F", "75" ], "dependency_breaking": "true" }, 384 "Pcmpgtb": { "opcodes": [ "66", "0F", "64" ], "dependency_breaking": "true" }, 385 "Pcmpgtd": { "opcodes": [ "66", "0F", "66" ], "dependency_breaking": "true" }, 386 "Pcmpgtq": { "feature": "SSE4_2", "opcodes": [ "66", "0F", "38", "37" ], "dependency_breaking": "true" }, 387 "Pcmpgtw": { "opcodes": [ "66", "0F", "65" ], "dependency_breaking": "true" }, 388 "Phaddd": { "feature": "SSSE3", "opcodes": [ "66", "0F", "38", "02" ] }, 389 "Phaddw": { "feature": "SSSE3", "opcodes": [ "66", "0F", "38", "01" ] }, 390 "Pmaxsb": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "3C" ] }, 391 "Pmaxsd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "3D" ] }, 392 "Pmaxsw": { "opcodes": [ "66", "0F", "EE" ] }, 393 "Pmaxub": { "opcodes": [ "66", "0F", "DE" ] }, 394 "Pmaxud": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "3F" ] }, 395 "Pmaxuw": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "3E" ] }, 396 "Pminsb": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "38" ] }, 397 "Pminsd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "39" ] }, 398 "Pminsw": { "opcodes": [ "66", "0F", "EA" ] }, 399 "Pminub": { "opcodes": [ "66", "0F", "DA" ] }, 400 "Pminud": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "3B" ] }, 401 "Pminuw": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "3A" ] }, 402 "Pmulhrsw": { "feature": "SSSE3", "opcodes": [ "66", "0F", "38", "0B" ] }, 403 "Pmulhw": { "opcodes": [ "66", "0F", "E5" ] }, 404 "Pmulld": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "40" ] }, 405 "Pmullw": { "opcodes": [ "66", "0F", "D5" ] }, 406 "Pmuludq": { "opcodes": [ "66", "0F", "F4" ] }, 407 "Por": { "opcodes": [ "66", "0F", "EB" ] }, 408 "Psadbw": { "opcodes": [ "66", "0F", "F6" ] }, 409 "Pshufb": { "feature": "SSSE3", "opcodes": [ "66", "0F", "38", "00" ] }, 410 "Pslld": { "opcodes": [ "66", "0F", "F2" ] }, 411 "Psllq": { "opcodes": [ "66", "0F", "F3" ] }, 412 "Psllw": { "opcodes": [ "66", "0F", "F1" ] }, 413 "Psrad": { "opcodes": [ "66", "0F", "E2" ] }, 414 "Psraw": { "opcodes": [ "66", "0F", "E1" ] }, 415 "Psrld": { "opcodes": [ "66", "0F", "D2" ] }, 416 "Psrlq": { "opcodes": [ "66", "0F", "D3" ] }, 417 "Psrlw": { "opcodes": [ "66", "0F", "D1" ] }, 418 "Psubb": { "opcodes": [ "66", "0F", "F8" ], "dependency_breaking": "true" }, 419 "Psubd": { "opcodes": [ "66", "0F", "FA" ], "dependency_breaking": "true" }, 420 "Psubq": { "opcodes": [ "66", "0F", "FB" ], "dependency_breaking": "true" }, 421 "Psubsb": { "opcodes": [ "66", "0F", "E8" ] }, 422 "Psubsw": { "opcodes": [ "66", "0F", "E9" ] }, 423 "Psubusb": { "opcodes": [ "66", "0F", "D8" ] }, 424 "Psubusw": { "opcodes": [ "66", "0F", "D9" ] }, 425 "Psubw": { "opcodes": [ "66", "0F", "F9" ], "dependency_breaking": "true" }, 426 "Punpckhbw": { "opcodes": [ "66", "0F", "68" ] }, 427 "Punpckhdq": { "opcodes": [ "66", "0F", "6A" ] }, 428 "Punpckhqdq": { "opcodes": [ "66", "0F", "6D" ] }, 429 "Punpckhwd": { "opcodes": [ "66", "0F", "69" ] }, 430 "Punpcklbw": { "opcodes": [ "66", "0F", "60" ] }, 431 "Punpckldq": { "opcodes": [ "66", "0F", "62" ] }, 432 "Punpcklqdq": { "opcodes": [ "66", "0F", "6C" ] }, 433 "Punpcklwd": { "opcodes": [ "66", "0F", "61" ] }, 434 "Pxor": { "opcodes": [ "66", "0F", "EF" ], "dependency_breaking": "true" }, 435 "Rsqrtps": { "opcodes": [ "0F", "52" ] }, 436 "Subpd": { "opcodes": [ "66", "0F", "5C" ] }, 437 "Subps": { "opcodes": [ "0F", "5C" ] }, 438 "Unpckhpd": { "opcodes": [ "66", "0F", "15" ] }, 439 "Unpckhps": { "opcodes": [ "0F", "15" ] }, 440 "Unpcklpd": { "opcodes": [ "66", "0F", "14" ] }, 441 "Unpcklps": { "opcodes": [ "0F", "14" ] }, 442 "Vrsqrtps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "52" ] }, 443 "Xorpd": { "opcodes": [ "66", "0F", "57" ], "dependency_breaking": "true" }, 444 "Xorps": { "opcodes": [ "0F", "57" ], "dependency_breaking": "true" } 445 }, 446 "args": [ 447 { "class": "VecReg128", "usage": "use_def" }, 448 { "class": "VecReg128/VecMem128", "usage": "use" } 449 ] 450 }, 451 { 452 "encodings": { 453 "Addsd": { "opcodes": [ "F2", "0F", "58" ] }, 454 "Cmpeqsd": { "opcodes": [ "F2", "0F", "C2", "00" ] }, 455 "Cmplesd": { "opcodes": [ "F2", "0F", "C2", "02" ] }, 456 "Cmpltsd": { "opcodes": [ "F2", "0F", "C2", "01" ] }, 457 "Cmpneqsd": { "opcodes": [ "F2", "0F", "C2", "04" ] }, 458 "Cmpnlesd": { "opcodes": [ "F2", "0F", "C2", "06" ] }, 459 "Cmpnltsd": { "opcodes": [ "F2", "0F", "C2", "05" ] }, 460 "Cmpordsd": { "opcodes": [ "F2", "0F", "C2", "07" ] }, 461 "Cmpunordsd": { "opcodes": [ "F2", "0F", "C2", "03" ] }, 462 "Divsd": { "opcodes": [ "F2", "0F", "5E" ] }, 463 "Mulsd": { "opcodes": [ "F2", "0F", "59" ] }, 464 "Subsd": { "opcodes": [ "F2", "0F", "5C" ] } 465 }, 466 "args": [ 467 { "class": "FpReg64", "usage": "use_def" }, 468 { "class": "FpReg64/VecMem64", "usage": "use" } 469 ] 470 }, 471 { 472 "encodings": { 473 "Addss": { "opcodes": [ "F3", "0F", "58" ] }, 474 "Cmpeqss": { "opcodes": [ "F3", "0F", "C2", "00" ] }, 475 "Cmpless": { "opcodes": [ "F3", "0F", "C2", "02" ] }, 476 "Cmpltss": { "opcodes": [ "F3", "0F", "C2", "01" ] }, 477 "Cmpneqss": { "opcodes": [ "F3", "0F", "C2", "04" ] }, 478 "Cmpnless": { "opcodes": [ "F3", "0F", "C2", "06" ] }, 479 "Cmpnltss": { "opcodes": [ "F3", "0F", "C2", "05" ] }, 480 "Cmpordss": { "opcodes": [ "F3", "0F", "C2", "07" ] }, 481 "Cmpunordss": { "opcodes": [ "F3", "0F", "C2", "03" ] }, 482 "Divss": { "opcodes": [ "F3", "0F", "5E" ] }, 483 "Mulss": { "opcodes": [ "F3", "0F", "59" ] }, 484 "Subss": { "opcodes": [ "F3", "0F", "5C" ] } 485 }, 486 "args": [ 487 { "class": "FpReg32", "usage": "use_def" }, 488 { "class": "FpReg32/VecMem32", "usage": "use" } 489 ] 490 }, 491 { 492 "encodings": { 493 "Addw": { "opcodes": [ "66", "01" ], "type": "reg_to_rm" }, 494 "Andw": { "opcodes": [ "66", "21" ], "type": "reg_to_rm" }, 495 "Btcw": { "opcodes": [ "66", "0F", "BB" ], "type": "reg_to_rm" }, 496 "Btrw": { "opcodes": [ "66", "0F", "B3" ], "type": "reg_to_rm" }, 497 "Btsw": { "opcodes": [ "66", "0F", "AB" ], "type": "reg_to_rm" }, 498 "Orw": { "opcodes": [ "66", "09" ], "type": "reg_to_rm" }, 499 "Subw": { "opcodes": [ "66", "29" ], "type": "reg_to_rm" }, 500 "Xorw": { "opcodes": [ "66", "31" ], "type": "reg_to_rm" } 501 }, 502 "args": [ 503 { "class": "GeneralReg16/Mem16", "usage": "use_def" }, 504 { "class": "GeneralReg16", "usage": "use" }, 505 { "class": "FLAGS", "usage": "def" } 506 ] 507 }, 508 { 509 "encodings": { 510 "Addw": { "opcodes": [ "66", "03" ] }, 511 "Andw": { "opcodes": [ "66", "23" ] }, 512 "Orw": { "opcodes": [ "66", "0B" ] }, 513 "Subw": { "opcodes": [ "66", "2B" ] }, 514 "Xorw": { "opcodes": [ "66", "33" ] } 515 }, 516 "args": [ 517 { "class": "GeneralReg16", "usage": "use_def" }, 518 { "class": "Mem16", "usage": "use" }, 519 { "class": "FLAGS", "usage": "def" } 520 ] 521 }, 522 { 523 "encodings": { 524 "Addw": { "opcodes": [ "66", "81", "0" ] }, 525 "Andw": { "opcodes": [ "66", "81", "4" ] }, 526 "Orw": { "opcodes": [ "66", "81", "1" ] }, 527 "Subw": { "opcodes": [ "66", "81", "5" ] }, 528 "Xorw": { "opcodes": [ "66", "81", "6" ] } 529 }, 530 "args": [ 531 { "class": "GeneralReg16/Mem16", "usage": "use_def" }, 532 { "class": "Imm16" }, 533 { "class": "FLAGS", "usage": "def" } 534 ] 535 }, 536 { 537 "encodings": { 538 "AddwAccumulator": { "opcodes": [ "66", "05" ] }, 539 "AndwAccumulator": { "opcodes": [ "66", "25" ] }, 540 "OrwAccumulator": { "opcodes": [ "66", "0D" ] }, 541 "SubwAccumulator": { "opcodes": [ "66", "2D" ] }, 542 "XorwAccumulator": { "opcodes": [ "66", "35" ] } 543 }, 544 "args": [ 545 { "class": "AX", "usage": "use_def" }, 546 { "class": "Imm16" }, 547 { "class": "FLAGS", "usage": "def" } 548 ] 549 }, 550 { 551 "encodings": { 552 "AddwImm8": { "opcodes": [ "66", "83", "0" ] }, 553 "AndwImm8": { "opcodes": [ "66", "83", "4" ] }, 554 "OrwImm8": { "opcodes": [ "66", "83", "1" ] }, 555 "Rolw": { "opcodes": [ "66", "C1", "0" ] }, 556 "Rorw": { "opcodes": [ "66", "C1", "1" ] }, 557 "Sarw": { "opcodes": [ "66", "C1", "7" ] }, 558 "Shlw": { "opcodes": [ "66", "C1", "4" ] }, 559 "Shrw": { "opcodes": [ "66", "C1", "5" ] }, 560 "SubwImm8": { "opcodes": [ "66", "83", "5" ] }, 561 "XorwImm8": { "opcodes": [ "66", "83", "6" ] } 562 }, 563 "args": [ 564 { "class": "GeneralReg16/Mem16", "usage": "use_def" }, 565 { "class": "Imm8" }, 566 { "class": "FLAGS", "usage": "def" } 567 ] 568 }, 569 { 570 "encodings": { 571 "Aesimc": { "feature": "AES", "opcodes": [ "66", "0F", "38", "DB" ] }, 572 "Movq": { "opcodes": [ "F3", "0F", "7E" ] }, 573 "Pmovsxbw": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "20" ] }, 574 "Pmovsxdq": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "25" ] }, 575 "Pmovsxwd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "23" ] }, 576 "Pmovzxbw": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "30" ] }, 577 "Pmovzxdq": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "35" ] }, 578 "Pmovzxwd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "33" ] }, 579 "Vaesimc": { "feature": "AESAVX", "opcodes": [ "C4", "02", "01", "DB" ] }, 580 "Vmovq": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "7E" ] } 581 }, 582 "args": [ 583 { "class": "XmmReg", "usage": "def" }, 584 { "class": "XmmReg/VecMem64", "usage": "use" } 585 ], 586 "comment": "Upper bits are zero-filled for Movq/Vmovq" 587 }, 588 { 589 "encodings": { 590 "Aeskeygenassist": { "feature": "AVX", "opcodes": [ "66", "0F", "3A", "DF" ] }, 591 "Pshufd": { "opcodes": [ "66", "0F", "70" ] }, 592 "Pshufhw": { "opcodes": [ "F3", "0F", "70" ] }, 593 "Pshuflw": { "opcodes": [ "F2", "0F", "70" ] }, 594 "Roundpd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "09" ] }, 595 "Roundps": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "08" ] }, 596 "Vaeskeygenassist": { "feature": "AVX", "opcodes": [ "C4", "03", "01", "DF" ] }, 597 "Vpshufd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "70" ] }, 598 "Vpshufhw": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "70" ] }, 599 "Vpshuflw": { "feature": "AVX", "opcodes": [ "C4", "01", "03", "70" ] }, 600 "Vroundpd": { "feature": "AVX", "opcodes": [ "C4", "03", "01", "09" ] }, 601 "Vroundps": { "feature": "AVX", "opcodes": [ "C4", "03", "01", "08" ] } 602 }, 603 "args": [ 604 { "class": "VecReg128", "usage": "def" }, 605 { "class": "VecReg128/VecMem128", "usage": "use" }, 606 { "class": "Imm8" } 607 ] 608 }, 609 { 610 "encodings": { 611 "Andnl": { "feature": "BMI", "opcodes": [ "C4", "02", "00", "F2" ], "type": "vex_rm_to_reg" } 612 }, 613 "args": [ 614 { "class": "GeneralReg32", "usage": "def" }, 615 { "class": "GeneralReg32", "usage": "use" }, 616 { "class": "GeneralReg32/Mem32", "usage": "use" }, 617 { "class": "FLAGS", "usage": "def" } 618 ] 619 }, 620 { 621 "encodings": { 622 "Bextrl": { "feature": "BMI", "opcodes": [ "C4", "02", "00", "F7" ] }, 623 "Bzhil": { "feature": "BMI2", "opcodes": [ "C4", "02", "00", "F5" ] } 624 }, 625 "args": [ 626 { "class": "GeneralReg32", "usage": "def" }, 627 { "class": "GeneralReg32/Mem32", "usage": "use" }, 628 { "class": "GeneralReg32", "usage": "use" }, 629 { "class": "FLAGS", "usage": "def" } 630 ] 631 }, 632 { 633 "encodings": { 634 "Blsil": { "feature": "BMI", "opcodes": [ "C4", "02", "00", "F3", "3" ], "type": "rm_to_vex" }, 635 "Blsmskl": { "feature": "BMI", "opcodes": [ "C4", "02", "00", "F3", "2" ], "type": "rm_to_vex" }, 636 "Blsrl": { "feature": "BMI", "opcodes": [ "C4", "02", "00", "F3", "1" ], "type": "rm_to_vex" }, 637 "Bsfl": { "opcodes": [ "0F", "BC" ] }, 638 "Bsrl": { "opcodes": [ "0F", "BD" ] }, 639 "Lzcntl": { "feature": "LZCNT", "opcodes": [ "F3", "0F", "BD" ] }, 640 "Popcntl": { "feature": "POPCNT", "opcodes": [ "F3", "0F", "B8" ] }, 641 "Tzcntl": { "feature": "BMI", "opcodes": [ "F3", "0F", "BC" ] } 642 }, 643 "args": [ 644 { "class": "GeneralReg32", "usage": "def" }, 645 { "class": "GeneralReg32/Mem32", "usage": "use" }, 646 { "class": "FLAGS", "usage": "def" } 647 ] 648 }, 649 { 650 "encodings": { 651 "Bsfw": { "opcodes": [ "66", "0F", "BC" ] }, 652 "Bsrw": { "opcodes": [ "66", "0F", "BD" ] }, 653 "Lzcntw": { "feature": "LZCNT", "opcodes": [ "66", "F3", "0F", "BD" ] }, 654 "Popcntw": { "feature": "POPCNT", "opcodes": [ "66", "F3", "0F", "B8" ] }, 655 "Tzcntw": { "feature": "BMI", "opcodes": [ "66", "F3", "0F", "BC" ] } 656 }, 657 "args": [ 658 { "class": "GeneralReg16", "usage": "def" }, 659 { "class": "GeneralReg16/Mem16", "usage": "use" }, 660 { "class": "FLAGS", "usage": "def" } 661 ] 662 }, 663 { 664 "encodings": { 665 "Bswapl": { "opcodes": [ "0F", "C8" ] } 666 }, 667 "args": [ 668 { "class": "GeneralReg32", "usage": "use_def" } 669 ] 670 }, 671 { 672 "encodings": { 673 "Btl": { "opcodes": [ "0F", "A3" ], "type": "reg_to_rm" }, 674 "Cmpl": { "opcode": "39", "type": "reg_to_rm", "dependency_breaking": "true" }, 675 "Testl": { "opcode": "85", "type": "reg_to_rm" } 676 }, 677 "args": [ 678 { "class": "GeneralReg32/Mem32", "usage": "use" }, 679 { "class": "GeneralReg32", "usage": "use" }, 680 { "class": "FLAGS", "usage": "def" } 681 ] 682 }, 683 { 684 "encodings": { 685 "Btw": { "opcodes": [ "66", "0F", "A3" ], "type": "reg_to_rm" }, 686 "Cmpw": { "opcodes": [ "66", "39" ], "type": "reg_to_rm" }, 687 "Testw": { "opcodes": [ "66", "85" ], "type": "reg_to_rm" } 688 }, 689 "args": [ 690 { "class": "GeneralReg16/Mem16", "usage": "use" }, 691 { "class": "GeneralReg16", "usage": "use" }, 692 { "class": "FLAGS", "usage": "def" } 693 ] 694 }, 695 { 696 "encodings": { 697 "Call": { "opcodes": [ "FF", "02" ] }, 698 "Push": { "opcode": "50" } 699 }, 700 "args": [ 701 { "class": "RSP", "usage": "use_def" }, 702 { "class": "GeneralReg", "usage": "use" } 703 ] 704 }, 705 { 706 "stems": [ "Call" ], 707 "args": [ 708 { "class": "RSP", "usage": "use_def" }, 709 { "class": "Label" } 710 ] 711 }, 712 { 713 "encodings": { 714 "Cbtw": { "opcodes": [ "66", "98" ] }, 715 "Cbw": { "opcodes": [ "66", "98" ] } 716 }, 717 "args": [ 718 { "class": "AL", "usage": "use" }, 719 { "class": "AX", "usage": "def" } 720 ] 721 }, 722 { 723 "encodings": { 724 "Cdq": { "opcode": "99" }, 725 "Cltd": { "opcode": "99" } 726 }, 727 "args": [ 728 { "class": "EAX", "usage": "use" }, 729 { "class": "EDX", "usage": "def" } 730 ] 731 }, 732 { 733 "encodings": { 734 "Clc": { "opcode": "F8" }, 735 "Cmc": { "opcode": "F5" }, 736 "Stc": { "opcode": "F9" } 737 }, 738 "args": [ 739 { "class": "FLAGS", "usage": "use_def" } 740 ] 741 }, 742 { 743 "encodings": { 744 "Cmovl": { "opcodes": [ "0F", "40" ] } 745 }, 746 "args": [ 747 { "class": "Cond" }, 748 { "class": "GeneralReg32", "usage": "use_def" }, 749 { "class": "GeneralReg32/Mem32", "usage": "use" }, 750 { "class": "FLAGS", "usage": "use" } 751 ] 752 }, 753 { 754 "encodings": { 755 "Cmovw": { "opcodes": [ "66", "0F", "40" ] } 756 }, 757 "args": [ 758 { "class": "Cond" }, 759 { "class": "GeneralReg16", "usage": "use_def" }, 760 { "class": "GeneralReg16/Mem16", "usage": "use" }, 761 { "class": "FLAGS", "usage": "use" } 762 ] 763 }, 764 { 765 "encodings": { 766 "CmpXchg8b": { "opcodes": [ "0F", "C7", "1" ] }, 767 "Lock CmpXchg8b": { "opcodes": [ "F0", "0F", "C7", "1" ] } 768 }, 769 "args": [ 770 { "class": "EAX", "usage": "use_def" }, 771 { "class": "EDX", "usage": "use_def" }, 772 { "class": "EBX", "usage": "use" }, 773 { "class": "ECX", "usage": "use" }, 774 { "class": "VecMem64", "usage": "use_def" }, 775 { "class": "FLAGS", "usage": "def" } 776 ] 777 }, 778 { 779 "encodings": { 780 "CmpXchgl": { "opcodes": [ "0F", "B1" ], "type": "reg_to_rm" } 781 }, 782 "args": [ 783 { "class": "EAX", "usage": "use_def" }, 784 { "class": "GeneralReg32/Mem32", "usage": "use_def" }, 785 { "class": "GeneralReg32", "usage": "use" }, 786 { "class": "FLAGS", "usage": "def" } 787 ] 788 }, 789 { 790 "encodings": { 791 "Cmpb": { "opcode": "38", "type": "reg_to_rm" }, 792 "Testb": { "opcode": "84", "type": "reg_to_rm" } 793 }, 794 "args": [ 795 { "class": "GeneralReg8/Mem8", "usage": "use" }, 796 { "class": "GeneralReg8", "usage": "use" }, 797 { "class": "FLAGS", "usage": "def" } 798 ] 799 }, 800 { 801 "encodings": { 802 "Cmpb": { "opcodes": [ "80", "7" ] }, 803 "Testb": { "opcodes": [ "F6", "0" ] } 804 }, 805 "args": [ 806 { "class": "GeneralReg8/Mem8", "usage": "use" }, 807 { "class": "Imm8" }, 808 { "class": "FLAGS", "usage": "def" } 809 ] 810 }, 811 { 812 "encodings": { 813 "Cmpb": { "opcode": "3A" } 814 }, 815 "args": [ 816 { "class": "GeneralReg8", "usage": "use" }, 817 { "class": "Mem8", "usage": "use" }, 818 { "class": "FLAGS", "usage": "def" } 819 ] 820 }, 821 { 822 "encodings": { 823 "CmpbAccumulator": { "opcode": "3C" }, 824 "TestbAccumulator": { "opcode": "A8" } 825 }, 826 "args": [ 827 { "class": "AL", "usage": "use" }, 828 { "class": "Imm8" }, 829 { "class": "FLAGS", "usage": "def" } 830 ] 831 }, 832 { 833 "encodings": { 834 "Cmpl": { "opcodes": [ "81", "7" ] }, 835 "Testl": { "opcodes": [ "F7", "0" ] } 836 }, 837 "args": [ 838 { "class": "GeneralReg32/Mem32", "usage": "use" }, 839 { "class": "Imm32" }, 840 { "class": "FLAGS", "usage": "def" } 841 ] 842 }, 843 { 844 "encodings": { 845 "Cmpl": { "opcode": "3B" } 846 }, 847 "args": [ 848 { "class": "GeneralReg32", "usage": "use" }, 849 { "class": "Mem32", "usage": "use" }, 850 { "class": "FLAGS", "usage": "def" } 851 ] 852 }, 853 { 854 "encodings": { 855 "CmplAccumulator": { "opcode": "3D" }, 856 "TestlAccumulator": { "opcode": "A9" } 857 }, 858 "args": [ 859 { "class": "EAX", "usage": "use" }, 860 { "class": "Imm32" }, 861 { "class": "FLAGS", "usage": "def" } 862 ] 863 }, 864 { 865 "encodings": { 866 "CmplImm8": { "opcodes": [ "83", "7" ] } 867 }, 868 "args": [ 869 { "class": "GeneralReg32/Mem32", "usage": "use" }, 870 { "class": "Imm8" }, 871 { "class": "FLAGS", "usage": "def" } 872 ] 873 }, 874 { 875 "encodings": { 876 "Cmpw": { "opcodes": [ "66", "81", "7" ] }, 877 "Testw": { "opcodes": [ "66", "F7", "0" ] } 878 }, 879 "args": [ 880 { "class": "GeneralReg16/Mem16", "usage": "use" }, 881 { "class": "Imm16" }, 882 { "class": "FLAGS", "usage": "def" } 883 ] 884 }, 885 { 886 "encodings": { 887 "Cmpw": { "opcodes": [ "66", "3B" ] } 888 }, 889 "args": [ 890 { "class": "GeneralReg16", "usage": "use" }, 891 { "class": "Mem16", "usage": "use" }, 892 { "class": "FLAGS", "usage": "def" } 893 ] 894 }, 895 { 896 "encodings": { 897 "CmpwAccumulator": { "opcodes": [ "66", "3D" ] }, 898 "TestwAccumulator": { "opcodes": [ "66", "A9" ] } 899 }, 900 "args": [ 901 { "class": "AX", "usage": "use" }, 902 { "class": "Imm16" }, 903 { "class": "FLAGS", "usage": "def" } 904 ] 905 }, 906 { 907 "encodings": { 908 "CmpwImm8": { "opcodes": [ "66", "83", "7" ] } 909 }, 910 "args": [ 911 { "class": "GeneralReg16/Mem16", "usage": "use" }, 912 { "class": "Imm8" }, 913 { "class": "FLAGS", "usage": "def" } 914 ] 915 }, 916 { 917 "encodings": { 918 "Cvtdq2pd": { "opcodes": [ "F3", "0F", "E6" ] }, 919 "Cvtdq2ps": { "opcodes": [ "0F", "5B" ] }, 920 "Cvtpd2dq": { "opcodes": [ "F2", "0F", "E6" ] }, 921 "Cvtpd2ps": { "opcodes": [ "66", "0F", "5A" ] }, 922 "Cvtps2dq": { "opcodes": [ "66", "0F", "5B" ] }, 923 "Cvtps2pd": { "opcodes": [ "0F", "5A" ] }, 924 "Cvttpd2dq": { "opcodes": [ "66", "0F", "E6" ] }, 925 "Cvttps2dq": { "opcodes": [ "F3", "0F", "5B" ] }, 926 "Vcvtdq2pd": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "E6" ] }, 927 "Vcvtdq2ps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "5B" ] }, 928 "Vcvtpd2dq": { "feature": "AVX", "opcodes": [ "C4", "01", "03", "E6" ] }, 929 "Vcvtpd2dqx": { 930 "comment": [ 931 "Suffix “x” used to distingush 128bit memory operand from 256bit memory operand", 932 "This is common convention for assemblers that use AT&T syntax" 933 ], 934 "feature": "AVX", 935 "opcodes": [ "C4", "01", "03", "E6" ] 936 }, 937 "Vcvtpd2ps": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "5A" ] }, 938 "Vcvtpd2psx": { 939 "comment": [ 940 "Suffix “x” used to distingush 128bit memory operand from 256bit memory operand", 941 "This is common convention for assemblers that use AT&T syntax" 942 ], 943 "feature": "AVX", 944 "opcodes": [ "C4", "01", "01", "5A" ] 945 }, 946 "Vcvtph2ps": { "feature": "F16C", "opcodes": [ "C4", "02", "01", "13" ] }, 947 "Vcvtps2dq": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "5B" ] }, 948 "Vcvtps2pd": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "5A" ] }, 949 "Vcvttpd2dq": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "E6" ] }, 950 "Vcvttpd2dqx": { 951 "comment": [ 952 "Suffix “x” used to distingush 128bit memory operand from 256bit memory operand", 953 "This is common convention for assemblers that use AT&T syntax" 954 ], 955 "feature": "AVX", 956 "opcodes": [ "C4", "01", "01", "E6" ] 957 }, 958 "Vcvttps2dq": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "5B" ] } 959 }, 960 "args": [ 961 { "class": "VecReg128", "usage": "def" }, 962 { "class": "VecReg128/VecMem128", "usage": "use" } 963 ] 964 }, 965 { 966 "encodings": { 967 "Cvtsd2sil": { "opcodes": [ "F2", "0F", "2D" ] }, 968 "Cvttsd2sil": { "opcodes": [ "F2", "0F", "2C" ] }, 969 "Vcvtsd2sil": { "feature": "AVX", "opcodes": [ "C4", "01", "03", "2D" ] }, 970 "Vcvttsd2sil": { "feature": "AVX", "opcodes": [ "C4", "01", "03", "2C" ] } 971 }, 972 "args": [ 973 { "class": "GeneralReg32", "usage": "def" }, 974 { "class": "FpReg64/VecMem64", "usage": "use" } 975 ] 976 }, 977 { 978 "encodings": { 979 "Cvtsd2ss": { "opcodes": [ "F2", "0F", "5A" ] } 980 }, 981 "args": [ 982 { "class": "FpReg32", "usage": "def" }, 983 { "class": "FpReg64/VecMem64", "usage": "use" } 984 ] 985 }, 986 { 987 "encodings": { 988 "Cvtsi2sdl": { "opcodes": [ "F2", "0F", "2A" ] } 989 }, 990 "args": [ 991 { "class": "FpReg64", "usage": "def" }, 992 { "class": "GeneralReg32/Mem32", "usage": "use" } 993 ] 994 }, 995 { 996 "encodings": { 997 "Cvtsi2ssl": { "opcodes": [ "F3", "0F", "2A" ] } 998 }, 999 "args": [ 1000 { "class": "FpReg32", "usage": "def" }, 1001 { "class": "GeneralReg32/Mem32", "usage": "use" } 1002 ] 1003 }, 1004 { 1005 "encodings": { 1006 "Cvtss2sd": { "opcodes": [ "F3", "0F", "5A" ] } 1007 }, 1008 "args": [ 1009 { "class": "FpReg64", "usage": "def" }, 1010 { "class": "FpReg32/VecMem32", "usage": "use" } 1011 ] 1012 }, 1013 { 1014 "encodings": { 1015 "Cvtss2sil": { "opcodes": [ "F3", "0F", "2D" ] }, 1016 "Cvttss2sil": { "opcodes": [ "F3", "0F", "2C" ] }, 1017 "Vcvtss2sil": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "2D" ] }, 1018 "Vcvttss2sil": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "2C" ] } 1019 }, 1020 "args": [ 1021 { "class": "GeneralReg32", "usage": "def" }, 1022 { "class": "FpReg32/VecMem32", "usage": "use" } 1023 ] 1024 }, 1025 { 1026 "encodings": { 1027 "Cwd": { "opcodes": [ "66", "99" ] }, 1028 "Cwtd": { "opcodes": [ "66", "99" ] } 1029 }, 1030 "args": [ 1031 { "class": "AX", "usage": "use" }, 1032 { "class": "DX", "usage": "def" } 1033 ] 1034 }, 1035 { 1036 "encodings": { 1037 "Cwde": { "opcode": "98" }, 1038 "Cwtl": { "opcode": "98" } 1039 }, 1040 "args": [ 1041 { "class": "AX", "usage": "use" }, 1042 { "class": "EAX", "usage": "def" } 1043 ] 1044 }, 1045 { 1046 "encodings": { 1047 "Decb": { "opcodes": [ "FE", "1" ] }, 1048 "Incb": { "opcodes": [ "FE", "0" ] }, 1049 "Negb": { "opcodes": [ "F6", "3" ] }, 1050 "RolbByOne": { "opcodes": [ "D0", "0" ] }, 1051 "RorbByOne": { "opcodes": [ "D0", "1" ] }, 1052 "SarbByOne": { "opcodes": [ "D0", "7" ] }, 1053 "ShlbByOne": { "opcodes": [ "D0", "4" ] }, 1054 "ShrbByOne": { "opcodes": [ "D0", "5" ] } 1055 }, 1056 "args": [ 1057 { "class": "GeneralReg8/Mem8", "usage": "use_def" }, 1058 { "class": "FLAGS", "usage": "def" } 1059 ] 1060 }, 1061 { 1062 "encodings": { 1063 "Decl": { "opcodes": [ "FF", "1" ] }, 1064 "Incl": { "opcodes": [ "FF", "0" ] } 1065 }, 1066 "args": [ 1067 { "class": "Mem32", "usage": "use_def" }, 1068 { "class": "FLAGS", "usage": "def" } 1069 ] 1070 }, 1071 { 1072 "encodings": { 1073 "Decw": { "opcodes": [ "66", "FF", "1" ] }, 1074 "Incw": { "opcodes": [ "66", "FF", "0" ] } 1075 }, 1076 "args": [ 1077 { "class": "Mem16", "usage": "use_def" }, 1078 { "class": "FLAGS", "usage": "def" } 1079 ] 1080 }, 1081 { 1082 "encodings": { 1083 "Divb": { "opcodes": [ "F6", "6" ] }, 1084 "Idivb": { "opcodes": [ "F6", "7" ] } 1085 }, 1086 "args": [ 1087 { "class": "AX", "usage": "use_def" }, 1088 { "class": "GeneralReg8/Mem8", "usage": "use" }, 1089 { "class": "FLAGS", "usage": "def" } 1090 ] 1091 }, 1092 { 1093 "encodings": { 1094 "Divl": { "opcodes": [ "F7", "6" ] }, 1095 "Idivl": { "opcodes": [ "F7", "7" ] } 1096 }, 1097 "args": [ 1098 { "class": "EAX", "usage": "use_def" }, 1099 { "class": "EDX", "usage": "use_def" }, 1100 { "class": "GeneralReg32/Mem32", "usage": "use" }, 1101 { "class": "FLAGS", "usage": "def" } 1102 ] 1103 }, 1104 { 1105 "encodings": { 1106 "Divw": { "opcodes": [ "66", "F7", "6" ] }, 1107 "Idivw": { "opcodes": [ "66", "F7", "7" ] } 1108 }, 1109 "args": [ 1110 { "class": "AX", "usage": "use_def" }, 1111 { "class": "DX", "usage": "use_def" }, 1112 { "class": "GeneralReg16/Mem16", "usage": "use" }, 1113 { "class": "FLAGS", "usage": "def" } 1114 ] 1115 }, 1116 { 1117 "encodings": { 1118 "F2xm1": { "opcodes": [ "D9", "F0" ] }, 1119 "Fabs": { "opcodes": [ "D9", "E1" ] }, 1120 "Fchs": { "opcodes": [ "D9", "E0" ] }, 1121 "Fcos": { "opcodes": [ "D9", "FF" ] }, 1122 "Fld1": { "opcodes": [ "D9", "E8" ] }, 1123 "Fldl2e": { "opcodes": [ "D9", "EA" ] }, 1124 "Fldl2t": { "opcodes": [ "D9", "E9" ] }, 1125 "Fldlg2": { "opcodes": [ "D9", "EC" ] }, 1126 "Fldln2": { "opcodes": [ "D9", "ED" ] }, 1127 "Fldpi": { "opcodes": [ "D9", "EB" ] }, 1128 "Fldz": { "opcodes": [ "D9", "EE" ] }, 1129 "Frndint": { "opcodes": [ "D9", "FC" ] }, 1130 "Fscale": { "opcodes": [ "D9", "FD" ] }, 1131 "Fsin": { "opcodes": [ "D9", "FE" ] }, 1132 "Fsqrt": { "opcodes": [ "D9", "FA" ] }, 1133 "Ftst": { "opcodes": [ "D9", "E4" ] } 1134 }, 1135 "args": [ 1136 { "class": "ST", "usage": "use_def" } 1137 ] 1138 }, 1139 { 1140 "encodings": { 1141 "FaddFromSt": { "opcodes": [ "DC", "0" ] }, 1142 "FaddpFromSt": { "opcodes": [ "DE", "0" ] }, 1143 "FdivFromSt": { "opcodes": [ "DC", "6" ] }, 1144 "FdivpFromSt": { "opcodes": [ "DE", "6" ] }, 1145 "FdivrFromSt": { "opcodes": [ "DC", "7" ] }, 1146 "FdivrpFromSt": { "opcodes": [ "DE", "7" ] }, 1147 "FmulFromSt": { "opcodes": [ "DC", "1" ] }, 1148 "FmulpFromSt": { "opcodes": [ "DE", "1" ] }, 1149 "FsubFromSt": { "opcodes": [ "DC", "4" ] }, 1150 "FsubpFromSt": { "opcodes": [ "DE", "4" ] }, 1151 "FsubrFromSt": { "opcodes": [ "DC", "5" ] }, 1152 "FsubrpFromSt": { "opcodes": [ "DE", "5" ] } 1153 }, 1154 "args": [ 1155 { "class": "RegX87", "usage": "use_def" }, 1156 { "class": "ST", "usage": "use" } 1157 ] 1158 }, 1159 { 1160 "encodings": { 1161 "FaddToSt": { "opcodes": [ "D8", "0" ] }, 1162 "FdivToSt": { "opcodes": [ "D8", "6" ] }, 1163 "FdivrToSt": { "opcodes": [ "D8", "7" ] }, 1164 "FmulToSt": { "opcodes": [ "D8", "1" ] }, 1165 "FsubToSt": { "opcodes": [ "D8", "4" ] }, 1166 "FsubrToSt": { "opcodes": [ "D8", "5" ] } 1167 }, 1168 "args": [ 1169 { "class": "ST", "usage": "use_def" }, 1170 { "class": "RegX87", "usage": "use" } 1171 ] 1172 }, 1173 { 1174 "encodings": { 1175 "Faddl": { "opcodes": [ "DC", "0" ] }, 1176 "Fdivl": { "opcodes": [ "DC", "6" ] }, 1177 "Fdivrl": { "opcodes": [ "DC", "7" ] }, 1178 "Fmull": { "opcodes": [ "DC", "1" ] }, 1179 "Fsubl": { "opcodes": [ "DC", "4" ] }, 1180 "Fsubrl": { "opcodes": [ "DC", "5" ] } 1181 }, 1182 "args": [ 1183 { "class": "ST", "usage": "use_def" }, 1184 { "class": "MemX8764", "usage": "use" } 1185 ] 1186 }, 1187 { 1188 "encodings": { 1189 "Fadds": { "opcodes": [ "D8", "0" ] }, 1190 "Fdivrs": { "opcodes": [ "D8", "7" ] }, 1191 "Fdivs": { "opcodes": [ "D8", "6" ] }, 1192 "Fiaddl": { "opcodes": [ "DA", "0" ] }, 1193 "Fidivl": { "opcodes": [ "DA", "6" ] }, 1194 "Fidivrl": { "opcodes": [ "DA", "7" ] }, 1195 "Fimull": { "opcodes": [ "DA", "1" ] }, 1196 "Fisubl": { "opcodes": [ "DA", "4" ] }, 1197 "Fisubrl": { "opcodes": [ "DA", "5" ] }, 1198 "Fmuls": { "opcodes": [ "D8", "1" ] }, 1199 "Fsubrs": { "opcodes": [ "D8", "5" ] }, 1200 "Fsubs": { "opcodes": [ "D8", "4" ] } 1201 }, 1202 "args": [ 1203 { "class": "ST", "usage": "use_def" }, 1204 { "class": "MemX8732", "usage": "use" } 1205 ] 1206 }, 1207 { 1208 "encodings": { 1209 "Fbld": { "opcodes": [ "DF", "4" ] }, 1210 "Fldt": { "opcodes": [ "DB", "5" ] } 1211 }, 1212 "args": [ 1213 { "class": "ST", "usage": "def" }, 1214 { "class": "MemX8780", "usage": "use" } 1215 ] 1216 }, 1217 { 1218 "encodings": { 1219 "Fbstp": { "opcodes": [ "DF", "6" ] }, 1220 "Fstpt": { "opcodes": [ "DB", "7" ] } 1221 }, 1222 "args": [ 1223 { "class": "MemX8780", "usage": "def" }, 1224 { "class": "ST", "usage": "use" } 1225 ] 1226 }, 1227 { 1228 "encodings": { 1229 "FcmovbToSt": { "opcodes": [ "DA", "0" ] }, 1230 "FcmovbeToSt": { "opcodes": [ "DA", "2" ] }, 1231 "FcmoveToSt": { "opcodes": [ "DA", "1" ] }, 1232 "FcmovnbToSt": { "opcodes": [ "DB", "0" ] }, 1233 "FcmovnbeToSt": { "opcodes": [ "DB", "2" ] }, 1234 "FcmovneToSt": { "opcodes": [ "DB", "1" ] }, 1235 "FcmovnuToSt": { "opcodes": [ "DB", "3" ] }, 1236 "FcmovuToSt": { "opcodes": [ "DA", "3" ] } 1237 }, 1238 "args": [ 1239 { "class": "ST", "usage": "use_def" }, 1240 { "class": "RegX87", "usage": "use" }, 1241 { "class": "FLAGS", "usage": "use" } 1242 ] 1243 }, 1244 { 1245 "encodings": { 1246 "Fcom": { "opcodes": [ "D8", "2" ] }, 1247 "Fcomp": { "opcodes": [ "D8", "3" ] }, 1248 "Fucom": { "opcodes": [ "DD", "4" ] }, 1249 "Fucomp": { "opcodes": [ "DD", "5" ] } 1250 }, 1251 "args": [ 1252 { "class": "ST", "usage": "use" }, 1253 { "class": "RegX87", "usage": "use" }, 1254 { "class": "CC", "usage": "def" } 1255 ] 1256 }, 1257 { 1258 "encodings": { 1259 "Fcomi": { "opcodes": [ "DB", "6" ] }, 1260 "Fcomip": { "opcodes": [ "DF", "6" ] }, 1261 "Fucomi": { "opcodes": [ "DB", "5" ] }, 1262 "Fucomip": { "opcodes": [ "DF", "5" ] } 1263 }, 1264 "args": [ 1265 { "class": "ST", "usage": "use" }, 1266 { "class": "RegX87", "usage": "use" }, 1267 { "class": "FLAGS", "usage": "def" } 1268 ] 1269 }, 1270 { 1271 "encodings": { 1272 "Fcoml": { "opcodes": [ "DC", "2" ] }, 1273 "Fcompl": { "opcodes": [ "DC", "3" ] } 1274 }, 1275 "args": [ 1276 { "class": "ST", "usage": "use" }, 1277 { "class": "MemX8764", "usage": "use" }, 1278 { "class": "CC", "usage": "def" } 1279 ] 1280 }, 1281 { 1282 "encodings": { 1283 "Fcompp": { "opcodes": [ "DE", "D9" ] }, 1284 "Fucompp": { "opcodes": [ "DA", "E9" ] } 1285 }, 1286 "args": [ 1287 { "class": "ST", "usage": "use" }, 1288 { "class": "ST1", "usage": "use" }, 1289 { "class": "CC", "usage": "def" } 1290 ] 1291 }, 1292 { 1293 "encodings": { 1294 "Fcomps": { "opcodes": [ "D8", "3" ] }, 1295 "Fcoms": { "opcodes": [ "D8", "2" ] }, 1296 "Ficoml": { "opcodes": [ "DA", "2" ] }, 1297 "Ficompl": { "opcodes": [ "DA", "3" ] } 1298 }, 1299 "args": [ 1300 { "class": "ST", "usage": "use" }, 1301 { "class": "MemX8732", "usage": "use" }, 1302 { "class": "CC", "usage": "def" } 1303 ] 1304 }, 1305 { 1306 "encodings": { 1307 "Fdecstp": { "opcodes": [ "D9", "F6" ] }, 1308 "Fincstp": { "opcodes": [ "D9", "F7" ] }, 1309 "Fnop": { "opcodes": [ "D9", "D0" ] }, 1310 "Fwait": { "opcode": "9B" }, 1311 "Int3": { "opcode": "CC" }, 1312 "Lfence": { "opcodes": [ "0F", "AE", "E8" ] }, 1313 "Mfence": { "opcodes": [ "0F", "AE", "F0" ] }, 1314 "Nop": { "opcode": "90" }, 1315 "Sfence": { "opcodes": [ "0F", "AE", "F8" ] }, 1316 "UD2": { "opcodes": [ "0F", "0B" ] }, 1317 "Wait": { "opcode": "9B" } 1318 }, 1319 "args": [] 1320 }, 1321 { 1322 "encodings": { 1323 "Ffree": { "opcodes": [ "DD", "0" ] } 1324 }, 1325 "args": [ 1326 { "class": "RegX87", "usage": "use" } 1327 ] 1328 }, 1329 { 1330 "encodings": { 1331 "Fiadds": { "opcodes": [ "DE", "0" ] }, 1332 "Fidivrs": { "opcodes": [ "DE", "7" ] }, 1333 "Fidivs": { "opcodes": [ "DE", "6" ] }, 1334 "Fimuls": { "opcodes": [ "DE", "1" ] }, 1335 "Fisubrs": { "opcodes": [ "DE", "5" ] }, 1336 "Fisubs": { "opcodes": [ "DE", "4" ] } 1337 }, 1338 "args": [ 1339 { "class": "ST", "usage": "use_def" }, 1340 { "class": "MemX8716", "usage": "use" } 1341 ] 1342 }, 1343 { 1344 "encodings": { 1345 "Ficomps": { "opcodes": [ "DE", "3" ] }, 1346 "Ficoms": { "opcodes": [ "DE", "2" ] } 1347 }, 1348 "args": [ 1349 { "class": "ST", "usage": "use" }, 1350 { "class": "MemX8716", "usage": "use" }, 1351 { "class": "CC", "usage": "def" } 1352 ] 1353 }, 1354 { 1355 "encodings": { 1356 "Fildl": { "opcodes": [ "DB", "0" ] }, 1357 "Flds": { "opcodes": [ "D9", "0" ] } 1358 }, 1359 "args": [ 1360 { "class": "ST", "usage": "def" }, 1361 { "class": "MemX8732", "usage": "use" } 1362 ] 1363 }, 1364 { 1365 "encodings": { 1366 "Fildll": { "opcodes": [ "DF", "5" ] }, 1367 "Fldl": { "opcodes": [ "DD", "0" ] } 1368 }, 1369 "args": [ 1370 { "class": "ST", "usage": "def" }, 1371 { "class": "MemX8764", "usage": "use" } 1372 ] 1373 }, 1374 { 1375 "encodings": { 1376 "Filds": { "opcodes": [ "DF", "0" ] } 1377 }, 1378 "args": [ 1379 { "class": "ST", "usage": "def" }, 1380 { "class": "MemX8716", "usage": "use" } 1381 ] 1382 }, 1383 { 1384 "encodings": { 1385 "Fistl": { "opcodes": [ "DB", "2" ] }, 1386 "Fistpl": { "opcodes": [ "DB", "3" ] }, 1387 "Fisttpl": { "feature": "SSE3", "opcodes": [ "DB", "1" ] }, 1388 "Fstps": { "opcodes": [ "D9", "3" ] }, 1389 "Fsts": { "opcodes": [ "D9", "2" ] } 1390 }, 1391 "args": [ 1392 { "class": "MemX8732", "usage": "def" }, 1393 { "class": "ST", "usage": "use" } 1394 ] 1395 }, 1396 { 1397 "encodings": { 1398 "Fistpll": { "opcodes": [ "DF", "7" ] }, 1399 "Fisttpll": { "feature": "SSE3", "opcodes": [ "DD", "1" ] }, 1400 "Fstl": { "opcodes": [ "DD", "2" ] }, 1401 "Fstpl": { "opcodes": [ "DD", "3" ] } 1402 }, 1403 "args": [ 1404 { "class": "MemX8764", "usage": "def" }, 1405 { "class": "ST", "usage": "use" } 1406 ] 1407 }, 1408 { 1409 "encodings": { 1410 "Fistps": { "opcodes": [ "DF", "3" ] }, 1411 "Fists": { "opcodes": [ "DF", "2" ] }, 1412 "Fisttps": { "feature": "SSE3", "opcodes": [ "DF", "1" ] } 1413 }, 1414 "args": [ 1415 { "class": "MemX8716", "usage": "def" }, 1416 { "class": "ST", "usage": "use" } 1417 ] 1418 }, 1419 { 1420 "encodings": { 1421 "Fld": { "opcodes": [ "D9", "0" ] } 1422 }, 1423 "args": [ 1424 { "class": "ST", "usage": "def" }, 1425 { "class": "RegX87", "usage": "use" } 1426 ] 1427 }, 1428 { 1429 "encodings": { 1430 "Fldcw": { "opcodes": [ "D9", "5" ] } 1431 }, 1432 "args": [ 1433 { "class": "CC", "usage": "def" }, 1434 { "class": "MemX8732", "usage": "use" } 1435 ] 1436 }, 1437 { 1438 "encodings": { 1439 "Fldenv": { "opcodes": [ "D9", "4" ] }, 1440 "Frstor": { "opcodes": [ "DD", "4" ] }, 1441 "Fxrstor": { "opcodes": [ "0F", "AE", "1" ] } 1442 }, 1443 "args": [ 1444 { "class": "MemX87", "usage": "use" }, 1445 { "class": "CC", "usage": "def" } 1446 ] 1447 }, 1448 { 1449 "encodings": { 1450 "Fnclex": { "opcodes": [ "DB", "E2" ] }, 1451 "Fndisi": { "opcodes": [ "DB", "E1" ] }, 1452 "Fneni": { "opcodes": [ "DB", "E0" ] }, 1453 "Fninit": { "opcodes": [ "DB", "E3" ] }, 1454 "Fnsetpm": { "opcodes": [ "DB", "E4" ] } 1455 }, 1456 "args": [ 1457 { "class": "CC", "usage": "def" } 1458 ] 1459 }, 1460 { 1461 "encodings": { 1462 "Fnsave": { "opcodes": [ "DD", "6" ] }, 1463 "Fnstenv": { "opcodes": [ "D9", "6" ] }, 1464 "Fxsave": { "opcodes": [ "0F", "AE", "0" ] } 1465 }, 1466 "args": [ 1467 { "class": "CC", "usage": "def" }, 1468 { "class": "MemX87", "usage": "use" } 1469 ] 1470 }, 1471 { 1472 "encodings": { 1473 "Fnstcw": { "opcodes": [ "D9", "7" ] } 1474 }, 1475 "args": [ 1476 { "class": "MemX8732", "usage": "def" }, 1477 { "class": "CC", "usage": "use" } 1478 ] 1479 }, 1480 { 1481 "encodings": { 1482 "Fnstsw": { "opcodes": [ "DF", "E0" ] } 1483 }, 1484 "args": [ 1485 { "class": "AX", "usage": "def" }, 1486 { "class": "SW", "usage": "use" } 1487 ] 1488 }, 1489 { 1490 "encodings": { 1491 "Fnstsw": { "opcodes": [ "DD", "7" ] } 1492 }, 1493 "args": [ 1494 { "class": "MemX8732", "usage": "def" }, 1495 { "class": "SW", "usage": "use" } 1496 ] 1497 }, 1498 { 1499 "encodings": { 1500 "Fpatan": { "opcodes": [ "D9", "F3" ] }, 1501 "Fprem": { "opcodes": [ "D9", "F8" ] }, 1502 "Fprem1": { "opcodes": [ "D9", "F5" ] }, 1503 "Fyl2x": { "opcodes": [ "D9", "F1" ] }, 1504 "Fyl2xp1": { "opcodes": [ "D9", "F9" ] } 1505 }, 1506 "args": [ 1507 { "class": "ST", "usage": "use_def" }, 1508 { "class": "ST1", "usage": "use" } 1509 ] 1510 }, 1511 { 1512 "encodings": { 1513 "Fptan": { "opcodes": [ "D9", "F2" ] }, 1514 "Fsincos": { "opcodes": [ "D9", "FB" ] }, 1515 "Fxtract": { "opcodes": [ "D9", "F4" ] } 1516 }, 1517 "args": [ 1518 { "class": "ST", "usage": "use_def" }, 1519 { "class": "ST1", "usage": "def" } 1520 ] 1521 }, 1522 { 1523 "encodings": { 1524 "Fst": { "opcodes": [ "DD", "2" ] }, 1525 "Fstp": { "opcodes": [ "DD", "3" ] } 1526 }, 1527 "args": [ 1528 { "class": "RegX87", "usage": "def" }, 1529 { "class": "ST", "usage": "use" } 1530 ] 1531 }, 1532 { 1533 "encodings": { 1534 "Fxam": { "opcodes": [ "D9", "E5" ] } 1535 }, 1536 "args": [ 1537 { "class": "ST", "usage": "use" }, 1538 { "class": "CC", "usage": "def" } 1539 ] 1540 }, 1541 { 1542 "encodings": { 1543 "Fxch": { "opcodes": [ "D9", "1" ] } 1544 }, 1545 "args": [ 1546 { "class": "RegX87", "usage": "use_def" }, 1547 { "class": "ST", "usage": "use_def" } 1548 ] 1549 }, 1550 { 1551 "encodings": { 1552 "Imulb": { "opcodes": [ "F6", "5" ] }, 1553 "Mulb": { "opcodes": [ "F6", "4" ] } 1554 }, 1555 "args": [ 1556 { "class": "AL", "usage": "use" }, 1557 { "class": "AX", "usage": "def" }, 1558 { "class": "GeneralReg8/Mem8", "usage": "use" }, 1559 { "class": "FLAGS", "usage": "def" } 1560 ] 1561 }, 1562 { 1563 "encodings": { 1564 "Imull": { "opcodes": [ "F7", "5" ] }, 1565 "Mull": { "opcodes": [ "F7", "4" ] } 1566 }, 1567 "args": [ 1568 { "class": "EAX", "usage": "use_def" }, 1569 { "class": "EDX", "usage": "def" }, 1570 { "class": "GeneralReg32/Mem32", "usage": "use" }, 1571 { "class": "FLAGS", "usage": "def" } 1572 ] 1573 }, 1574 { 1575 "encodings": { 1576 "Imull": { "opcode": "69" } 1577 }, 1578 "args": [ 1579 { "class": "GeneralReg32", "usage": "def" }, 1580 { "class": "GeneralReg32/Mem32", "usage": "use" }, 1581 { "class": "Imm32" }, 1582 { "class": "FLAGS", "usage": "def" } 1583 ] 1584 }, 1585 { 1586 "encodings": { 1587 "Imull": { "opcodes": [ "0F", "AF" ] } 1588 }, 1589 "args": [ 1590 { "class": "GeneralReg32", "usage": "use_def" }, 1591 { "class": "GeneralReg32/Mem32", "usage": "use" }, 1592 { "class": "FLAGS", "usage": "def" } 1593 ] 1594 }, 1595 { 1596 "encodings": { 1597 "ImullImm8": { "opcode": "6B" } 1598 }, 1599 "args": [ 1600 { "class": "GeneralReg32", "usage": "def" }, 1601 { "class": "GeneralReg32/Mem32", "usage": "use" }, 1602 { "class": "Imm8" }, 1603 { "class": "FLAGS", "usage": "def" } 1604 ] 1605 }, 1606 { 1607 "encodings": { 1608 "Imulw": { "opcodes": [ "66", "F7", "5" ] }, 1609 "Mulw": { "opcodes": [ "66", "F7", "4" ] } 1610 }, 1611 "args": [ 1612 { "class": "AX", "usage": "use_def" }, 1613 { "class": "DX", "usage": "def" }, 1614 { "class": "GeneralReg16/Mem16", "usage": "use" }, 1615 { "class": "FLAGS", "usage": "def" } 1616 ] 1617 }, 1618 { 1619 "encodings": { 1620 "Imulw": { "opcodes": [ "66", "69" ] } 1621 }, 1622 "args": [ 1623 { "class": "GeneralReg16", "usage": "def" }, 1624 { "class": "GeneralReg16/Mem16", "usage": "use" }, 1625 { "class": "Imm16" }, 1626 { "class": "FLAGS", "usage": "def" } 1627 ] 1628 }, 1629 { 1630 "encodings": { 1631 "Imulw": { "opcodes": [ "66", "0F", "AF" ] } 1632 }, 1633 "args": [ 1634 { "class": "GeneralReg16", "usage": "use_def" }, 1635 { "class": "GeneralReg16/Mem16", "usage": "use" }, 1636 { "class": "FLAGS", "usage": "def" } 1637 ] 1638 }, 1639 { 1640 "encodings": { 1641 "ImulwImm8": { "opcodes": [ "66", "6B" ] } 1642 }, 1643 "args": [ 1644 { "class": "GeneralReg16", "usage": "def" }, 1645 { "class": "GeneralReg16/Mem16", "usage": "use" }, 1646 { "class": "Imm8" }, 1647 { "class": "FLAGS", "usage": "def" } 1648 ] 1649 }, 1650 { 1651 "stems": [ "Jcc" ], 1652 "args": [ 1653 { "class": "Cond" }, 1654 { "class": "Label" }, 1655 { "class": "FLAGS", "usage": "use" } 1656 ] 1657 }, 1658 { 1659 "encodings": { 1660 "Jmp": { "opcodes": [ "FF", "4" ] } 1661 }, 1662 "args": [ 1663 { "class": "GeneralReg", "usage": "use" } 1664 ] 1665 }, 1666 { 1667 "stems": [ "Jmp" ], 1668 "args": [ 1669 { "class": "Label" } 1670 ] 1671 }, 1672 { 1673 "encodings": { 1674 "Lahf": { "opcode": "9F" } 1675 }, 1676 "args": [ 1677 { "class": "EAX", "usage": "use_def" }, 1678 { "class": "FLAGS", "usage": "use" } 1679 ], 1680 "comment": "Use use_def below because LAHF writes to AH while preserving the rest of RAX" 1681 }, 1682 { 1683 "encodings": { 1684 "Ldmxcsr": { "opcodes": [ "0F", "AE", "2" ] }, 1685 "Vldmxcsr": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "AE", "2" ] } 1686 }, 1687 "args": [ 1688 { "class": "Mem32", "usage": "use" } 1689 ] 1690 }, 1691 { 1692 "encodings": { 1693 "Leal": { "opcode": "8D" } 1694 }, 1695 "args": [ 1696 { "class": "GeneralReg32", "usage": "def" }, 1697 { "class": "Mem", "usage": "use" } 1698 ] 1699 }, 1700 { 1701 "encodings": { 1702 "Lock CmpXchgb": { "opcodes": [ "F0", "0F", "B0" ], "type": "reg_to_rm" } 1703 }, 1704 "args": [ 1705 { "class": "AL", "usage": "use_def" }, 1706 { "class": "Mem8", "usage": "use_def" }, 1707 { "class": "GeneralReg8", "usage": "use" }, 1708 { "class": "FLAGS", "usage": "def" } 1709 ] 1710 }, 1711 { 1712 "encodings": { 1713 "Lock CmpXchgl": { "opcodes": [ "F0", "0F", "B1" ], "type": "reg_to_rm" } 1714 }, 1715 "args": [ 1716 { "class": "EAX", "usage": "use_def" }, 1717 { "class": "Mem32", "usage": "use_def" }, 1718 { "class": "GeneralReg32", "usage": "use" }, 1719 { "class": "FLAGS", "usage": "def" } 1720 ] 1721 }, 1722 { 1723 "encodings": { 1724 "Lock CmpXchgw": { "opcodes": [ "F0", "66", "0F", "B1" ], "type": "reg_to_rm" } 1725 }, 1726 "args": [ 1727 { "class": "AX", "usage": "use_def" }, 1728 { "class": "Mem16", "usage": "use_def" }, 1729 { "class": "GeneralReg16", "usage": "use" }, 1730 { "class": "FLAGS", "usage": "def" } 1731 ] 1732 }, 1733 { 1734 "encodings": { 1735 "Lock Xaddb": { "opcodes": [ "F0", "0F", "C0" ], "type": "reg_to_rm" }, 1736 "Xaddb": { "opcodes": [ "0F", "C0" ], "type": "reg_to_rm" } 1737 }, 1738 "args": [ 1739 { "class": "Mem8", "usage": "use_def" }, 1740 { "class": "GeneralReg8", "usage": "use_def" }, 1741 { "class": "FLAGS", "usage": "use_def" } 1742 ] 1743 }, 1744 { 1745 "encodings": { 1746 "Lock Xaddl": { "opcodes": [ "F0", "0F", "C1" ], "type": "reg_to_rm" }, 1747 "Xaddl": { "opcodes": [ "0F", "C1" ], "type": "reg_to_rm" } 1748 }, 1749 "args": [ 1750 { "class": "Mem32", "usage": "use_def" }, 1751 { "class": "GeneralReg32", "usage": "use_def" }, 1752 { "class": "FLAGS", "usage": "use_def" } 1753 ] 1754 }, 1755 { 1756 "encodings": { 1757 "Lock Xaddw": { "opcodes": [ "F0", "66", "0F", "C1" ], "type": "reg_to_rm" }, 1758 "Xaddw": { "opcodes": [ "66", "0F", "C1" ], "type": "reg_to_rm" } 1759 }, 1760 "args": [ 1761 { "class": "Mem16", "usage": "use_def" }, 1762 { "class": "GeneralReg16", "usage": "use_def" }, 1763 { "class": "FLAGS", "usage": "use_def" } 1764 ] 1765 }, 1766 { 1767 "encodings": { 1768 "Movapd": { "opcodes": [ "66", "0F", "28" ] }, 1769 "Movaps": { "opcodes": [ "0F", "28" ] }, 1770 "Movdqa": { "opcodes": [ "66", "0F", "6F" ] }, 1771 "Movdqu": { "opcodes": [ "F3", "0F", "6F" ] } 1772 }, 1773 "args": [ 1774 { "class": "XmmReg", "usage": "def" }, 1775 { "class": "XmmReg/VecMem128", "usage": "use" } 1776 ] 1777 }, 1778 { 1779 "encodings": { 1780 "Movapd": { "opcodes": [ "66", "0F", "29" ] }, 1781 "Movaps": { "opcodes": [ "0F", "29" ] }, 1782 "Vmovapd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "29" ] }, 1783 "Vmovaps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "29" ] } 1784 }, 1785 "args": [ 1786 { "class": "VecMem128", "usage": "def" }, 1787 { "class": "XmmReg", "usage": "use" } 1788 ] 1789 }, 1790 { 1791 "encodings": { 1792 "Movb": { "opcode": "B0" } 1793 }, 1794 "args": [ 1795 { "class": "GeneralReg8", "usage": "def" }, 1796 { "class": "Imm8" } 1797 ] 1798 }, 1799 { 1800 "encodings": { 1801 "Movb": { "opcode": "8A" } 1802 }, 1803 "args": [ 1804 { "class": "GeneralReg8", "usage": "def" }, 1805 { "class": "Mem8", "usage": "use" } 1806 ] 1807 }, 1808 { 1809 "encodings": { 1810 "Movb": { "opcode": "88", "type": "reg_to_rm" } 1811 }, 1812 "args": [ 1813 { "class": "GeneralReg8/Mem8", "usage": "def" }, 1814 { "class": "GeneralReg8", "usage": "use" } 1815 ] 1816 }, 1817 { 1818 "encodings": { 1819 "Movb": { "opcodes": [ "C6", "0" ] } 1820 }, 1821 "args": [ 1822 { "class": "Mem8", "usage": "def" }, 1823 { "class": "Imm8" } 1824 ] 1825 }, 1826 { 1827 "encodings": { 1828 "Movd": { "opcodes": [ "66", "0F", "7E" ], "type": "reg_to_rm" }, 1829 "Vmovd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "7E" ], "type": "reg_to_rm" } 1830 }, 1831 "args": [ 1832 { "class": "GeneralReg32/Mem32", "usage": "def" }, 1833 { "class": "XmmReg", "usage": "use" } 1834 ] 1835 }, 1836 { 1837 "encodings": { 1838 "Movd": { "opcodes": [ "66", "0F", "6E" ] }, 1839 "Vmovd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "6E" ] } 1840 }, 1841 "args": [ 1842 { "class": "XmmReg", "usage": "def" }, 1843 { "class": "GeneralReg32/Mem32", "usage": "use" } 1844 ] 1845 }, 1846 { 1847 "name": "MovdqRegReg", 1848 "args": [ 1849 { "class": "XmmReg", "usage": "def" }, 1850 { "class": "XmmReg", "usage": "use" } 1851 ], 1852 "asm": "Pmov", 1853 "mnemo": "MOVDQ" 1854 }, 1855 { 1856 "encodings": { 1857 "Movdqa": { "opcodes": [ "66", "0F", "7F" ] }, 1858 "Movdqu": { "opcodes": [ "F3", "0F", "7F" ] }, 1859 "Vmovdqa": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "7F" ] }, 1860 "Vmovdqu": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "7F" ] } 1861 }, 1862 "args": [ 1863 { "class": "VecMem128", "usage": "def" }, 1864 { "class": "XmmReg", "usage": "use" } 1865 ] 1866 }, 1867 { 1868 "encodings": { 1869 "Movhlps": { "opcodes": [ "0F", "12" ] }, 1870 "Movlhps": { "opcodes": [ "0F", "16" ] }, 1871 "Movsd": { "opcodes": [ "F2", "0F", "10" ] }, 1872 "Movss": { "opcodes": [ "F3", "0F", "10" ] } 1873 }, 1874 "args": [ 1875 { "class": "XmmReg", "usage": "use_def" }, 1876 { "class": "XmmReg", "usage": "use" } 1877 ], 1878 "comment": "Upper bits (lower bits for Movlhps) are unchanged" 1879 }, 1880 { 1881 "encodings": { 1882 "Movhpd": { "opcodes": [ "66", "0F", "17" ] }, 1883 "Movhps": { "opcodes": [ "0F", "17" ] }, 1884 "Movlpd": { "opcodes": [ "66", "0F", "13" ] }, 1885 "Movlps": { "opcodes": [ "0F", "13" ] }, 1886 "Vmovhpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "17" ] }, 1887 "Vmovhps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "17" ] }, 1888 "Vmovlpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "13" ] }, 1889 "Vmovlps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "13" ] } 1890 }, 1891 "args": [ 1892 { "class": "VecMem64", "usage": "use_def" }, 1893 { "class": "XmmReg", "usage": "use" } 1894 ] 1895 }, 1896 { 1897 "encodings": { 1898 "Movhpd": { "opcodes": [ "66", "0F", "16" ] }, 1899 "Movhps": { "opcodes": [ "0F", "16" ] }, 1900 "Movlpd": { "opcodes": [ "66", "0F", "12" ] }, 1901 "Movlps": { "opcodes": [ "0F", "12" ] } 1902 }, 1903 "args": [ 1904 { "class": "XmmReg", "usage": "use_def" }, 1905 { "class": "VecMem64", "usage": "use" } 1906 ] 1907 }, 1908 { 1909 "encodings": { 1910 "Movl": { "opcode": "B8" } 1911 }, 1912 "args": [ 1913 { "class": "GeneralReg32", "usage": "def" }, 1914 { "class": "Imm32" } 1915 ] 1916 }, 1917 { 1918 "encodings": { 1919 "Movl": { "opcode": "8B" } 1920 }, 1921 "args": [ 1922 { "class": "GeneralReg32", "usage": "def" }, 1923 { "class": "Mem32", "usage": "use" } 1924 ] 1925 }, 1926 { 1927 "encodings": { 1928 "Movl": { "opcode": "89", "type": "reg_to_rm" } 1929 }, 1930 "args": [ 1931 { "class": "GeneralReg32/Mem32", "usage": "def" }, 1932 { "class": "GeneralReg32", "usage": "use" } 1933 ] 1934 }, 1935 { 1936 "encodings": { 1937 "Movl": { "opcodes": [ "C7", "0" ] } 1938 }, 1939 "args": [ 1940 { "class": "Mem32", "usage": "def" }, 1941 { "class": "Imm32" } 1942 ] 1943 }, 1944 { 1945 "encodings": { 1946 "Movmskpd": { "opcodes": [ "66", "0F", "50" ] }, 1947 "Movmskps": { "opcodes": [ "0F", "50" ] }, 1948 "Vmovmskpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "50" ] }, 1949 "Vmovmskps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "50" ] } 1950 }, 1951 "args": [ 1952 { "class": "GeneralReg32", "usage": "def" }, 1953 { "class": "XmmReg", "usage": "use" } 1954 ] 1955 }, 1956 { 1957 "encodings": { 1958 "Movq": { "opcodes": [ "66", "0F", "D6" ] }, 1959 "Movsd": { "opcodes": [ "F2", "0F", "11" ] }, 1960 "Vmovq": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "D6" ] }, 1961 "Vmovsd": { "feature": "AVX", "opcodes": [ "C4", "01", "03", "11" ] } 1962 }, 1963 "args": [ 1964 { "class": "VecMem64", "usage": "def" }, 1965 { "class": "XmmReg", "usage": "use" } 1966 ] 1967 }, 1968 { 1969 "encodings": { 1970 "Movsd": { "opcodes": [ "F2", "0F", "10" ] }, 1971 "Vmovsd": { "feature": "AVX", "opcodes": [ "C4", "01", "03", "10" ] } 1972 }, 1973 "args": [ 1974 { "class": "XmmReg", "usage": "def" }, 1975 { "class": "VecMem64", "usage": "use" } 1976 ], 1977 "comment": "Upper bits are zero-filled" 1978 }, 1979 { 1980 "encodings": { 1981 "Movss": { "opcodes": [ "F3", "0F", "11" ] }, 1982 "Vmovss": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "11" ] } 1983 }, 1984 "args": [ 1985 { "class": "Mem32", "usage": "def" }, 1986 { "class": "XmmReg", "usage": "use" } 1987 ] 1988 }, 1989 { 1990 "encodings": { 1991 "Movss": { "opcodes": [ "F3", "0F", "10" ] }, 1992 "Vmovss": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "10" ] } 1993 }, 1994 "args": [ 1995 { "class": "XmmReg", "usage": "def" }, 1996 { "class": "VecMem32", "usage": "use" } 1997 ], 1998 "comment": "Upper bits are zero-filled" 1999 }, 2000 { 2001 "encodings": { 2002 "Movsxbl": { "opcodes": [ "0F", "BE" ] }, 2003 "Movzxbl": { "opcodes": [ "0F", "B6" ] } 2004 }, 2005 "args": [ 2006 { "class": "GeneralReg32", "usage": "def" }, 2007 { "class": "GeneralReg8/Mem8", "usage": "use" } 2008 ] 2009 }, 2010 { 2011 "encodings": { 2012 "Movsxwl": { "opcodes": [ "0F", "BF" ] }, 2013 "Movzxwl": { "opcodes": [ "0F", "B7" ] } 2014 }, 2015 "args": [ 2016 { "class": "GeneralReg32", "usage": "def" }, 2017 { "class": "GeneralReg16/Mem16", "usage": "use" } 2018 ] 2019 }, 2020 { 2021 "encodings": { 2022 "Movw": { "opcodes": [ "66", "B8" ] } 2023 }, 2024 "args": [ 2025 { "class": "GeneralReg16", "usage": "def" }, 2026 { "class": "Imm16" } 2027 ] 2028 }, 2029 { 2030 "encodings": { 2031 "Movw": { "opcodes": [ "66", "8B" ] } 2032 }, 2033 "args": [ 2034 { "class": "GeneralReg16", "usage": "def" }, 2035 { "class": "Mem16", "usage": "use" } 2036 ] 2037 }, 2038 { 2039 "encodings": { 2040 "Movw": { "opcodes": [ "66", "89" ], "type": "reg_to_rm" } 2041 }, 2042 "args": [ 2043 { "class": "GeneralReg16/Mem16", "usage": "def" }, 2044 { "class": "GeneralReg16", "usage": "use" } 2045 ] 2046 }, 2047 { 2048 "encodings": { 2049 "Movw": { "opcodes": [ "66", "C7", "0" ] } 2050 }, 2051 "args": [ 2052 { "class": "Mem16", "usage": "def" }, 2053 { "class": "Imm16" } 2054 ] 2055 }, 2056 { 2057 "encodings": { 2058 "Mulxl": { "feature": "BMI2", "opcodes": [ "C4", "02", "03", "F6" ], "type": "vex_rm_to_reg" }, 2059 "Pdepl": { "feature": "BMI2", "opcodes": [ "C4", "02", "03", "F5" ], "type": "vex_rm_to_reg" }, 2060 "Pextl": { "feature": "BMI2", "opcodes": [ "C4", "02", "02", "F5" ], "type": "vex_rm_to_reg" } 2061 }, 2062 "args": [ 2063 { "class": "GeneralReg32", "usage": "use_def" }, 2064 { "class": "GeneralReg32", "usage": "use" }, 2065 { "class": "GeneralReg32/Mem32", "usage": "use" } 2066 ] 2067 }, 2068 { 2069 "encodings": { 2070 "Negl": { "opcodes": [ "F7", "3" ] }, 2071 "RollByOne": { "opcodes": [ "D1", "0" ] }, 2072 "RorlByOne": { "opcodes": [ "D1", "1" ] }, 2073 "SarlByOne": { "opcodes": [ "D1", "7" ] }, 2074 "ShllByOne": { "opcodes": [ "D1", "4" ] }, 2075 "ShrlByOne": { "opcodes": [ "D1", "5" ] } 2076 }, 2077 "args": [ 2078 { "class": "GeneralReg32/Mem32", "usage": "use_def" }, 2079 { "class": "FLAGS", "usage": "def" } 2080 ] 2081 }, 2082 { 2083 "encodings": { 2084 "Negw": { "opcodes": [ "66", "F7", "3" ] }, 2085 "RolwByOne": { "opcodes": [ "66", "D1", "0" ] }, 2086 "RorwByOne": { "opcodes": [ "66", "D1", "1" ] }, 2087 "SarwByOne": { "opcodes": [ "66", "D1", "7" ] }, 2088 "ShlwByOne": { "opcodes": [ "66", "D1", "4" ] }, 2089 "ShrwByOne": { "opcodes": [ "66", "D1", "5" ] } 2090 }, 2091 "args": [ 2092 { "class": "GeneralReg16/Mem16", "usage": "use_def" }, 2093 { "class": "FLAGS", "usage": "def" } 2094 ] 2095 }, 2096 { 2097 "encodings": { 2098 "Notb": { "opcodes": [ "F6", "2" ] } 2099 }, 2100 "args": [ 2101 { "class": "GeneralReg8/Mem8", "usage": "use_def" } 2102 ] 2103 }, 2104 { 2105 "encodings": { 2106 "Notl": { "opcodes": [ "F7", "2" ] } 2107 }, 2108 "args": [ 2109 { "class": "GeneralReg32/Mem32", "usage": "use_def" } 2110 ] 2111 }, 2112 { 2113 "encodings": { 2114 "Notw": { "opcodes": [ "66", "F7", "2" ] } 2115 }, 2116 "args": [ 2117 { "class": "GeneralReg16/Mem16", "usage": "use_def" } 2118 ] 2119 }, 2120 { 2121 "encodings": { 2122 "Pclmulqdq": { "feature": "CLMUL", "opcodes": [ "66", "0F", "3A", "44" ] }, 2123 "Shufpd": { "opcodes": [ "66", "0F", "C6" ] }, 2124 "Shufps": { "opcodes": [ "0F", "C6" ] } 2125 }, 2126 "args": [ 2127 { "class": "VecReg128", "usage": "use_def" }, 2128 { "class": "VecReg128/VecMem128", "usage": "use" }, 2129 { "class": "Imm8" } 2130 ] 2131 }, 2132 { 2133 "encodings": { 2134 "Pextrb": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "14" ], "type": "reg_to_rm" }, 2135 "Pextrd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "16" ], "type": "reg_to_rm" }, 2136 "Pextrw": { "opcodes": [ "66", "0F", "C5" ] }, 2137 "Vpextrb": { "feature": "AVX", "opcodes": [ "C4", "03", "01", "14" ], "type": "reg_to_rm" }, 2138 "Vpextrd": { "feature": "AVX", "opcodes": [ "C4", "03", "01", "16" ], "type": "reg_to_rm" }, 2139 "Vpextrw": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "C5" ] } 2140 }, 2141 "args": [ 2142 { "class": "GeneralReg32", "usage": "def" }, 2143 { "class": "VecReg128", "usage": "use" }, 2144 { "class": "Imm8" } 2145 ] 2146 }, 2147 { 2148 "encodings": { 2149 "Pextrb": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "14" ], "type": "reg_to_rm" }, 2150 "Vpextrb": { "feature": "AVX", "opcodes": [ "C4", "03", "01", "14" ], "type": "reg_to_rm" } 2151 }, 2152 "args": [ 2153 { "class": "Mem8", "usage": "def" }, 2154 { "class": "VecReg128", "usage": "use" }, 2155 { "class": "Imm8" } 2156 ] 2157 }, 2158 { 2159 "encodings": { 2160 "Pextrd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "16" ], "type": "reg_to_rm" }, 2161 "Vpextrd": { "feature": "AVX", "opcodes": [ "C4", "03", "01", "16" ], "type": "reg_to_rm" } 2162 }, 2163 "args": [ 2164 { "class": "Mem32", "usage": "def" }, 2165 { "class": "VecReg128", "usage": "use" }, 2166 { "class": "Imm8" } 2167 ] 2168 }, 2169 { 2170 "encodings": { 2171 "Pextrw": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "15" ] }, 2172 "Vpextrw": { "feature": "AVX", "opcodes": [ "C4", "03", "01", "15" ] } 2173 }, 2174 "args": [ 2175 { "class": "Mem16", "usage": "def" }, 2176 { "class": "VecReg128", "usage": "use" }, 2177 { "class": "Imm8" } 2178 ] 2179 }, 2180 { 2181 "encodings": { 2182 "Pinsrb": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "20" ] }, 2183 "Pinsrd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "22" ] }, 2184 "Pinsrw": { "opcodes": [ "66", "0F", "C4" ] } 2185 }, 2186 "args": [ 2187 { "class": "VecReg128", "usage": "use_def" }, 2188 { "class": "GeneralReg32", "usage": "use" }, 2189 { "class": "Imm8" } 2190 ] 2191 }, 2192 { 2193 "encodings": { 2194 "Pinsrb": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "20" ] } 2195 }, 2196 "args": [ 2197 { "class": "VecReg128", "usage": "use_def" }, 2198 { "class": "Mem8", "usage": "use" }, 2199 { "class": "Imm8" } 2200 ] 2201 }, 2202 { 2203 "encodings": { 2204 "Pinsrd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "22" ] } 2205 }, 2206 "args": [ 2207 { "class": "VecReg128", "usage": "use_def" }, 2208 { "class": "Mem32", "usage": "use" }, 2209 { "class": "Imm8" } 2210 ] 2211 }, 2212 { 2213 "encodings": { 2214 "Pinsrw": { "opcodes": [ "66", "0F", "C4" ] } 2215 }, 2216 "args": [ 2217 { "class": "VecReg128", "usage": "use_def" }, 2218 { "class": "Mem16", "usage": "use" }, 2219 { "class": "Imm8" } 2220 ] 2221 }, 2222 { 2223 "encodings": { 2224 "Pmovmskb": { "opcodes": [ "66", "0F", "D7" ] }, 2225 "Vpmovmskb": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "D7" ] } 2226 }, 2227 "args": [ 2228 { "class": "GeneralReg32", "usage": "def" }, 2229 { "class": "VecReg128", "usage": "use" } 2230 ] 2231 }, 2232 { 2233 "encodings": { 2234 "Pmovsxbd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "21" ] }, 2235 "Pmovsxwq": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "24" ] }, 2236 "Pmovzxbd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "31" ] }, 2237 "Pmovzxwq": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "34" ] } 2238 }, 2239 "args": [ 2240 { "class": "XmmReg", "usage": "def" }, 2241 { "class": "XmmReg/VecMem32", "usage": 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{ "class": "RSP", "usage": "use_def" }, 2277 { "class": "Imm32" } 2278 ] 2279 }, 2280 { 2281 "encodings": { 2282 "PushImm8": { "opcode": "6A" } 2283 }, 2284 "args": [ 2285 { "class": "RSP", "usage": "use_def" }, 2286 { "class": "Imm8" } 2287 ] 2288 }, 2289 { 2290 "encodings": { 2291 "RclbByCl": { "opcodes": [ "D2", "2" ] }, 2292 "RcrbByCl": { "opcodes": [ "D2", "3" ] } 2293 }, 2294 "args": [ 2295 { "class": "GeneralReg8/Mem8", "usage": "use_def" }, 2296 { "class": "CL", "usage": "use" }, 2297 { "class": "FLAGS", "usage": "use_def" } 2298 ] 2299 }, 2300 { 2301 "encodings": { 2302 "RclbByOne": { "opcodes": [ "D0", "2" ] }, 2303 "RcrbByOne": { "opcodes": [ "D0", "3" ] } 2304 }, 2305 "args": [ 2306 { "class": "GeneralReg8/Mem8", "usage": "use_def" }, 2307 { "class": "FLAGS", "usage": "use_def" } 2308 ] 2309 }, 2310 { 2311 "encodings": { 2312 "RcllByCl": { "opcodes": [ "D3", "2" ] }, 2313 "RcrlByCl": { "opcodes": [ "D3", "3" ] } 2314 }, 2315 "args": [ 2316 { "class": "GeneralReg32/Mem32", "usage": "use_def" }, 2317 { "class": "CL", "usage": "use" }, 2318 { "class": "FLAGS", "usage": "use_def" } 2319 ] 2320 }, 2321 { 2322 "encodings": { 2323 "RcllByOne": { "opcodes": [ "D1", "2" ] }, 2324 "RcrlByOne": { "opcodes": [ "D1", "3" ] } 2325 }, 2326 "args": [ 2327 { "class": "GeneralReg32/Mem32", "usage": "use_def" }, 2328 { "class": "FLAGS", "usage": "use_def" } 2329 ] 2330 }, 2331 { 2332 "encodings": { 2333 "RclwByCl": { "opcodes": [ "66", "D3", "2" ] }, 2334 "RcrwByCl": { "opcodes": [ "66", "D3", "3" ] } 2335 }, 2336 "args": [ 2337 { "class": "GeneralReg16/Mem16", "usage": "use_def" }, 2338 { "class": "CL", "usage": "use" }, 2339 { "class": "FLAGS", "usage": "use_def" } 2340 ] 2341 }, 2342 { 2343 "encodings": { 2344 "RclwByOne": { "opcodes": [ "66", "D1", "2" ] }, 2345 "RcrwByOne": { "opcodes": [ "66", "D1", "3" ] } 2346 }, 2347 "args": [ 2348 { "class": "GeneralReg16/Mem16", "usage": "use_def" }, 2349 { "class": "FLAGS", "usage": "use_def" } 2350 ] 2351 }, 2352 { 2353 "encodings": { 2354 "Ret": { "opcode": "C3" } 2355 }, 2356 "args": [ 2357 { "class": "RSP", "usage": "use_def" } 2358 ] 2359 }, 2360 { 2361 "encodings": { 2362 "RolbByCl": { "opcodes": [ "D2", "0" ] }, 2363 "RorbByCl": { "opcodes": [ "D2", "1" ] }, 2364 "SarbByCl": { "opcodes": [ "D2", "7" ] }, 2365 "ShlbByCl": { "opcodes": [ "D2", "4" ] }, 2366 "ShrbByCl": { "opcodes": [ "D2", "5" ] } 2367 }, 2368 "args": [ 2369 { "class": "GeneralReg8/Mem8", "usage": "use_def" }, 2370 { "class": "CL", "usage": "use" }, 2371 { "class": "FLAGS", "usage": "def" } 2372 ] 2373 }, 2374 { 2375 "encodings": { 2376 "RollByCl": { "opcodes": [ "D3", "0" ] }, 2377 "RorlByCl": { "opcodes": [ "D3", "1" ] }, 2378 "SarlByCl": { "opcodes": [ "D3", "7" ] }, 2379 "ShllByCl": { "opcodes": [ "D3", "4" ] }, 2380 "ShrlByCl": { "opcodes": [ "D3", "5" ] } 2381 }, 2382 "args": [ 2383 { "class": "GeneralReg32/Mem32", "usage": "use_def" }, 2384 { "class": "CL", "usage": "use" }, 2385 { "class": "FLAGS", "usage": "def" } 2386 ] 2387 }, 2388 { 2389 "encodings": { 2390 "RolwByCl": { "opcodes": [ "66", "D3", "0" ] }, 2391 "RorwByCl": { "opcodes": [ "66", "D3", "1" ] }, 2392 "SarwByCl": { "opcodes": [ "66", "D3", "7" ] }, 2393 "ShlwByCl": { "opcodes": [ "66", "D3", "4" ] }, 2394 "ShrwByCl": { "opcodes": [ "66", "D3", "5" ] } 2395 }, 2396 "args": [ 2397 { "class": "GeneralReg16/Mem16", "usage": "use_def" }, 2398 { "class": "CL", "usage": "use" }, 2399 { "class": "FLAGS", "usage": "def" } 2400 ] 2401 }, 2402 { 2403 "encodings": { 2404 "Rorxl": { "feature": "BMI2", "opcodes": [ "C4", "03", "03", "F0" ] } 2405 }, 2406 "args": [ 2407 { "class": "GeneralReg32", "usage": "def" }, 2408 { "class": "GeneralReg32/Mem32", "usage": "use" }, 2409 { "class": "Imm8" } 2410 ] 2411 }, 2412 { 2413 "encodings": { 2414 "Roundsd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "0B" ] } 2415 }, 2416 "args": [ 2417 { "class": "FpReg64", "usage": "def" }, 2418 { "class": "FpReg64/VecMem64", "usage": "use" }, 2419 { "class": "Imm8" } 2420 ] 2421 }, 2422 { 2423 "encodings": { 2424 "Roundss": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "0A" ] } 2425 }, 2426 "args": [ 2427 { "class": "FpReg32", "usage": "def" }, 2428 { "class": "FpReg32/VecMem32", "usage": "use" }, 2429 { "class": "Imm8" } 2430 ] 2431 }, 2432 { 2433 "encodings": { 2434 "Sahf": { "opcode": "9E" } 2435 }, 2436 "args": [ 2437 { "class": "EAX", "usage": "use" }, 2438 { "class": "FLAGS", "usage": "def" } 2439 ] 2440 }, 2441 { 2442 "encodings": { 2443 "Sarxl": { "feature": "BMI2", "opcodes": [ "C4", "02", "02", "F7" ] }, 2444 "Shlxl": { "feature": "BMI2", "opcodes": [ "C4", "02", "01", "F7" ] }, 2445 "Shrxl": { "feature": "BMI2", "opcodes": [ "C4", "02", "03", "F7" ] } 2446 }, 2447 "args": [ 2448 { "class": "GeneralReg32", "usage": "use_def" }, 2449 { "class": "GeneralReg32/Mem32", "usage": "use" }, 2450 { "class": "GeneralReg32", "usage": "use" } 2451 ] 2452 }, 2453 { 2454 "encodings": { 2455 "Setcc": { "opcodes": [ "0F", "90", "0" ] } 2456 }, 2457 "args": [ 2458 { "class": "Cond" }, 2459 { "class": "GeneralReg8/Mem8", "usage": "def" }, 2460 { "class": "FLAGS", "usage": "use" } 2461 ] 2462 }, 2463 { 2464 "encodings": { 2465 "Shldl": { "opcodes": [ "0F", "A4" ], "type": "reg_to_rm" }, 2466 "Shrdl": { "opcodes": [ "0F", "AC" ], "type": "reg_to_rm" } 2467 }, 2468 "args": [ 2469 { "class": "GeneralReg32/Mem32", "usage": "use_def" }, 2470 { "class": "GeneralReg32", "usage": "use" }, 2471 { "class": "Imm8" }, 2472 { "class": "FLAGS", "usage": "def" } 2473 ] 2474 }, 2475 { 2476 "encodings": { 2477 "ShldlByCl": { "opcodes": [ "0F", "A5" ], "type": "reg_to_rm" }, 2478 "ShrdlByCl": { "opcodes": [ "0F", "AD" ], "type": "reg_to_rm" } 2479 }, 2480 "args": [ 2481 { "class": "GeneralReg32/Mem32", "usage": "use_def" }, 2482 { "class": "GeneralReg32", "usage": "use" }, 2483 { "class": "CL", "usage": "use" }, 2484 { "class": "FLAGS", "usage": "def" } 2485 ] 2486 }, 2487 { 2488 "encodings": { 2489 "Sqrtsd": { "opcodes": [ "F2", "0F", "51" ] } 2490 }, 2491 "args": [ 2492 { "class": "FpReg64", "usage": "def" }, 2493 { "class": "FpReg64/VecMem64", "usage": "use" } 2494 ] 2495 }, 2496 { 2497 "encodings": { 2498 "Sqrtss": { "opcodes": [ "F3", "0F", "51" ] } 2499 }, 2500 "args": [ 2501 { "class": "FpReg32", "usage": "def" }, 2502 { "class": "FpReg32/VecMem32", "usage": "use" } 2503 ] 2504 }, 2505 { 2506 "encodings": { 2507 "Stmxcsr": { "opcodes": [ "0F", "AE", "3" ] }, 2508 "Vstmxcsr": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "AE", "3" ] } 2509 }, 2510 "args": [ 2511 { "class": "Mem32", "usage": "def" } 2512 ] 2513 }, 2514 { 2515 "encodings": { 2516 "Ucomisd": { "opcodes": [ "66", "0F", "2E" ] } 2517 }, 2518 "args": [ 2519 { "class": "FpReg64", "usage": "use" }, 2520 { "class": "FpReg64/VecMem64", "usage": "use" }, 2521 { "class": "FLAGS", "usage": "def" } 2522 ] 2523 }, 2524 { 2525 "encodings": { 2526 "Ucomiss": { "opcodes": [ "0F", "2E" ] } 2527 }, 2528 "args": [ 2529 { "class": "FpReg32", "usage": "use" }, 2530 { "class": "FpReg32/VecMem32", "usage": "use" }, 2531 { "class": "FLAGS", "usage": "def" } 2532 ] 2533 }, 2534 { 2535 "encodings": { 2536 "Vaddpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "58" ], "type": "optimizable_using_commutation" }, 2537 "Vaddps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "58" ], "type": "optimizable_using_commutation" }, 2538 "Vaesdec": { "feature": "AESAVX", "opcodes": [ "C4", "02", "01", "DE" ], "type": "vex_rm_to_reg" }, 2539 "Vaesdeclast": { "feature": "AESAVX", "opcodes": [ "C4", "02", "01", "DF" ], "type": "vex_rm_to_reg" }, 2540 "Vaesenc": { "feature": "AESAVX", "opcodes": [ "C4", "02", "01", "DC" ], "type": "vex_rm_to_reg" }, 2541 "Vaesenclast": { "feature": "AESAVX", "opcodes": [ "C4", "02", "01", "DD" ], "type": "vex_rm_to_reg" }, 2542 "Vandpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "54" ], "type": "optimizable_using_commutation" }, 2543 "Vandps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "54" ], "type": "optimizable_using_commutation" }, 2544 "Vcmpeqpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "C2", "00" ], "type": "optimizable_using_commutation" }, 2545 "Vcmpeqps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "C2", "00" ], "type": "optimizable_using_commutation" }, 2546 "Vcmplepd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "C2", "02" ], "type": "vex_rm_to_reg" }, 2547 "Vcmpleps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "C2", "02" ], "type": "vex_rm_to_reg" }, 2548 "Vcmpltpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "C2", "01" ], "type": "vex_rm_to_reg" }, 2549 "Vcmpltps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "C2", "01" ], "type": "vex_rm_to_reg" }, 2550 "Vcmpneqpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "C2", "04" ], "type": "optimizable_using_commutation" }, 2551 "Vcmpneqps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "C2", "04" ], "type": "optimizable_using_commutation" }, 2552 "Vcmpnlepd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "C2", "06" ], "type": "vex_rm_to_reg" }, 2553 "Vcmpnleps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "C2", "06" ], "type": "vex_rm_to_reg" }, 2554 "Vcmpnltpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "C2", "05" ], "type": "vex_rm_to_reg" }, 2555 "Vcmpnltps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "C2", "05" ], "type": "vex_rm_to_reg" }, 2556 "Vcmpordpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "C2", "07" ], "type": "optimizable_using_commutation" }, 2557 "Vcmpordps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "C2", "07" ], "type": "optimizable_using_commutation" }, 2558 "Vcmpunordpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "C2", "03" ], "type": "optimizable_using_commutation" }, 2559 "Vcmpunordps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "C2", "03" ], "type": "optimizable_using_commutation" }, 2560 "Vdivpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "5E" 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"class": "VecReg128", "usage": "use" }, 3487 { "class": "Imm2" } 3488 ] 3489 }, 3490 { 3491 "encodings": { 3492 "Vpermil2pd": { "feature": "AVX", "opcodes": [ "C4", "03", "85", "49" ], "type": "vex_imm_rm_to_reg" }, 3493 "Vpermil2ps": { "feature": "AVX", "opcodes": [ "C4", "03", "85", "48" ], "type": "vex_imm_rm_to_reg" } 3494 }, 3495 "args": [ 3496 { "class": "VecReg256", "usage": "def" }, 3497 { "class": "VecReg256", "usage": "use" }, 3498 { "class": "VecReg256", "usage": "use" }, 3499 { "class": "VecMem256", "usage": "use" }, 3500 { "class": "Imm2" } 3501 ] 3502 }, 3503 { 3504 "encodings": { 3505 "Vpermil2pd": { "feature": "AVX", "opcodes": [ "C4", "03", "05", "49" ], "type": "vex_rm_imm_to_reg" }, 3506 "Vpermil2ps": { "feature": "AVX", "opcodes": [ "C4", "03", "05", "48" ], "type": "vex_rm_imm_to_reg" } 3507 }, 3508 "args": [ 3509 { "class": "VecReg256", "usage": "def" }, 3510 { "class": "VecReg256", "usage": "use" }, 3511 { "class": "VecReg256/VecMem256", "usage": "use" }, 3512 { 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