1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef HASWELL_REGISTERS_MCHBAR_H 4 #define HASWELL_REGISTERS_MCHBAR_H 5 6 /* Memory controller characteristics */ 7 #define NUM_CHANNELS 2 8 #define NUM_SLOTS 2 9 10 /* Register definitions */ 11 #define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */ 12 #define MAD_DIMM(ch) (0x5004 + (ch) * 4) 13 #define MC_INIT_STATE_G 0x5030 14 #define MRC_REVISION 0x5034 /* MRC Revision */ 15 16 #define MC_LOCK 0x50fc /* Memory Controller Lock register */ 17 18 #define GFXVTBAR 0x5400 /* Base address for IGD */ 19 #define EDRAMBAR 0x5408 /* Base address for eDRAM */ 20 #define VTVC0BAR 0x5410 /* Base address for PEG, USB, SATA, etc. */ 21 #define INTRDIRCTL 0x5418 /* Interrupt Redirection Control (PAIR) */ 22 #define GDXCBAR 0x5420 /* Generic Debug eXternal Connection */ 23 24 /* PAVP message register. Bit 0 locks PAVP settings, and bits [31..20] are an offset. */ 25 #define MMIO_PAVP_MSG 0x5500 26 27 #define PCU_DDR_PTM_CTL 0x5880 28 29 /* Some power MSRs are also represented in MCHBAR */ 30 #define MCH_PKG_POWER_LIMIT_LO 0x59a0 31 #define MCH_PKG_POWER_LIMIT_HI 0x59a4 32 33 #define MCH_DDR_POWER_LIMIT_LO 0x58e0 34 #define MCH_DDR_POWER_LIMIT_HI 0x58e4 35 36 #define SSKPD 0x5d10 /* 64-bit scratchpad register */ 37 38 /* PCODE MMIO communications live in the MCHBAR */ 39 #define BIOS_MAILBOX_DATA 0x5da0 40 41 #define BIOS_MAILBOX_INTERFACE 0x5da4 42 #define MAILBOX_RUN_BUSY (1 << 31) 43 #define MAILBOX_BIOS_CMD_READ_PCS 1 44 #define MAILBOX_BIOS_CMD_WRITE_PCS 2 45 #define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509 46 #define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909 47 #define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa 48 #define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb 49 #define MAILBOX_BIOS_CMD_READ_C9C10_VOLTAGE 0x26 50 #define MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE 0x27 51 52 /* Errors are returned back in bits 7:0 */ 53 #define MAILBOX_BIOS_ERROR_NONE 0 54 #define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1 55 #define MAILBOX_BIOS_ERROR_TIMEOUT 2 56 #define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3 57 #define MAILBOX_BIOS_ERROR_RESERVED 4 58 #define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5 59 #define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6 60 #define MAILBOX_BIOS_ERROR_VR_ERROR 7 61 62 #define BIOS_RESET_CPL 0x5da8 /* 8-bit */ 63 64 #define MC_BIOS_DATA 0x5e04 /* Miscellaneous information for BIOS */ 65 #define SAPMCTL 0x5f00 66 67 #define HDAUDRID 0x6008 68 #define UMAGFXCTL 0x6020 69 #define VDMBDFBARKVM 0x6030 70 #define VDMBDFBARPAVP 0x6034 71 #define VTDTRKLCK 0x63fc 72 #define REQLIM 0x6800 73 #define DMIVCLIM 0x7000 74 #define CRDTLCK 0x77fc 75 #define MCARBLCK 0x7ffc 76 77 #endif /* HASWELL_REGISTERS_MCHBAR_H */ 78