1 /* 2 * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <lib/utils_def.h> 11 12 #include <nrd_css_fw_def2.h> 13 #include <nrd_plat_arm_def2.h> 14 #include <nrd_ros_fw_def2.h> 15 #include <nrd_sdei.h> 16 17 /* Remote chip address offset */ 18 #define NRD_REMOTE_CHIP_MEM_OFFSET(n) \ 19 ((ULL(1) << NRD_ADDR_BITS_PER_CHIP) * (n)) 20 21 #define NRD_MAX_CPUS_PER_CLUSTER U(1) 22 #define NRD_MAX_PE_PER_CPU U(1) 23 24 /* Boot ROM */ 25 #define NRD_CSS_SECURE_ROM_SIZE UL(0x00080000) /* 512KB */ 26 27 /* Secure SRAM */ 28 #define NRD_CSS_SECURE_SRAM_SIZE UL(0x00080000) /* 512KB */ 29 30 /* NS SRAM */ 31 #define NRD_CSS_NS_SRAM_SIZE UL(0x00080000) /* 512KB */ 32 33 /* DRAM2 */ 34 #define NRD_CSS_DRAM2_SIZE ULL(0x180000000) /* 6GB */ 35 36 #define TZC400_OFFSET UL(0x1000000) 37 38 #if (NRD_PLATFORM_VARIANT == 1) 39 #define TZC400_COUNT U(2) 40 #elif (NRD_PLATFORM_VARIANT == 2) 41 #define TZC400_COUNT U(4) 42 #else 43 #define TZC400_COUNT U(8) 44 #endif 45 46 #define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \ 47 (n * TZC400_OFFSET)) 48 49 #define TZC_NSAID_ALL_AP U(0) 50 #define TZC_NSAID_PCI U(1) 51 #define TZC_NSAID_HDLCD0 U(2) 52 #define TZC_NSAID_DMA U(5) 53 #define TZC_NSAID_DMA2 U(8) 54 #define TZC_NSAID_CLCD U(7) 55 #define TZC_NSAID_AP U(9) 56 #define TZC_NSAID_VIRTIO U(15) 57 58 #define PLAT_ARM_TZC_NS_DEV_ACCESS \ 59 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP)) | \ 60 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD0)) | \ 61 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_PCI)) | \ 62 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_DMA)) | \ 63 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_DMA2)) | \ 64 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_AP)) | \ 65 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_CLCD)) | \ 66 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIRTIO)) 67 68 /* 69 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 70 */ 71 #if (NRD_PLATFORM_VARIANT == 2) 72 #define NRD_ADDR_BITS_PER_CHIP U(46) /* 64TB */ 73 #else 74 #define NRD_ADDR_BITS_PER_CHIP U(42) /* 4TB */ 75 #endif 76 77 /* GIC SPI range for multichip */ 78 #define NRD_CHIP0_SPI_MIN U(32) 79 #define NRD_CHIP0_SPI_MAX U(511) 80 #if NRD_CHIP_COUNT > 1 81 #define NRD_CHIP1_SPI_MIN U(512) 82 #define NRD_CHIP1_SPI_MAX U(991) 83 #endif 84 #if NRD_CHIP_COUNT > 2 85 #define NRD_CHIP2_SPI_MIN U(4096) 86 #define NRD_CHIP2_SPI_MAX U(4575) 87 #endif 88 #if NRD_CHIP_COUNT > 3 89 #define NRD_CHIP3_SPI_MIN U(4576) 90 #define NRD_CHIP3_SPI_MAX U(5055) 91 #endif 92 93 #endif /* PLATFORM_DEF_H */ 94