| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | BreakFalseDeps.cpp | 125 const TargetRegisterClass *OpRC = in pickBestRegisterForUndef() local
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| D | MachineInstr.cpp | 902 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI); in getRegClassConstraintEffect() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/ |
| D | BreakFalseDeps.cpp | 136 const TargetRegisterClass *OpRC = in pickBestRegisterForUndef() local
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| D | RegAllocFast.cpp | 1109 const TargetRegisterClass *OpRC = MRI->getRegClass(Reg); in addRegClassDefCounts() local
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| D | MachineInstr.cpp | 959 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI); in getRegClassConstraintEffect() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 312 const TargetRegisterClass *OpRC = nullptr; in AddRegisterOperand() local
381 const TargetRegisterClass *OpRC = in AddOperand() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 314 const TargetRegisterClass *OpRC = nullptr; in AddRegisterOperand() local
390 const TargetRegisterClass *OpRC = in AddOperand() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIFixSGPRCopies.cpp | 794 const TargetRegisterClass *OpRC = in processPHINode() local
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| D | SIInstrInfo.cpp | 4290 const TargetRegisterClass *OpRC = RI.getSubClassWithSubReg( in legalizeGenericOperand() local
4554 const TargetRegisterClass *OpRC = in legalizeOperands() local
4616 const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg()); in legalizeOperands() local
5823 const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass); in findUsedSGPR() local
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 2236 const TargetRegisterClass *OpRC = in legalizeOperands() local
2290 const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg()); in legalizeOperands() local
3003 const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass); in findUsedSGPR() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86SpeculativeLoadHardening.cpp | 2035 auto *OpRC = MRI->getRegClass(OpReg); in hardenLoadAddr() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/ |
| D | X86SpeculativeLoadHardening.cpp | 1661 auto *OpRC = MRI->getRegClass(OpReg); in hardenLoadAddr() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| D | SIFoldOperands.cpp | 1592 const TargetRegisterClass *OpRC = in tryFoldRegSequence() local
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| D | SIInstrInfo.cpp | 5554 const TargetRegisterClass *OpRC = RI.getSubClassWithSubReg( in legalizeGenericOperand() local
5867 const TargetRegisterClass *OpRC = in legalizeOperands() local
5929 const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg()); in legalizeOperands() local
7427 const TargetRegisterClass *OpRC = in findUsedSGPR() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/GlobalISel/ |
| D | Utils.cpp | 114 const TargetRegisterClass *OpRC = TII.getRegClass(II, OpIdx, &TRI, MF); in constrainOperandRegClass() local
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| /external/llvm/lib/CodeGen/ |
| D | MachineInstr.cpp | 1246 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI); in getRegClassConstraintEffect() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonBitSimplify.cpp | 1876 auto *OpRC = HII.getRegClass(HII.get(Opc), OpNum, &HRI, MF); in validateReg() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/ |
| D | HexagonBitSimplify.cpp | 1911 auto *OpRC = HII.getRegClass(HII.get(Opc), OpNum, &HRI, MF); in validateReg() local
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