| /external/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerMIPS32.cpp | 207 void AssemblerMIPS32::emitRsRt(IValueT Opcode, const Operand *OpRs, in emitRsRt()
218 void AssemblerMIPS32::emitRtRsImm16(IValueT Opcode, const Operand *OpRt, in emitRtRsImm16()
231 void AssemblerMIPS32::emitRtRsImm16Rel(IValueT Opcode, const Operand *OpRt, in emitRtRsImm16Rel()
255 void AssemblerMIPS32::emitFtRsImm16(IValueT Opcode, const Operand *OpFt, in emitFtRsImm16()
268 void AssemblerMIPS32::emitRdRtSa(IValueT Opcode, const Operand *OpRd, in emitRdRtSa()
281 void AssemblerMIPS32::emitRdRsRt(IValueT Opcode, const Operand *OpRd, in emitRdRsRt()
295 void AssemblerMIPS32::emitCOP1Fcmp(IValueT Opcode, FPInstDataFormat Format, in emitCOP1Fcmp()
309 void AssemblerMIPS32::emitCOP1FmtFsFd(IValueT Opcode, FPInstDataFormat Format, in emitCOP1FmtFsFd()
322 void AssemblerMIPS32::emitCOP1FmtFtFsFd(IValueT Opcode, FPInstDataFormat Format, in emitCOP1FmtFtFsFd()
339 void AssemblerMIPS32::emitCOP1FmtRtFsFd(IValueT Opcode, FPInstDataFormat Format, in emitCOP1FmtRtFsFd()
[all …]
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.h | 358 bool isSALU(uint16_t Opcode) const { in isSALU()
366 bool isVALU(uint16_t Opcode) const { in isVALU()
374 bool isVMEM(uint16_t Opcode) const { in isVMEM()
382 bool isSOP1(uint16_t Opcode) const { in isSOP1()
390 bool isSOP2(uint16_t Opcode) const { in isSOP2()
398 bool isSOPC(uint16_t Opcode) const { in isSOPC()
406 bool isSOPK(uint16_t Opcode) const { in isSOPK()
414 bool isSOPP(uint16_t Opcode) const { in isSOPP()
422 bool isPacked(uint16_t Opcode) const { in isPacked()
430 bool isVOP1(uint16_t Opcode) const { in isVOP1()
[all …]
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.h | 187 bool isSALU(uint16_t Opcode) const { in isSALU()
195 bool isVALU(uint16_t Opcode) const { in isVALU()
203 bool isVMEM(uint16_t Opcode) const { in isVMEM()
211 bool isSOP1(uint16_t Opcode) const { in isSOP1()
219 bool isSOP2(uint16_t Opcode) const { in isSOP2()
227 bool isSOPC(uint16_t Opcode) const { in isSOPC()
235 bool isSOPK(uint16_t Opcode) const { in isSOPK()
243 bool isSOPP(uint16_t Opcode) const { in isSOPP()
251 bool isVOP1(uint16_t Opcode) const { in isVOP1()
259 bool isVOP2(uint16_t Opcode) const { in isVOP2()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.h | 337 bool isSALU(uint16_t Opcode) const { in isSALU()
345 bool isVALU(uint16_t Opcode) const { in isVALU()
353 bool isVMEM(uint16_t Opcode) const { in isVMEM()
361 bool isSOP1(uint16_t Opcode) const { in isSOP1()
369 bool isSOP2(uint16_t Opcode) const { in isSOP2()
377 bool isSOPC(uint16_t Opcode) const { in isSOPC()
385 bool isSOPK(uint16_t Opcode) const { in isSOPK()
393 bool isSOPP(uint16_t Opcode) const { in isSOPP()
401 bool isPacked(uint16_t Opcode) const { in isPacked()
409 bool isVOP1(uint16_t Opcode) const { in isVOP1()
[all …]
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/RISCV/ |
| D | RISCVMakeCompressible.cpp | 100 static unsigned log2LdstWidth(unsigned Opcode) { in log2LdstWidth()
119 static uint8_t compressedLDSTOffsetMask(unsigned Opcode) { in compressedLDSTOffsetMask()
125 static bool compressibleSPOffset(int64_t Offset, unsigned Opcode) { in compressibleSPOffset()
133 static int64_t getBaseAdjustForCompression(int64_t Offset, unsigned Opcode) { in getBaseAdjustForCompression()
148 const unsigned Opcode = MI.getOpcode(); in isCompressibleLoad() local
157 const unsigned Opcode = MI.getOpcode(); in isCompressibleStore() local
176 const unsigned Opcode = MI.getOpcode(); in getRegImmPairPreventingCompression() local
289 unsigned Opcode = MI.getOpcode(); in updateOperands() local
368 unsigned Opcode = RISCV::FPR32RegClass.contains(RegImm.Reg) in runOnMachineFunction() local
|
| /external/llvm/lib/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.cpp | 59 MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, Type *Ty) { in buildInstr()
72 MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, unsigned Res, in buildInstr()
77 MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, Type *Ty, in buildInstr()
88 MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, unsigned Res, in buildInstr()
95 MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode) { in buildInstr()
99 MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, Type *Ty, in buildInstr()
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.h | 146 static inline bool isSPLSOpcode(unsigned Opcode) { in isSPLSOpcode()
160 static inline bool isRMOpcode(unsigned Opcode) { in isRMOpcode()
170 static inline bool isRRMOpcode(unsigned Opcode) { in isRRMOpcode()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.h | 145 static inline bool isSPLSOpcode(unsigned Opcode) { in isSPLSOpcode()
159 static inline bool isRMOpcode(unsigned Opcode) { in isRMOpcode()
169 static inline bool isRRMOpcode(unsigned Opcode) { in isRRMOpcode()
|
| /external/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.h | 141 static inline bool isSPLSOpcode(unsigned Opcode) { in isSPLSOpcode()
155 static inline bool isRMOpcode(unsigned Opcode) { in isRMOpcode()
165 static inline bool isRRMOpcode(unsigned Opcode) { in isRRMOpcode()
|
| /external/swiftshader/third_party/llvm-16.0/llvm/include/llvm/CodeGen/ |
| D | TargetOpcodes.h | 30 inline bool isPreISelGenericOpcode(unsigned Opcode) { in isPreISelGenericOpcode()
36 inline bool isTargetSpecificOpcode(unsigned Opcode) { in isTargetSpecificOpcode()
42 inline bool isPreISelGenericOptimizationHint(unsigned Opcode) { in isPreISelGenericOptimizationHint()
|
| /external/llvm/tools/llvm-readobj/ |
| D | ARMEHABIPrinter.h | 97 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_00xxxxxx() local
102 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_01xxxxxx() local
120 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10011101() local
124 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10011111() local
128 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_1001nnnn() local
132 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10100nnn() local
138 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10101nnn() local
144 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10110000() local
161 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10110010_uleb128() local
187 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_101101nn() local
[all …]
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/SystemZ/ |
| D | SystemZShortenInst.cpp | 110 bool SystemZShortenInst::shortenOn0(MachineInstr &MI, unsigned Opcode) { in shortenOn0()
120 bool SystemZShortenInst::shortenOn01(MachineInstr &MI, unsigned Opcode) { in shortenOn01()
132 bool SystemZShortenInst::shortenOn001(MachineInstr &MI, unsigned Opcode) { in shortenOn001()
145 bool SystemZShortenInst::shortenOn001AddCC(MachineInstr &MI, unsigned Opcode) { in shortenOn001AddCC()
158 bool SystemZShortenInst::shortenFPConv(MachineInstr &MI, unsigned Opcode) { in shortenFPConv()
180 bool SystemZShortenInst::shortenFusedFPOp(MachineInstr &MI, unsigned Opcode) { in shortenFusedFPOp()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMTargetTransformInfo.cpp | 53 int ARMTTIImpl::getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, in getIntImmCodeSizeCost()
61 int ARMTTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, in getIntImmCost()
76 int ARMTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) { in getCastInstrCost()
269 int ARMTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy, in getVectorInstrCost()
294 int ARMTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy) { in getCmpSelInstrCost()
412 unsigned Opcode, Type *Ty, TTI::OperandValueKind Op1Info, in getArithmeticInstrCost()
483 int ARMTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, in getMemoryOpCost()
496 int ARMTTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, in getInterleavedMemoryOpCost()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMUnwindOpAsm.h | 72 void EmitInt8(unsigned Opcode) { in EmitInt8()
77 void EmitInt16(unsigned Opcode) { in EmitInt16()
83 void EmitBytes(const uint8_t *Opcode, size_t Size) { in EmitBytes()
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMUnwindOpAsm.h | 72 void EmitInt8(unsigned Opcode) { in EmitInt8()
77 void EmitInt16(unsigned Opcode) { in EmitInt16()
83 void emitBytes(const uint8_t *Opcode, size_t Size) { in emitBytes()
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMUnwindOpAsm.h | 74 void EmitInt8(unsigned Opcode) { in EmitInt8()
79 void EmitInt16(unsigned Opcode) { in EmitInt16()
85 void EmitBytes(const uint8_t *Opcode, size_t Size) { in EmitBytes()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCTargetTransformInfo.cpp | 108 int PPCTTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, in getIntImmCost()
281 unsigned Opcode, Type *Ty, TTI::OperandValueKind Op1Info, in getArithmeticInstrCost()
304 int PPCTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) { in getCastInstrCost()
310 int PPCTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy) { in getCmpSelInstrCost()
314 int PPCTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) { in getVectorInstrCost()
353 int PPCTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, in getMemoryOpCost()
410 int PPCTTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, in getInterleavedMemoryOpCost()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZShortenInst.cpp | 108 bool SystemZShortenInst::shortenOn0(MachineInstr &MI, unsigned Opcode) { in shortenOn0()
118 bool SystemZShortenInst::shortenOn01(MachineInstr &MI, unsigned Opcode) { in shortenOn01()
130 bool SystemZShortenInst::shortenOn001(MachineInstr &MI, unsigned Opcode) { in shortenOn001()
143 bool SystemZShortenInst::shortenOn001AddCC(MachineInstr &MI, unsigned Opcode) { in shortenOn001AddCC()
156 bool SystemZShortenInst::shortenFPConv(MachineInstr &MI, unsigned Opcode) { in shortenFPConv()
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZAsmPrinter.cpp | 31 static MCInst lowerRILow(const MachineInstr *MI, unsigned Opcode) { in lowerRILow()
45 static MCInst lowerRIHigh(const MachineInstr *MI, unsigned Opcode) { in lowerRIHigh()
59 static MCInst lowerRIEfLow(const MachineInstr *MI, unsigned Opcode) { in lowerRIEfLow()
85 static MCInst lowerSubvectorLoad(const MachineInstr *MI, unsigned Opcode) { in lowerSubvectorLoad()
95 static MCInst lowerSubvectorStore(const MachineInstr *MI, unsigned Opcode) { in lowerSubvectorStore()
|
| D | SystemZShortenInst.cpp | 109 bool SystemZShortenInst::shortenOn0(MachineInstr &MI, unsigned Opcode) { in shortenOn0()
119 bool SystemZShortenInst::shortenOn01(MachineInstr &MI, unsigned Opcode) { in shortenOn01()
131 bool SystemZShortenInst::shortenOn001(MachineInstr &MI, unsigned Opcode) { in shortenOn001()
144 bool SystemZShortenInst::shortenOn001AddCC(MachineInstr &MI, unsigned Opcode) { in shortenOn001AddCC()
157 bool SystemZShortenInst::shortenFPConv(MachineInstr &MI, unsigned Opcode) { in shortenFPConv()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCPredicates.cpp | 18 PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) { in InvertPredicate()
52 PPC::Predicate PPC::getSwappedPredicate(PPC::Predicate Opcode) { in getSwappedPredicate()
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCPredicates.cpp | 18 PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) { in InvertPredicate()
52 PPC::Predicate PPC::getSwappedPredicate(PPC::Predicate Opcode) { in getSwappedPredicate()
|
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCPredicates.cpp | 19 PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) { in InvertPredicate()
53 PPC::Predicate PPC::getSwappedPredicate(PPC::Predicate Opcode) { in getSwappedPredicate()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64TargetTransformInfo.cpp | 64 int AArch64TTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, in getIntImmCost()
179 int AArch64TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) { in getCastInstrCost()
294 int AArch64TTIImpl::getExtractWithExtendCost(unsigned Opcode, Type *Dst, in getExtractWithExtendCost()
349 int AArch64TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, in getVectorInstrCost()
375 unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info, in getArithmeticInstrCost()
435 int AArch64TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, in getCmpSelInstrCost()
466 int AArch64TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, in getMemoryOpCost()
495 int AArch64TTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, in getInterleavedMemoryOpCost()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonTargetTransformInfo.cpp | 154 unsigned HexagonTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, in getMemoryOpCost()
201 unsigned HexagonTTIImpl::getMaskedMemoryOpCost(unsigned Opcode, in getMaskedMemoryOpCost()
211 unsigned HexagonTTIImpl::getGatherScatterOpCost(unsigned Opcode, Type *DataTy, in getGatherScatterOpCost()
217 unsigned HexagonTTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, in getInterleavedMemoryOpCost()
229 unsigned HexagonTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, in getCmpSelInstrCost()
240 unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info, in getArithmeticInstrCost()
253 unsigned HexagonTTIImpl::getCastInstrCost(unsigned Opcode, Type *DstTy, in getCastInstrCost()
266 unsigned HexagonTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, in getVectorInstrCost()
|