1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef SOC_MEDIATEK_USB_COMMON_H 4 #define SOC_MEDIATEK_USB_COMMON_H 5 6 #include <stddef.h> 7 #include <stdint.h> 8 9 /* ip_pw_ctrl0 */ 10 #define CTRL0_IP_SW_RST (0x1 << 0) 11 12 /* ip_pw_ctrl1 */ 13 #define CTRL1_IP_HOST_PDN (0x1 << 0) 14 15 /* ip_pw_sts1 */ 16 #define STS1_U3_MAC_RST (0x1 << 16) 17 #define STS1_SYS125_RST (0x1 << 10) 18 #define STS1_REF_RST (0x1 << 8) 19 #define STS1_SYSPLL_STABLE (0x1 << 0) 20 21 /* ip_pw_sts2 */ 22 #define STS2_U2_MAC_RST (0x1 << 0) 23 24 /* ip_xhci_cap */ 25 #define CAP_U3_PORT_NUM(p) ((p) & 0xff) 26 #define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff) 27 28 /* u3_ctrl_p */ 29 #define CTRL_U3_PORT_HOST_SEL (0x1 << 2) 30 #define CTRL_U3_PORT_PDN (0x1 << 1) 31 #define CTRL_U3_PORT_DIS (0x1 << 0) 32 33 /* u2_ctrl_p */ 34 #define CTRL_U2_PORT_HOST_SEL (0x1 << 2) 35 #define CTRL_U2_PORT_PDN (0x1 << 1) 36 #define CTRL_U2_PORT_DIS (0x1 << 0) 37 38 struct ssusb_ippc_regs { 39 u32 ip_pw_ctr0; 40 u32 ip_pw_ctr1; 41 u32 ip_pw_ctr2; 42 u32 ip_pw_ctr3; 43 u32 ip_pw_sts1; 44 u32 ip_pw_sts2; 45 u32 reserved0[3]; 46 u32 ip_xhci_cap; 47 u32 reserved1[2]; 48 u64 u3_ctrl_p[4]; 49 u64 u2_ctrl_p[6]; 50 }; 51 52 /* U2PHY_COM USBPHYACR5 */ 53 #define PA5_RG_U2_HSTX_SRCTRL (0x7 << 12) 54 #define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12) 55 #define PA5_RG_U2_HS_100U_U3_EN (0x1 << 11) 56 57 /* U2PHY_COM USBPHYACR6 */ 58 #define PA6_RG_U2_ISO_EN (0x1 << 31) 59 #define PA6_RG_U2_BC11_SW_EN (0x1 << 23) 60 #define PA6_RG_U2_OTG_VBUSCMP_EN (0x1 << 20) 61 #define PA6_RG_U2_DISCTH (0xf << 4) 62 #define PA6_RG_U2_DISCTH_VAL(x) ((0xf & (x)) << 4) 63 #define PA6_RG_U2_SQTH (0xf << 0) 64 #define PA6_RG_U2_SQTH_VAL(x) ((0xf & (x)) << 0) 65 66 /* U2PHY_COM U2PHYACR4 */ 67 #define P2C_RG_USB20_GPIO_CTL (0x1 << 9) 68 #define P2C_USB20_GPIO_MODE (0x1 << 8) 69 #define P2C_U2_GPIO_CTR_MSK (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE) 70 71 /* U2PHY_COM U2PHYDTM0 */ 72 #define P2C_FORCE_UART_EN (0x1 << 26) 73 #define P2C_FORCE_DATAIN (0x1 << 23) 74 #define P2C_FORCE_DM_PULLDOWN (0x1 << 21) 75 #define P2C_FORCE_DP_PULLDOWN (0x1 << 20) 76 #define P2C_FORCE_XCVRSEL (0x1 << 19) 77 #define P2C_FORCE_SUSPENDM (0x1 << 18) 78 #define P2C_FORCE_TERMSEL (0x1 << 17) 79 #define P2C_RG_DATAIN (0xf << 10) 80 #define P2C_RG_DATAIN_VAL(x) ((0xf & (x)) << 10) 81 #define P2C_RG_DMPULLDOWN (0x1 << 7) 82 #define P2C_RG_DPPULLDOWN (0x1 << 6) 83 #define P2C_RG_XCVRSEL (0x3 << 4) 84 #define P2C_RG_XCVRSEL_VAL(x) ((0x3 & (x)) << 4) 85 #define P2C_RG_SUSPENDM (0x1 << 3) 86 #define P2C_RG_TERMSEL (0x1 << 2) 87 #define P2C_DTM0_PART_MASK \ 88 (P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \ 89 P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \ 90 P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \ 91 P2C_RG_TERMSEL) 92 93 /* U2PHY_COM U2PHYDTM1 */ 94 #define P2C_RG_UART_EN (0x1 << 16) 95 #define P2C_RG_VBUSVALID (0x1 << 5) 96 #define P2C_RG_SESSEND (0x1 << 4) 97 #define P2C_RG_AVALID (0x1 << 2) 98 99 /* U3PHYA PHYA_REG0 */ 100 #define P3A_RG_U3_VUSB10_ON (1 << 5) 101 102 /* U3PHYA PHYA_REG6 */ 103 #define P3A_RG_TX_EIDLE_CM (0xf << 28) 104 #define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28) 105 106 /* U3PHYA PHYA_REG9 */ 107 #define P3A_RG_RX_DAC_MUX (0x1f << 1) 108 #define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1) 109 110 /* U3PHYA_DA REG0 */ 111 #define P3A_RG_XTAL_EXT_EN_U3 (0x3 << 10) 112 #define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10) 113 114 /* U3PHYD CDR1 */ 115 #define P3D_RG_CDR_BIR_LTD1 (0x1f << 24) 116 #define P3D_RG_CDR_BIR_LTD1_VAL(x) ((0x1f & (x)) << 24) 117 #define P3D_RG_CDR_BIR_LTD0 (0x1f << 8) 118 #define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8) 119 120 struct sif_u2_phy_com { 121 u32 reserved0[5]; 122 u32 usbphyacr5; 123 u32 usbphyacr6; 124 u32 u2phyacr3; 125 u32 u2phyacr4; 126 u32 reserved1[17]; 127 u32 u2phydtm0; 128 u32 u2phydtm1; 129 u32 reserved2[36]; /* 0x70 - 0xff */ 130 }; 131 check_member(sif_u2_phy_com, u2phydtm0, 0x68); 132 133 struct sif_u3phyd { 134 u32 reserved0[4]; 135 u32 phyd_cal0; 136 u32 phyd_cal1; 137 u32 reserved1[15]; 138 u32 phyd_reserved; 139 u32 phyd_cdr1; 140 u32 reserved2[41]; 141 }; 142 143 struct sif_u3phya { 144 u32 phya_reg0; 145 u32 reserved0[5]; 146 u32 phya_reg6; 147 u32 reserved1[2]; 148 u32 phya_reg9; 149 u32 reserved2[54]; 150 }; 151 152 struct sif_u3phya_da { 153 u32 reg0; 154 u32 reserved[63]; 155 }; 156 157 /* 158 * This is defined as weak no-ops that can be overridden by legacy SOCs. Some 159 * legacy SOCs need specific settings before init USB. And we expect future 160 * SOCs will not need it. 161 */ 162 void mtk_usb_prepare(void); 163 void mtk_usb_adjust_phy_shift(void); 164 165 void setup_usb_host(void); 166 void update_usb_base_regs(uintptr_t ippc_base, uintptr_t sif_base); 167 void setup_usb_secondary_host(void); 168 void setup_usb_host_controller(void); 169 #endif 170