1 /* 2 * Copyright (c) 2024, Rockchip, Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PMU_H__ 8 #define __PMU_H__ 9 10 #include <lib/mmio.h> 11 12 #define PMU0_PWR_CON 0x0000 13 #define PMU0_WAKEUP_INT_CON 0x0008 14 #define PMU0_WAKEUP_INT_ST 0x000c 15 #define PMU0_PMIC_STABLE_CNT_THRES 0x0010 16 #define PMU0_WAKEUP_RST_CLR_CNT_THRES 0x0014 17 #define PMU0_OSC_STABLE_CNT_THRES 0x0018 18 #define PMU0_PWR_CHAIN_STABLE_CON 0x001c 19 #define PMU0_DDR_RET_CON(i) (0x0020 + (i) * 4) 20 #define PMU0_INFO_TX_CON 0x0030 21 22 #define PMU1_VERSION_ID 0x4000 23 #define PMU1_PWR_CON 0x4004 24 #define PMU1_PWR_FSM 0x4008 25 #define PMU1_INT_MASK_CON 0x400c 26 #define PMU1_WAKEUP_INT_CON 0x4010 27 #define PMU1_WAKEUP_INT_ST 0x4014 28 #define PMU1_WAKEUP_EDGE_CON 0x4018 29 #define PMU1_WAKEUP_EDGE_ST 0x401c 30 #define PMU1_DDR_PWR_CON(i) (0x4020 + (i) * 4) 31 #define PMU1_DDR_PWR_SFTCON(i) (0x4030 + (i) * 4) 32 #define PMU1_DDR_PWR_FSM 0x4040 33 #define PMU1_DDR_PWR_ST 0x4044 34 #define PMU1_CRU_PWR_CON 0x4050 35 #define PMU1_CRU_PWR_SFTCON 0x4054 36 #define PMU1_CRU_PWR_FSM 0x4058 37 #define PMU1_PLLPD_CON(i) (0x4060 + (i) * 4) 38 #define PMU1_PLLPD_SFTCON(i) (0x4068 + (i) * 4) 39 #define PMU1_STABLE_CNT_THRESH 0x4080 40 #define PMU1_OSC_STABLE_CNT_THRESH 0x4084 41 #define PMU1_WAKEUP_RST_CLR_CNT_THRESH 0x4088 42 #define PMU1_PLL_LOCK_CNT_THRESH 0x408c 43 #define PMU1_WAKEUP_TIMEOUT_THRESH 0x4094 44 #define PMU1_PWM_SWITCH_CNT_THRESH 0x4098 45 #define PMU1_SYS_REG(i) (0x4100 + (i) * 4) 46 47 #define PMU2_PWR_CON1 0x8000 48 #define PMU2_DSU_PWR_CON 0x8004 49 #define PMU2_DSU_PWR_SFTCON 0x8008 50 #define PMU2_DSU_AUTO_PWR_CON 0x800c 51 #define PMU2_CPU_AUTO_PWR_CON(i) (0x8010 + (i) * 4) 52 #define PMU2_CPU_PWR_SFTCON(i) (0x8030 + (i) * 4) 53 #define PMU2_CORE_PWR_CON(i) (0x8050 + (i) * 4) 54 #define PMU2_CORE_PWR_SFTCON(i) (0x8058 + (i) * 4) 55 #define PMU2_CORE_AUTO_PWR_CON(i) (0x8060 + (i) * 4) 56 #define PMU2_CLUSTER_NOC_AUTO_CON 0x8068 57 #define PMU2_CLUSTER_DBG_PWR_CON 0x806c 58 #define PMU2_CLUSTER_IDLE_CON 0x8070 59 #define PMU2_CLUSTER_IDLE_SFTCON 0x8074 60 #define PMU2_CLUSTER_IDLE_ACK 0x8078 61 #define PMU2_CLUSTER_IDLE_ST 0x807c 62 #define PMU2_CLUSTER_ST 0x8080 63 #define PMU2_SCU_PWR_FSM_STATUS(i) (0x8084 + (i) * 4) 64 #define PMU2_CORE_PCHANNEL_STATUS(i) (0x808c + (i) * 4) 65 #define PMU2_CPU_PWR_CHAIN_STABLE_CON 0x8098 66 #define PMU2_CLUSTER_MEMPWR_GATE_SFTCON 0x809c 67 #define PMU2_DSU_STABLE_CNT_THRESH 0x80b0 68 #define PMU2_DSU_PWRUP_CNT_THRESH 0x80b4 69 #define PMU2_DSU_PWRDN_CNT_THRESH 0x80b8 70 #define PMU2_CORE0_STABLE_CNT_THRESH 0x80bc 71 #define PMU2_CORE0_PWRUP_CNT_THRESH 0x80c0 72 #define PMU2_CORE0_PWRDN_CNT_THRESH 0x80c4 73 #define PMU2_CORE1_STABLE_CNT_THRESH 0x80c8 74 #define PMU2_CORE1_PWRUP_CNT_THRESH 0x80cc 75 #define PMU2_CORE1_PWRDN_CNT_THRESH 0x80d0 76 #define PMU2_DBG_RST_CNT_THRESH(i) (0x80d4 + (i) * 4) 77 #define PMU2_BUS_IDLE_CON(i) (0x8100 + (i) * 4) 78 #define PMU2_BUS_IDLE_SFTCON(i) (0x810c + (i) * 4) 79 #define PMU2_BUS_IDLE_ACK(i) (0x8118 + (i) * 4) 80 #define PMU2_BUS_IDLE_ST(i) (0x8120 + (i) * 4) 81 #define PMU2_BIU_AUTO_CON(i) (0x8128 + (i) * 4) 82 #define PMU2_PWR_GATE_CON(i) (0x8140 + (i) * 4) 83 #define PMU2_PWR_GATE_SFTCON(i) (0x814c + (i) * 4) 84 #define PMU2_VOL_GATE_CON(i) (0x8158 + (i) * 4) 85 #define PMU2_PWR_UP_CHAIN_STABLE_CON(i) (0x8164 + (i) * 4) 86 #define PMU2_PWR_DWN_CHAIN_STABLE_CON(i)(0x8170 + (i) * 4) 87 #define PMU2_PWR_STABLE_CHAIN_CNT_THRES 0x817c 88 #define PMU2_PWR_GATE_ST(i) (0x8180 + (i) * 4) 89 #define PMU2_PWR_GATE_FSM 0x8188 90 #define PMU2_VOL_GATE_FAST_CON 0x818c 91 #define PMU2_GPU_PWRUP_CNT 0x8190 92 #define PMU2_GPU_PWRDN_CNT 0x8194 93 #define PMU2_NPU_PWRUP_CNT 0x8198 94 #define PMU2_NPU_PWRDN_CNT 0x819c 95 #define PMU2_MEMPWR_GATE_SFTCON(i) (0x81a0 + (i) * 4) 96 #define PMU2_MEMPWR_MD_GATE_SFTCON(i) (0x81b0 + (i) * 4) 97 #define PMU2_MEMPWR_MD_GATE_STATUS 0x81bc 98 #define PMU2_SUBMEM_PWR_ACK_BYPASS(i) (0x81c0 + (i) * 4) 99 #define PMU2_QCHANNEL_PWR_CON 0x81d0 100 #define PMU2_QCHANNEL_PWR_SFTCON 0x81d4 101 #define PMU2_QCHANNEL_STATUS 0x81d8 102 #define PMU2_DEBUG_INFO_SEL 0x81e0 103 #define PMU2_VOP_SUBPD_STATE 0x81e4 104 #define PMU2_PWR_CHAIN0_ST(i) (0x81e8 + (i) * 4) 105 #define PMU2_PWR_CHAIN1_ST(i) (0x81f0 + (i) * 4) 106 #define PMU2_PWR_MEM_ST(i) (0x81f8 + (i) * 4) 107 #define PMU2_BISR_CON(i) (0x8200 + (i) * 4) 108 #define PMU2_BISR_STATUS(i) (0x8280 + (i) * 4) 109 110 #define PMU2_QCH_PWR_MSK 0x7f 111 112 #define PD_CTR_LOOP 500 113 #define PD_CHECK_LOOP 500 114 #define WFEI_CHECK_LOOP 500 115 #define BUS_IDLE_LOOP 1000 116 #define QCH_PWR_LOOP 5000 117 118 /* PMU1SCRU */ 119 #define PMU1SCRU_GATE_CON(i) (0x800 + (i) * 4) 120 121 /* PMU_GRF */ 122 #define PMU0_GRF_SOC_CON(i) ((i) * 4) 123 #define PMU0_GRF_OS_REGS(i) (0x80 + ((i) - 8) * 4) 124 #define PMU1_GRF_SOC_CON(i) ((i) * 4) 125 #define PMU0_GRF_IO_RET_CON(i) (0x20 + (i) * 4) 126 127 /* PMU_SGRF */ 128 #define PMU0_SGRF_SOC_CON(i) ((i) * 4) 129 #define PMU1_SGRF_SOC_CON(i) ((i) * 4) 130 131 /* sys grf */ 132 #define GRF_CPU_STATUS0 0x0420 133 134 #define CORES_PM_DISABLE 0x0 135 #define PD_CHECK_LOOP 500 136 #define WFEI_CHECK_LOOP 500 137 138 /* The ways of cores power domain contorlling */ 139 enum cores_pm_ctr_mode { 140 core_pwr_pd = 0, 141 core_pwr_wfi = 1, 142 core_pwr_wfi_int = 2 143 }; 144 145 /* PMU0_PWR_CON */ 146 enum pmu0_pwr_con { 147 pmu0_powermode_en = 0, 148 pmu0_pmu1_pwr_bypass = 1, 149 pmu0_pmu1_bus_bypass = 2, 150 pmu0_wkup_bypass = 3, 151 pmu0_pmic_bypass = 4, 152 pmu0_reset_bypass = 5, 153 pmu0_freq_sw_bypass = 6, 154 pmu0_osc_dis_bypass = 7, 155 pmu0_pmu1_pwr_gt_en = 8, 156 pmu0_pmu1_pwr_gt_sft_en = 9, 157 pmu0_pmu1_mem_gt_sft_en = 10, 158 pmu0_pmu1_bus_idle_en = 11, 159 pmu0_pmu1_bus_idle_sft_en = 12, 160 pmu0_pmu1_biu_auto_en = 13, 161 pmu0_pwr_off_io_en = 14, 162 }; 163 164 /* PMU1_PWR_CON */ 165 enum pmu1_pwr_con { 166 powermode_en = 0, 167 dsu_bypass = 1, 168 bus_bypass = 4, 169 ddr_bypass = 5, 170 pwrdn_bypass = 6, 171 cru_bypass = 7, 172 qch_bypass = 8, 173 core_bypass = 9, 174 cpu_sleep_wfi_dis = 12, 175 }; 176 177 /* PMU1_DDR_PWR_CON */ 178 enum pmu1_ddr_pwr_con { 179 ddr_sref_en = 0, 180 ddr_sref_a_en = 1, 181 ddrio_ret_en = 2, 182 ddrio_ret_exit_en = 5, 183 ddrio_rstiov_en = 6, 184 ddrio_rstiov_exit_en = 7, 185 ddr_gating_a_en = 8, 186 ddr_gating_c_en = 9, 187 ddr_gating_p_en = 10, 188 }; 189 190 /* PMU_CRU_PWR_CON */ 191 enum pmu1_cru_pwr_con { 192 alive_32k_en = 0, 193 osc_dis_en = 1, 194 wakeup_rst_en = 2, 195 input_clamp_en = 3, 196 alive_osc_mode_en = 4, 197 power_off_en = 5, 198 pwm_switch_en = 6, 199 pwm_gpio_ioe_en = 7, 200 pwm_switch_io = 8, 201 pd_clk_src_gate_en = 9, 202 }; 203 204 /* PMU_PLLPD_CON */ 205 enum pmu1_pllpd_con { 206 B0PLL_PD_EN, 207 B1PLL_PD_EN, 208 LPLL_PD_EN, 209 D0APLL_PD_EN, 210 D0BPLL_PD_EN, 211 D1APLL_PD_EN, 212 D1BPLL_PD_EN, 213 D2APLL_PD_EN, 214 D2BPLL_PD_EN, 215 D3APLL_PD_EN, 216 D3BPLL_PD_EN, 217 V0PLL_PD_EN, 218 AUPLL_PD_EN, 219 GPLL_PD_EN, 220 CPLL_PD_EN, 221 NPLL_PD_EN, 222 PPLL_PD_EN = 0, 223 SPLL_PD_EN = 1, 224 }; 225 226 enum pmu1_wakeup_int { 227 WAKEUP_CPU0_INT_EN, 228 WAKEUP_CPU1_INT_EN, 229 WAKEUP_CPU2_INT_EN, 230 WAKEUP_CPU3_INT_EN, 231 WAKEUP_CPU4_INT_EN, 232 WAKEUP_CPU5_INT_EN, 233 WAKEUP_CPU6_INT_EN, 234 WAKEUP_CPU7_INT_EN, 235 WAKEUP_GPIO0_INT_EN, 236 WAKEUP_SDMMC_EN, 237 WAKEUP_SDIO_EN, 238 WAKEUP_USBDEV_EN, 239 WAKEUP_UART0_EN, 240 WAKEUP_VAD_EN, 241 WAKEUP_TIMER_EN, 242 WAKEUP_SOC_INT_EN, 243 WAKEUP_TIMEROUT_EN, 244 WAKEUP_PMUMCU_CEC_EN = 20, 245 }; 246 247 enum pmu2_dsu_auto_pwr_con { 248 dsu_pm_en = 0, 249 dsu_pm_int_wakeup_en = 1, 250 dsu_pm_sft_wakeup_en = 3, 251 }; 252 253 enum pmu2_cpu_auto_pwr_con { 254 cpu_pm_en = 0, 255 cpu_pm_int_wakeup_en = 1, 256 cpu_pm_sft_wakeup_en = 3, 257 }; 258 259 enum pmu2_core_auto_pwr_con { 260 core_pm_en = 0, 261 core_pm_int_wakeup_en = 1, 262 core_pm_int_wakeup_glb_msk = 2, 263 core_pm_sft_wakeup_en = 3, 264 }; 265 266 enum pmu2_dsu_power_con { 267 DSU_PWRDN_EN, 268 DSU_PWROFF_EN, 269 BIT_FULL_EN, 270 DSU_RET_EN, 271 CLUSTER_CLK_SRC_GT_EN, 272 }; 273 274 enum pmu2_core_power_con { 275 CORE_PWRDN_EN, 276 CORE_PWROFF_EN, 277 CORE_CPU_PWRDN_EN, 278 CORE_PWR_CNT_EN, 279 }; 280 281 enum pmu2_cluster_idle_con { 282 IDLE_REQ_BIGCORE0_EN = 0, 283 IDLE_REQ_BIGCORE1_EN = 2, 284 IDLE_REQ_DSU_EN = 4, 285 IDLE_REQ_LITDSU_EN = 5, 286 IDLE_REQ_ADB400_CORE_QCH_EN = 6, 287 }; 288 289 enum qos_id { 290 QOS_ISP0_MWO = 0, 291 QOS_ISP0_MRO = 1, 292 QOS_ISP1_MWO = 2, 293 QOS_ISP1_MRO = 3, 294 QOS_VICAP_M0 = 4, 295 QOS_VICAP_M1 = 5, 296 QOS_FISHEYE0 = 6, 297 QOS_FISHEYE1 = 7, 298 QOS_VOP_M0 = 8, 299 QOS_VOP_M1 = 9, 300 QOS_RKVDEC0 = 10, 301 QOS_RKVDEC1 = 11, 302 QOS_AV1 = 12, 303 QOS_RKVENC0_M0RO = 13, 304 QOS_RKVENC0_M1RO = 14, 305 QOS_RKVENC0_M2WO = 15, 306 QOS_RKVENC1_M0RO = 16, 307 QOS_RKVENC1_M1RO = 17, 308 QOS_RKVENC1_M2WO = 18, 309 QOS_DSU_M0 = 19, 310 QOS_DSU_M1 = 20, 311 QOS_DSU_MP = 21, 312 QOS_DEBUG = 22, 313 QOS_GPU_M0 = 23, 314 QOS_GPU_M1 = 24, 315 QOS_GPU_M2 = 25, 316 QOS_GPU_M3 = 26, 317 QOS_NPU1 = 27, 318 QOS_NPU0_MRO = 28, 319 QOS_NPU2 = 29, 320 QOS_NPU0_MWR = 30, 321 QOS_MCU_NPU = 31, 322 QOS_JPEG_DEC = 32, 323 QOS_JPEG_ENC0 = 33, 324 QOS_JPEG_ENC1 = 34, 325 QOS_JPEG_ENC2 = 35, 326 QOS_JPEG_ENC3 = 36, 327 QOS_RGA2_MRO = 37, 328 QOS_RGA2_MWO = 38, 329 QOS_RGA3_0 = 39, 330 QOS_RGA3_1 = 40, 331 QOS_VDPU = 41, 332 QOS_IEP = 42, 333 QOS_HDCP0 = 43, 334 QOS_HDCP1 = 44, 335 QOS_HDMIRX = 45, 336 QOS_GIC600_M0 = 46, 337 QOS_GIC600_M1 = 47, 338 QOS_MMU600PCIE_TCU = 48, 339 QOS_MMU600PHP_TBU = 49, 340 QOS_MMU600PHP_TCU = 50, 341 QOS_USB3_0 = 51, 342 QOS_USB3_1 = 52, 343 QOS_USBHOST_0 = 53, 344 QOS_USBHOST_1 = 54, 345 QOS_EMMC = 55, 346 QOS_FSPI = 56, 347 QOS_SDIO = 57, 348 QOS_DECOM = 58, 349 QOS_DMAC0 = 59, 350 QOS_DMAC1 = 60, 351 QOS_DMAC2 = 61, 352 QOS_GIC600M = 62, 353 QOS_DMA2DDR = 63, 354 QOS_MCU_DDR = 64, 355 QOS_VAD = 65, 356 QOS_MCU_PMU = 66, 357 QOS_CRYPTOS = 67, 358 QOS_CRYPTONS = 68, 359 QOS_DCF = 69, 360 QOS_SDMMC = 70, 361 }; 362 363 enum pmu2_pdid { 364 PD_GPU = 0, 365 PD_NPU = 1, 366 PD_VCODEC = 2, 367 PD_NPUTOP = 3, 368 PD_NPU1 = 4, 369 PD_NPU2 = 5, 370 PD_VENC0 = 6, 371 PD_VENC1 = 7, 372 PD_RKVDEC0 = 8, 373 PD_RKVDEC1 = 9, 374 PD_VDPU = 10, 375 PD_RGA30 = 11, 376 PD_AV1 = 12, 377 PD_VI = 13, 378 PD_FEC = 14, 379 PD_ISP1 = 15, 380 PD_RGA31 = 16, 381 PD_VOP = 17, 382 PD_VO0 = 18, 383 PD_VO1 = 19, 384 PD_AUDIO = 20, 385 PD_PHP = 21, 386 PD_GMAC = 22, 387 PD_PCIE = 23, 388 PD_NVM = 24, 389 PD_NVM0 = 25, 390 PD_SDIO = 26, 391 PD_USB = 27, 392 PD_SECURE = 28, 393 PD_SDMMC = 29, 394 PD_CRYPTO = 30, 395 PD_CENTER = 31, 396 PD_DDR01 = 32, 397 PD_DDR23 = 33, 398 }; 399 400 enum pmu2_pd_repair_id { 401 PD_RPR_PMU = 0, 402 PD_RPR_GPU = 1, 403 PD_RPR_NPUTOP = 2, 404 PD_RPR_NPU1 = 3, 405 PD_RPR_NPU2 = 4, 406 PD_RPR_VENC0 = 5, 407 PD_RPR_VENC1 = 6, 408 PD_RPR_RKVDEC0 = 7, 409 PD_RPR_RKVDEC1 = 8, 410 PD_RPR_VDPU = 9, 411 PD_RPR_RGA30 = 10, 412 PD_RPR_AV1 = 11, 413 PD_RPR_VI = 12, 414 PD_RPR_FEC = 13, 415 PD_RPR_ISP1 = 14, 416 PD_RPR_RGA31 = 15, 417 PD_RPR_VOP = 16, 418 PD_RPR_VO0 = 17, 419 PD_RPR_VO1 = 18, 420 PD_RPR_AUDIO = 19, 421 PD_RPR_PHP = 20, 422 PD_RPR_GMAC = 21, 423 PD_RPR_PCIE = 22, 424 PD_RPR_NVM0 = 23, 425 PD_RPR_SDIO = 24, 426 PD_RPR_USB = 25, 427 PD_RPR_SDMMC = 26, 428 PD_RPR_CRYPTO = 27, 429 PD_RPR_CENTER = 28, 430 PD_RPR_DDR01 = 29, 431 PD_RPR_DDR23 = 30, 432 PD_RPR_BUS = 31, 433 }; 434 435 enum pmu2_bus_id { 436 BUS_ID_GPU = 0, 437 BUS_ID_NPUTOP = 1, 438 BUS_ID_NPU1 = 2, 439 BUS_ID_NPU2 = 3, 440 BUS_ID_RKVENC0 = 4, 441 BUS_ID_RKVENC1 = 5, 442 BUS_ID_RKVDEC0 = 6, 443 BUS_ID_RKVDEC1 = 7, 444 BUS_ID_VDPU = 8, 445 BUS_ID_AV1 = 9, 446 BUS_ID_VI = 10, 447 BUS_ID_ISP = 11, 448 BUS_ID_RGA31 = 12, 449 BUS_ID_VOP = 13, 450 BUS_ID_VOP_CHANNEL = 14, 451 BUS_ID_VO0 = 15, 452 BUS_ID_VO1 = 16, 453 BUS_ID_AUDIO = 17, 454 BUS_ID_NVM = 18, 455 BUS_ID_SDIO = 19, 456 BUS_ID_USB = 20, 457 BUS_ID_PHP = 21, 458 BUS_ID_VO1USBTOP = 22, 459 BUS_ID_SECURE = 23, 460 BUS_ID_SECURE_CENTER_CHANNEL = 24, 461 BUS_ID_SECURE_VO1USB_CHANNEL = 25, 462 BUS_ID_CENTER = 26, 463 BUS_ID_CENTER_CHANNEL = 27, 464 BUS_ID_MSCH0 = 28, 465 BUS_ID_MSCH1 = 29, 466 BUS_ID_MSCH2 = 30, 467 BUS_ID_MSCH3 = 31, 468 BUS_ID_MSCH = 32, 469 BUS_ID_BUS = 33, 470 BUS_ID_TOP = 34, 471 }; 472 473 enum pmu2_mem_st { 474 PD_NPU_TOP_MEM_ST = 11, 475 PD_NPU1_MEM_ST = 12, 476 PD_NPU2_MEM_ST = 13, 477 PD_VENC0_MEM_ST = 14, 478 PD_VENC1_MEM_ST = 15, 479 PD_RKVDEC0_MEM_ST = 16, 480 PD_RKVDEC1_MEM_ST = 17, 481 PD_RGA30_MEM_ST = 19, 482 PD_AV1_MEM_ST = 20, 483 PD_VI_MEM_ST = 21, 484 PD_FEC_MEM_ST = 22, 485 PD_ISP1_MEM_ST = 23, 486 PD_RGA31_MEM_ST = 24, 487 PD_VOP_MEM_ST = 25, 488 PD_VO0_MEM_ST = 26, 489 PD_VO1_MEM_ST = 27, 490 PD_AUDIO_MEM_ST = 28, 491 PD_PHP_MEM_ST = 29, 492 PD_GMAC_MEM_ST = 30, 493 PD_PCIE_MEM_ST = 31, 494 PD_NVM0_MEM_ST = 33, 495 PD_SDIO_MEM_ST = 34, 496 PD_USB_MEM_ST = 35, 497 PD_SDMMC_MEM_ST = 37, 498 }; 499 500 enum pmu2_qid { 501 QID_PHPMMU_TBU = 0, 502 QID_PHPMMU_TCU = 1, 503 QID_PCIEMMU_TBU0 = 2, 504 QID_PCIEMU_TCU = 3, 505 QID_PHP_GICITS = 4, 506 QID_BUS_GICITS0 = 5, 507 QID_BUS_GICITS1 = 6, 508 }; 509 510 /* PMU_DSU_PWR_CON */ 511 enum pmu_dsu_pwr_con { 512 DSU_PWRDN_ENA = 2, 513 DSU_PWROFF_ENA, 514 DSU_RET_ENA = 6, 515 CLUSTER_CLK_SRC_GATE_ENA, 516 DSU_PWR_CON_END 517 }; 518 519 enum cpu_power_state { 520 CPU_POWER_ON, 521 CPU_POWER_OFF, 522 CPU_EMULATION_OFF, 523 CPU_RETENTION, 524 CPU_DEBUG 525 }; 526 527 enum dsu_power_state { 528 DSU_POWER_ON, 529 CLUSTER_TRANSFER_IDLE, 530 DSU_POWER_DOWN, 531 DSU_OFF, 532 DSU_WAKEUP, 533 DSU_POWER_UP, 534 CLUSTER_TRANSFER_RESUME, 535 DSU_FUNCTION_RETENTION 536 }; 537 538 /* PMU2_CLUSTER_STS 0x8080 */ 539 enum pmu2_cluster_sts_bits { 540 pd_cpu0_dwn = 0, 541 pd_cpu1_dwn, 542 pd_cpu2_dwn, 543 pd_cpu3_dwn, 544 pd_cpu4_dwn, 545 pd_cpu5_dwn, 546 pd_cpu6_dwn, 547 pd_cpu7_dwn, 548 pd_core0_dwn, 549 pd_core1_dwn 550 }; 551 552 #define CLUSTER_STS_NONBOOT_CPUS_DWN 0xfe 553 554 enum cpu_off_trigger { 555 CPU_OFF_TRIGGER_WFE = 0, 556 CPU_OFF_TRIGGER_REQ_EML, 557 CPU_OFF_TRIGGER_REQ_WFI, 558 CPU_OFF_TRIGGER_REQ_WFI_NBT_CPU, 559 CPU_OFF_TRIGGER_REQ_WFI_NBT_CPU_SRAM 560 }; 561 562 /***************************************************************************** 563 * power domain on or off 564 *****************************************************************************/ 565 enum pmu_pd_state { 566 pmu_pd_on = 0, 567 pmu_pd_off = 1 568 }; 569 570 enum bus_state { 571 bus_active, 572 bus_idle, 573 }; 574 575 #define RK_CPU_STATUS_OFF 0 576 #define RK_CPU_STATUS_ON 1 577 #define RK_CPU_STATUS_BUSY -1 578 579 #define PD_CTR_LOOP 500 580 #define MAX_WAIT_COUNT 500 581 582 #define pmu_bus_idle_st(id) \ 583 (!!(mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ST((id) / 32)) & BIT((id) % 32))) 584 585 #define pmu_bus_idle_ack(id) \ 586 (!!(mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ACK((id) / 32)) & BIT((id) % 32))) 587 588 void pm_pll_wait_lock(uint32_t pll_base); 589 #endif /* __PMU_H__ */ 590