1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_ROCKCHIP_RK3288_CLOCK_H__ 4 #define __SOC_ROCKCHIP_RK3288_CLOCK_H__ 5 6 #include <soc/addressmap.h> 7 #include <types.h> 8 9 #define OSC_HZ (24*MHz) 10 11 #define GPLL_HZ (594*MHz) 12 #define CPLL_HZ (384*MHz) 13 #define NPLL_HZ (384*MHz) 14 15 enum apll_frequencies { 16 APLL_1800_MHZ, 17 APLL_1416_MHZ, 18 APLL_600_MHZ, 19 }; 20 21 /* The SRAM is clocked off aclk_bus, so we want to max it out for boot speed. */ 22 #define PD_BUS_ACLK_HZ (297000*KHz) 23 #define PD_BUS_HCLK_HZ (148500*KHz) 24 #define PD_BUS_PCLK_HZ (74250*KHz) 25 26 #define PERI_ACLK_HZ (148500*KHz) 27 #define PERI_HCLK_HZ (148500*KHz) 28 #define PERI_PCLK_HZ (74250*KHz) 29 30 #define PWM_CLOCK_HZ PD_BUS_PCLK_HZ 31 32 void rkclk_init(void); 33 void rkclk_configure_spi(unsigned int bus, unsigned int hz); 34 void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy); 35 void rkclk_ddr_phy_ctl_reset(u32 ch, u32 n); 36 void rkclk_configure_ddr(unsigned int hz); 37 void rkclk_configure_i2s(unsigned int hz); 38 void rkclk_configure_cpu(enum apll_frequencies apll_freq); 39 void rkclk_configure_crypto(unsigned int hz); 40 void rkclk_configure_tsadc(unsigned int hz); 41 void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz); 42 int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz); 43 void rkclk_configure_edp(void); 44 void rkclk_configure_hdmi(void); 45 int rkclk_was_watchdog_reset(void); 46 unsigned int rkclk_i2c_clock_for_bus(unsigned int bus); 47 48 #endif /* __SOC_ROCKCHIP_RK3288_CLOCK_H__ */ 49