1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _BAYTRAIL_GFX_H_ 4 #define _BAYTRAIL_GFX_H_ 5 6 /* 7 * PCI config registers. 8 */ 9 10 #define GGC 0x50 11 # define GGC_VGA_DISABLE (1 << 1) 12 # define GGC_GTT_SIZE_MASK (3 << 8) 13 # define GGC_GTT_SIZE_0MB (0 << 8) 14 # define GGC_GTT_SIZE_1MB (1 << 8) 15 # define GGC_GTT_SIZE_2MB (2 << 8) 16 # define GGC_GSM_SIZE_MASK (0x1f << 3) 17 # define GGC_GSM_SIZE_0MB (0 << 3) 18 # define GGC_GSM_SIZE_32MB (1 << 3) 19 # define GGC_GSM_SIZE_64MB (2 << 3) 20 # define GGC_GSM_SIZE_96MB (3 << 3) 21 # define GGC_GSM_SIZE_128MB (4 << 3) 22 # define GGC_GSM_SIZE_160MB (5 << 3) 23 # define GGC_GSM_SIZE_192MB (6 << 3) 24 # define GGC_GSM_SIZE_224MB (7 << 3) 25 # define GGC_GSM_SIZE_256MB (8 << 3) 26 # define GGC_GSM_SIZE_288MB (9 << 3) 27 # define GGC_GSM_SIZE_320MB (10 << 3) 28 # define GGC_GSM_SIZE_352MB (11 << 3) 29 # define GGC_GSM_SIZE_384MB (12 << 3) 30 # define GGC_GSM_SIZE_416MB (13 << 3) 31 # define GGC_GSM_SIZE_448MB (14 << 3) 32 # define GGC_GSM_SIZE_480MB (15 << 3) 33 # define GGC_GSM_SIZE_512MB (16 << 3) 34 35 #define GSM_BASE 0x5c 36 #define GTT_BASE 0x70 37 38 #define MSAC 0x62 39 #define APERTURE_SIZE_MASK (3 << 1) 40 #define APERTURE_SIZE_128MB (0 << 1) 41 #define APERTURE_SIZE_256MB (1 << 1) 42 #define APERTURE_SIZE_512MB (3 << 1) 43 44 #define VLV_DISPLAY_BASE 0x180000 45 #define PIPEA_REG(reg) (VLV_DISPLAY_BASE + (reg)) 46 #define PIPEB_REG(reg) (VLV_DISPLAY_BASE + 0x100 + (reg)) 47 48 /* Panel control registers */ 49 #define HOTPLUG_CTRL 0x61110 50 #define PP_CONTROL 0x61204 51 #define PP_CONTROL_UNLOCK 0xabcd0000 52 #define PP_CONTROL_EDP_FORCE_VDD (1 << 3) 53 #define PP_ON_DELAYS 0x61208 54 #define PP_OFF_DELAYS 0x6120c 55 #define PP_DIVISOR 0x61210 56 #define BACKLIGHT_CTL2 0x61250 57 #define BACKLIGHT_ENABLE (1 << 31) 58 #define BACKLIGHT_CTL 0x61254 59 60 #endif /* _BAYTRAIL_GFX_H_ */ 61