1 /* 2 * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef PLATFORM_DEF_H 10 #define PLATFORM_DEF_H 11 12 #include <arch.h> 13 #include <common/interrupt_props.h> 14 #include <common/tbbr/tbbr_img_def.h> 15 #include <plat/common/common_def.h> 16 #include "socfpga_plat_def.h" 17 18 /* Platform Type */ 19 #define PLAT_SOCFPGA_STRATIX10 1 20 #define PLAT_SOCFPGA_AGILEX 2 21 #define PLAT_SOCFPGA_N5X 3 22 #define PLAT_SOCFPGA_AGILEX5 4 23 #define SIMICS_RUN 1 24 #define MAX_IO_MTD_DEVICES U(1) 25 /* Boot Source configuration 26 * TODO: Shall consider "assert_numeric" in the future 27 */ 28 #if SOCFPGA_BOOT_SOURCE_NAND 29 #define BOOT_SOURCE BOOT_SOURCE_NAND 30 #elif SOCFPGA_BOOT_SOURCE_SDMMC 31 #define BOOT_SOURCE BOOT_SOURCE_SDMMC 32 #elif SOCFPGA_BOOT_SOURCE_QSPI 33 #define BOOT_SOURCE BOOT_SOURCE_QSPI 34 #else 35 #define BOOT_SOURCE BOOT_SOURCE_SDMMC 36 #endif 37 38 /* sysmgr.boot_scratch_cold4 & 5 used for CPU release address for SPL */ 39 #define PLAT_CPU_RELEASE_ADDR 0xffd12210 40 41 /* Magic word to indicate L2 reset is completed */ 42 #define L2_RESET_DONE_STATUS 0x1228E5E7 43 44 /* Magic word to differentiate for SMP secondary core boot request */ 45 #define SMP_SEC_CORE_BOOT_REQ 0x1228E5E8 46 47 /* Define next boot image name and offset */ 48 /* Get non-secure image entrypoint for BL33. Zephyr and Linux */ 49 #ifdef PRELOADED_BL33_BASE 50 #define PLAT_NS_IMAGE_OFFSET PRELOADED_BL33_BASE 51 #else 52 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 53 #define PLAT_NS_IMAGE_OFFSET 0x80200000 54 #else 55 #define PLAT_NS_IMAGE_OFFSET 0x10000000 56 #endif 57 #endif /* #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 */ 58 59 #define PLAT_QSPI_DATA_BASE (0x3C00000) 60 #define PLAT_NAND_DATA_BASE (0x0200000) 61 #define PLAT_SDMMC_DATA_BASE (0x0) 62 63 64 /******************************************************************************* 65 * Platform binary types for linking 66 ******************************************************************************/ 67 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 68 #define PLATFORM_LINKER_ARCH aarch64 69 70 /* SoCFPGA supports up to 124GB RAM */ 71 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39) 72 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39) 73 74 75 /******************************************************************************* 76 * Generic platform constants 77 ******************************************************************************/ 78 #define PLAT_SECONDARY_ENTRY_BASE 0x01f78bf0 79 80 /* Size of cacheable stacks */ 81 #define PLATFORM_STACK_SIZE 0x2000 82 83 /* PSCI related constant */ 84 #define PLAT_NUM_POWER_DOMAINS 5 85 #define PLAT_MAX_PWR_LVL 1 86 #define PLAT_MAX_RET_STATE 1 87 #define PLAT_MAX_OFF_STATE 2 88 #define PLATFORM_SYSTEM_COUNT U(1) 89 #define PLATFORM_CLUSTER_COUNT U(1) 90 #define PLATFORM_CLUSTER0_CORE_COUNT U(4) 91 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 92 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 93 PLATFORM_CLUSTER0_CORE_COUNT) 94 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 95 96 /* Interrupt related constant */ 97 98 #define INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER 29 99 100 #define INTEL_SOCFPGA_IRQ_SEC_SGI_0 8 101 #define INTEL_SOCFPGA_IRQ_SEC_SGI_1 9 102 #define INTEL_SOCFPGA_IRQ_SEC_SGI_2 10 103 #define INTEL_SOCFPGA_IRQ_SEC_SGI_3 11 104 #define INTEL_SOCFPGA_IRQ_SEC_SGI_4 12 105 #define INTEL_SOCFPGA_IRQ_SEC_SGI_5 13 106 #define INTEL_SOCFPGA_IRQ_SEC_SGI_6 14 107 #define INTEL_SOCFPGA_IRQ_SEC_SGI_7 15 108 109 #define TSP_IRQ_SEC_PHY_TIMER INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER 110 #define TSP_SEC_MEM_BASE BL32_BASE 111 #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1) 112 113 114 /******************************************************************************* 115 * BL31 specific defines. 116 ******************************************************************************/ 117 /* 118 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 119 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 120 * little space for growth. 121 */ 122 123 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 124 125 #define BL1_RO_BASE (0xffe00000) 126 #define BL1_RO_LIMIT (0xffe0f000) 127 #define BL1_RW_BASE (0xffe10000) 128 #define BL1_RW_LIMIT (0xffe1ffff) 129 #define BL1_RW_SIZE (0x14000) 130 131 #define BL_DATA_LIMIT PLAT_HANDOFF_OFFSET 132 133 #define PLAT_CPUID_RELEASE (BL_DATA_LIMIT - 16) 134 #define PLAT_SEC_ENTRY (BL_DATA_LIMIT - 8) 135 136 #define CMP_ENTRY 0xFFE3EFF8 137 138 #define PLAT_SEC_WARM_ENTRY 0 139 140 /******************************************************************************* 141 * Platform specific page table and MMU setup constants 142 ******************************************************************************/ 143 #define MAX_XLAT_TABLES 8 144 #define MAX_MMAP_REGIONS 16 145 146 /******************************************************************************* 147 * Declarations and constants to access the mailboxes safely. Each mailbox is 148 * aligned on the biggest cache line size in the platform. This is known only 149 * to the platform as it might have a combination of integrated and external 150 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 151 * line at any cache level. They could belong to different cpus/clusters & 152 * get written while being protected by different locks causing corruption of 153 * a valid mailbox address. 154 ******************************************************************************/ 155 #define CACHE_WRITEBACK_SHIFT 6 156 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 157 158 /******************************************************************************* 159 * UART related constants 160 ******************************************************************************/ 161 #define CRASH_CONSOLE_BASE PLAT_UART0_BASE 162 #define PLAT_INTEL_UART_BASE PLAT_UART0_BASE 163 164 #define PLAT_BAUDRATE (115200) 165 #define PLAT_UART_CLOCK (100000000) 166 167 /******************************************************************************* 168 * PHY related constants 169 ******************************************************************************/ 170 171 #define EMAC0_PHY_MODE PHY_INTERFACE_MODE_RGMII 172 #define EMAC1_PHY_MODE PHY_INTERFACE_MODE_RGMII 173 #define EMAC2_PHY_MODE PHY_INTERFACE_MODE_RGMII 174 175 /******************************************************************************* 176 * GIC related constants 177 ******************************************************************************/ 178 #define PLAT_INTEL_SOCFPGA_GICD_BASE PLAT_GICD_BASE 179 #define PLAT_INTEL_SOCFPGA_GICC_BASE PLAT_GICC_BASE 180 181 /******************************************************************************* 182 * System counter frequency related constants 183 ******************************************************************************/ 184 185 /* 186 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 187 * terminology. On a GICv2 system or mode, the lists will be merged and treated 188 * as Group 0 interrupts. 189 */ 190 #define PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(grp) \ 191 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER, \ 192 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 193 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_0, \ 194 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 195 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_1, \ 196 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 197 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_2, \ 198 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 199 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_3, \ 200 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 201 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_4, \ 202 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 203 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_5, \ 204 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 205 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_6, \ 206 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 207 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_7, \ 208 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE) 209 210 #define PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(grp) 211 212 #define MAX_IO_HANDLES 4 213 #define MAX_IO_DEVICES 4 214 #define MAX_IO_BLOCK_DEVICES 2 215 216 #ifndef __ASSEMBLER__ 217 struct socfpga_bl31_params { 218 param_header_t h; 219 image_info_t *bl31_image_info; 220 entry_point_info_t *bl32_ep_info; 221 image_info_t *bl32_image_info; 222 entry_point_info_t *bl33_ep_info; 223 image_info_t *bl33_image_info; 224 }; 225 #endif 226 227 #endif /* PLATFORM_DEF_H */ 228