1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _TEGRA210_PMC_H_ 4 #define _TEGRA210_PMC_H_ 5 6 #include <stdint.h> 7 8 enum { 9 POWER_PARTID_CRAIL = 0, 10 POWER_PARTID_TD = 1, 11 POWER_PARTID_VE = 2, 12 POWER_PARTID_PCX = 3, 13 POWER_PARTID_C0L2 = 5, 14 POWER_PARTID_MPE = 6, 15 POWER_PARTID_HEG = 7, 16 POWER_PARTID_SAX = 8, 17 POWER_PARTID_CE1 = 9, 18 POWER_PARTID_CE2 = 10, 19 POWER_PARTID_CE3 = 11, 20 POWER_PARTID_CELP = 12, 21 POWER_PARTID_CE0 = 14, 22 POWER_PARTID_C0NC = 15, 23 POWER_PARTID_C1NC = 16, 24 POWER_PARTID_SOR = 17, 25 POWER_PARTID_DIS = 18, 26 POWER_PARTID_DISB = 19, 27 POWER_PARTID_XUSBA = 20, 28 POWER_PARTID_XUSBB = 21, 29 POWER_PARTID_XUSBC = 22, 30 POWER_PARTID_VIC = 23, 31 POWER_PARTID_IRAM = 24, 32 POWER_PARTID_NVDEC = 25, 33 POWER_PARTID_NVJPG = 26, 34 POWER_PARTID_APE = 27, 35 POWER_PARTID_DFD = 28, 36 POWER_PARTID_VE2 = 29, 37 }; 38 39 struct tegra_pmc_regs { 40 u32 cntrl; 41 u32 sec_disable; 42 u32 pmc_swrst; 43 u32 wake_mask; 44 u32 wake_lvl; 45 u32 wake_status; 46 u32 sw_wake_status; 47 u32 dpd_pads_oride; 48 u32 dpd_sample; 49 u32 dpd_enable; 50 u32 pwrgate_timer_off; 51 u32 clamp_status; 52 u32 pwrgate_toggle; 53 u32 remove_clamping_cmd; 54 u32 pwrgate_status; 55 u32 pwrgood_timer; 56 u32 blink_timer; 57 u32 no_iopower; 58 u32 pwr_det; 59 u32 pwr_det_latch; 60 u32 scratch0; 61 u32 scratch1; 62 u32 scratch2; 63 u32 scratch3; 64 u32 scratch4; 65 u32 scratch5; 66 u32 scratch6; 67 u32 scratch7; 68 u32 scratch8; 69 u32 scratch9; 70 u32 scratch10; 71 u32 scratch11; 72 u32 scratch12; 73 u32 scratch13; 74 u32 scratch14; 75 u32 scratch15; 76 u32 scratch16; 77 u32 scratch17; 78 u32 scratch18; 79 u32 scratch19; 80 u32 odmdata; 81 u32 scratch21; 82 u32 scratch22; 83 u32 scratch23; 84 u32 secure_scratch0; 85 u32 secure_scratch1; 86 u32 secure_scratch2; 87 u32 secure_scratch3; 88 u32 secure_scratch4; 89 u32 secure_scratch5; 90 u32 cpupwrgood_timer; 91 u32 cpupwroff_timer; 92 u32 pg_mask; 93 u32 pg_mask_1; 94 u32 auto_wake_lvl; 95 u32 auto_wake_lvl_mask; 96 u32 wake_delay; 97 u32 pwr_det_val; 98 u32 ddr_pwr; 99 u32 usb_debounce_del; 100 u32 usb_a0; 101 u32 crypto_op; 102 u32 pllp_wb0_override; 103 u32 scratch24; 104 u32 scratch25; 105 u32 scratch26; 106 u32 scratch27; 107 u32 scratch28; 108 u32 scratch29; 109 u32 scratch30; 110 u32 scratch31; 111 u32 scratch32; 112 u32 scratch33; 113 u32 scratch34; 114 u32 scratch35; 115 u32 scratch36; 116 u32 scratch37; 117 u32 scratch38; 118 u32 scratch39; 119 u32 scratch40; 120 u32 scratch41; 121 u32 scratch42; 122 u32 bondout_mirror[3]; 123 u32 sys_33v_en; 124 u32 bondout_mirror_access; 125 u32 gate; 126 u32 wake2_mask; 127 u32 wake2_lvl; 128 u32 wake2_status; 129 u32 sw_wake2_status; 130 u32 auto_wake2_lvl_mask; 131 u32 pg_mask_2; 132 u32 pg_mask_ce1; 133 u32 pg_mask_ce2; 134 u32 pg_mask_ce3; 135 u32 pwrgate_timer_ce[7]; 136 u32 pcx_edpd_cntrl; 137 u32 osc_edpd_over; 138 u32 clk_out_cntrl; 139 u32 sata_pwrgt; 140 u32 sensor_ctrl; 141 u32 rst_status; 142 u32 io_dpd_req; 143 u32 io_dpd_status; 144 u32 io_dpd2_req; 145 u32 io_dpd2_status; 146 u32 sel_dpd_tim; 147 u32 vddp_sel; 148 u32 ddr_cfg; 149 u32 e_no_vttgen; 150 u8 _rsv0[4]; 151 u32 pllm_wb0_override_freq; 152 u32 test_pwrgate; 153 u32 pwrgate_timer_mult; 154 u32 dis_sel_dpd; 155 u32 utmip_uhsic_triggers; 156 u32 utmip_uhsic_saved_state; 157 u32 utmip_pad_cfg; 158 u32 utmip_term_pad_cfg; 159 u32 utmip_uhsic_sleep_cfg; 160 u32 utmip_uhsic_sleepwalk_cfg; 161 u32 utmip_sleepwalk_p[3]; 162 u32 uhsic_sleepwalk_p0; 163 u32 utmip_uhsic_status; 164 u32 utmip_uhsic_fake; 165 u32 bondout_mirror3[5 - 3]; 166 u32 secure_scratch6; 167 u32 secure_scratch7; 168 u32 scratch43; 169 u32 scratch44; 170 u32 scratch45; 171 u32 scratch46; 172 u32 scratch47; 173 u32 scratch48; 174 u32 scratch49; 175 u32 scratch50; 176 u32 scratch51; 177 u32 scratch52; 178 u32 scratch53; 179 u32 scratch54; 180 u32 scratch55; 181 u32 scratch0_eco; 182 u32 por_dpd_ctrl; 183 u32 scratch2_eco; 184 u32 utmip_uhsic_line_wakeup; 185 u32 utmip_bias_master_cntrl; 186 u32 utmip_master_config; 187 u32 td_pwrgate_inter_part_timer; 188 u32 utmip_uhsic2_triggers; 189 u32 utmip_uhsic2_saved_state; 190 u32 utmip_uhsic2_sleep_cfg; 191 u32 utmip_uhsic2_sleepwalk_cfg; 192 u32 uhsic2_sleepwalk_p1; 193 u32 utmip_uhsic2_status; 194 u32 utmip_uhsic2_fake; 195 u32 utmip_uhsic2_line_wakeup; 196 u32 utmip_master2_config; 197 u32 utmip_uhsic_rpd_cfg; 198 u32 pg_mask_ce0; 199 u32 pg_mask3[5 - 3]; 200 u32 pllm_wb0_override2; 201 u32 tsc_mult; 202 u32 cpu_vsense_override; 203 u32 glb_amap_cfg; 204 u32 sticky_bits; 205 u32 sec_disable2; 206 u32 weak_bias; 207 u32 reg_short; 208 u32 pg_mask_andor; 209 u8 _rsv1[0x2c]; 210 u32 secure_scratch8; /* offset 0x300 */ 211 u32 secure_scratch9; 212 u32 secure_scratch10; 213 u32 secure_scratch11; 214 u32 secure_scratch12; 215 u32 secure_scratch13; 216 u32 secure_scratch14; 217 u32 secure_scratch15; 218 u32 secure_scratch16; 219 u32 secure_scratch17; 220 u32 secure_scratch18; 221 u32 secure_scratch19; 222 u32 secure_scratch20; 223 u32 secure_scratch21; 224 u32 secure_scratch22; 225 u32 secure_scratch23; 226 u32 secure_scratch24; 227 u32 secure_scratch25; 228 u32 secure_scratch26; 229 u32 secure_scratch27; 230 u32 secure_scratch28; 231 u32 secure_scratch29; 232 u32 secure_scratch30; 233 u32 secure_scratch31; 234 u32 secure_scratch32; 235 u32 secure_scratch33; 236 u32 secure_scratch34; 237 u32 secure_scratch35; 238 u32 secure_scratch36; 239 u32 secure_scratch37; 240 u32 secure_scratch38; 241 u32 secure_scratch39; 242 u32 secure_scratch40; 243 u32 secure_scratch41; 244 u32 secure_scratch42; 245 u32 secure_scratch43; 246 u32 secure_scratch44; 247 u32 secure_scratch45; 248 u32 secure_scratch46; 249 u32 secure_scratch47; 250 u32 secure_scratch48; 251 u32 secure_scratch49; 252 u32 secure_scratch50; 253 u32 secure_scratch51; 254 u32 secure_scratch52; 255 u32 secure_scratch53; 256 u32 secure_scratch54; 257 u32 secure_scratch55; 258 u32 secure_scratch56; 259 u32 secure_scratch57; 260 u32 secure_scratch58; 261 u32 secure_scratch59; 262 u32 secure_scratch60; 263 u32 secure_scratch61; 264 u32 secure_scratch62; 265 u32 secure_scratch63; 266 u32 secure_scratch64; 267 u32 secure_scratch65; 268 u32 secure_scratch66; 269 u32 secure_scratch67; 270 u32 secure_scratch68; 271 u32 secure_scratch69; 272 u32 secure_scratch70; 273 u32 secure_scratch71; 274 u32 secure_scratch72; 275 u32 secure_scratch73; 276 u32 secure_scratch74; 277 u32 secure_scratch75; 278 u32 secure_scratch76; 279 u32 secure_scratch77; 280 u32 secure_scratch78; 281 u32 secure_scratch79; 282 u32 _rsv0x420[8]; 283 u32 cntrl2; /* 0x440 */ 284 u32 _rsv0x444[2]; 285 u32 event_counter; /* 0x44C */ 286 u32 fuse_control; 287 u32 scratch1_eco; 288 u32 _rsv0x458[1]; 289 u32 io_dpd3_req; /* 0x45C */ 290 u32 io_dpd3_status; 291 u32 io_dpd4_req; 292 u32 io_dpd4_status; 293 u32 _rsv0x46C[30]; 294 u32 ddr_cntrl; /* 0x4E4 */ 295 u32 _rsv0x4E8[70]; 296 u32 scratch56; /* 0x600 */ 297 u32 scratch57; 298 u32 scratch58; 299 u32 scratch59; 300 u32 scratch60; 301 u32 scratch61; 302 u32 scratch62; 303 u32 scratch63; 304 u32 scratch64; 305 u32 scratch65; 306 u32 scratch66; 307 u32 scratch67; 308 u32 scratch68; 309 u32 scratch69; 310 u32 scratch70; 311 u32 scratch71; 312 u32 scratch72; 313 u32 scratch73; 314 u32 scratch74; 315 u32 scratch75; 316 u32 scratch76; 317 u32 scratch77; 318 u32 scratch78; 319 u32 scratch79; 320 u32 scratch80; 321 u32 scratch81; 322 u32 scratch82; 323 u32 scratch83; 324 u32 scratch84; 325 u32 scratch85; 326 u32 scratch86; 327 u32 scratch87; 328 u32 scratch88; 329 u32 scratch89; 330 u32 scratch90; 331 u32 scratch91; 332 u32 scratch92; 333 u32 scratch93; 334 u32 scratch94; 335 u32 scratch95; 336 u32 scratch96; 337 u32 scratch97; 338 u32 scratch98; 339 u32 scratch99; 340 u32 scratch100; 341 u32 scratch101; 342 u32 scratch102; 343 u32 scratch103; 344 u32 scratch104; 345 u32 scratch105; 346 u32 scratch106; 347 u32 scratch107; 348 u32 scratch108; 349 u32 scratch109; 350 u32 scratch110; 351 u32 scratch111; 352 u32 scratch112; 353 u32 scratch113; 354 u32 scratch114; 355 u32 scratch115; 356 u32 scratch116; 357 u32 scratch117; 358 u32 scratch118; 359 u32 scratch119; 360 u32 scratch120; /* 0x700 */ 361 u32 scratch121; 362 u32 scratch122; 363 u32 scratch123; 364 u32 scratch124; 365 u32 scratch125; 366 u32 scratch126; 367 u32 scratch127; 368 u32 scratch128; 369 u32 scratch129; 370 u32 scratch130; 371 u32 scratch131; 372 u32 scratch132; 373 u32 scratch133; 374 u32 scratch134; 375 u32 scratch135; 376 u32 scratch136; 377 u32 scratch137; 378 u32 scratch138; 379 u32 scratch139; 380 u32 scratch140; 381 u32 scratch141; 382 u32 scratch142; 383 u32 scratch143; 384 u32 scratch144; 385 u32 scratch145; 386 u32 scratch146; 387 u32 scratch147; 388 u32 scratch148; 389 u32 scratch149; 390 u32 scratch150; 391 u32 scratch151; 392 u32 scratch152; 393 u32 scratch153; 394 u32 scratch154; 395 u32 scratch155; 396 u32 scratch156; 397 u32 scratch157; 398 u32 scratch158; 399 u32 scratch159; 400 u32 scratch160; 401 u32 scratch161; 402 u32 scratch162; 403 u32 scratch163; 404 u32 scratch164; 405 u32 scratch165; 406 u32 scratch166; 407 u32 scratch167; 408 u32 scratch168; 409 u32 scratch169; 410 u32 scratch170; 411 u32 scratch171; 412 u32 scratch172; 413 u32 scratch173; 414 u32 scratch174; 415 u32 scratch175; 416 u32 scratch176; 417 u32 scratch177; 418 u32 scratch178; 419 u32 scratch179; 420 u32 scratch180; 421 u32 scratch181; 422 u32 scratch182; 423 u32 scratch183; 424 u32 scratch184; 425 u32 scratch185; 426 u32 scratch186; 427 u32 scratch187; 428 u32 scratch188; 429 u32 scratch189; 430 u32 scratch190; 431 u32 scratch191; 432 u32 scratch192; 433 u32 scratch193; 434 u32 scratch194; 435 u32 scratch195; 436 u32 scratch196; 437 u32 scratch197; 438 u32 scratch198; 439 u32 scratch199; 440 u32 scratch200; 441 u32 scratch201; 442 u32 scratch202; 443 u32 scratch203; 444 u32 scratch204; 445 u32 scratch205; 446 u32 scratch206; 447 u32 scratch207; 448 u32 scratch208; 449 u32 scratch209; 450 u32 scratch210; 451 u32 scratch211; 452 u32 scratch212; 453 u32 scratch213; 454 u32 scratch214; 455 u32 scratch215; 456 u32 scratch216; 457 u32 scratch217; 458 u32 scratch218; 459 u32 scratch219; 460 u32 scratch220; 461 u32 scratch221; 462 u32 scratch222; 463 u32 scratch223; 464 u32 scratch224; 465 u32 scratch225; 466 u32 scratch226; 467 u32 scratch227; 468 u32 scratch228; 469 u32 scratch229; 470 u32 scratch230; 471 u32 scratch231; 472 u32 scratch232; 473 u32 scratch233; 474 u32 scratch234; 475 u32 scratch235; 476 u32 scratch236; 477 u32 scratch237; 478 u32 scratch238; 479 u32 scratch239; 480 u32 scratch240; 481 u32 scratch241; 482 u32 scratch242; 483 u32 scratch243; 484 u32 scratch244; 485 u32 scratch245; 486 u32 scratch246; 487 u32 scratch247; 488 u32 scratch248; 489 u32 scratch249; 490 u32 scratch250; 491 u32 scratch251; 492 u32 scratch252; 493 u32 scratch253; 494 u32 scratch254; 495 u32 scratch255; 496 u32 scratch256; 497 u32 scratch257; 498 u32 scratch258; 499 u32 scratch259; 500 u32 scratch260; 501 u32 scratch261; 502 u32 scratch262; 503 u32 scratch263; 504 u32 scratch264; 505 u32 scratch265; 506 u32 scratch266; 507 u32 scratch267; 508 u32 scratch268; 509 u32 scratch269; 510 u32 scratch270; 511 u32 scratch271; 512 u32 scratch272; 513 u32 scratch273; 514 u32 scratch274; 515 u32 scratch275; 516 u32 scratch276; 517 u32 scratch277; 518 u32 scratch278; 519 u32 scratch279; 520 u32 scratch280; 521 u32 scratch281; 522 u32 scratch282; 523 u32 scratch283; 524 u32 scratch284; 525 u32 scratch285; 526 u32 scratch286; 527 u32 scratch287; 528 u32 scratch288; 529 u32 scratch289; 530 u32 scratch290; 531 u32 scratch291; 532 u32 scratch292; 533 u32 scratch293; 534 u32 scratch294; 535 u32 scratch295; 536 u32 scratch296; 537 u32 scratch297; 538 u32 scratch298; 539 u32 scratch299; /* 0x9CC */ 540 u32 _rsv0x9D0[50]; 541 u32 secure_scratch80; /* 0xa98 */ 542 u32 secure_scratch81; 543 u32 secure_scratch82; 544 u32 secure_scratch83; 545 u32 secure_scratch84; 546 u32 secure_scratch85; 547 u32 secure_scratch86; 548 u32 secure_scratch87; 549 u32 secure_scratch88; 550 u32 secure_scratch89; 551 u32 secure_scratch90; 552 u32 secure_scratch91; 553 u32 secure_scratch92; 554 u32 secure_scratch93; 555 u32 secure_scratch94; 556 u32 secure_scratch95; 557 u32 secure_scratch96; 558 u32 secure_scratch97; 559 u32 secure_scratch98; 560 u32 secure_scratch99; 561 u32 secure_scratch100; 562 u32 secure_scratch101; 563 u32 secure_scratch102; 564 u32 secure_scratch103; 565 u32 secure_scratch104; 566 u32 secure_scratch105; 567 u32 secure_scratch106; 568 u32 secure_scratch107; 569 u32 secure_scratch108; 570 u32 secure_scratch109; 571 u32 secure_scratch110; 572 u32 secure_scratch111; 573 u32 secure_scratch112; 574 u32 secure_scratch113; 575 u32 secure_scratch114; 576 u32 secure_scratch115; 577 u32 secure_scratch116; 578 u32 secure_scratch117; 579 u32 secure_scratch118; 580 u32 secure_scratch119; 581 }; 582 583 check_member(tegra_pmc_regs, secure_scratch119, 0xB34); 584 585 enum { 586 PMC_RST_STATUS_SOURCE_MASK = 0x7, 587 PMC_RST_STATUS_SOURCE_POR = 0x0, 588 PMC_RST_STATUS_SOURCE_WATCHDOG = 0x1, 589 PMC_RST_STATUS_SOURCE_SENSOR = 0x2, 590 PMC_RST_STATUS_SOURCE_SW_MAIN = 0x3, 591 PMC_RST_STATUS_SOURCE_LP0 = 0x4, 592 PMC_RST_STATUS_NUM_SOURCES = 0x5, 593 }; 594 595 enum { 596 PMC_PWRGATE_TOGGLE_PARTID_MASK = 0x1f, 597 PMC_PWRGATE_TOGGLE_PARTID_SHIFT = 0, 598 PMC_PWRGATE_TOGGLE_START = 0x1 << 8 599 }; 600 601 enum { 602 PMC_CNTRL_KBC_CLK_DIS = 0x1 << 0, 603 PMC_CNTRL_RTC_CLK_DIS = 0x1 << 1, 604 PMC_CNTRL_RTC_RST = 0x1 << 2, 605 PMC_CNTRL_KBC_RST = 0x1 << 3, 606 PMC_CNTRL_MAIN_RST = 0x1 << 4, 607 PMC_CNTRL_LATCHWAKE_EN = 0x1 << 5, 608 PMC_CNTRL_GLITCHDET_DIS = 0x1 << 6, 609 PMC_CNTRL_BLINK_EN = 0x1 << 7, 610 PMC_CNTRL_PWRREQ_POLARITY = 0x1 << 8, 611 PMC_CNTRL_PWRREQ_OE = 0x1 << 9, 612 PMC_CNTRL_SYSCLK_POLARITY = 0x1 << 10, 613 PMC_CNTRL_SYSCLK_OE = 0x1 << 11, 614 PMC_CNTRL_PWRGATE_DIS = 0x1 << 12, 615 PMC_CNTRL_AOINIT = 0x1 << 13, 616 PMC_CNTRL_SIDE_EFFECT_LP0 = 0x1 << 14, 617 PMC_CNTRL_CPUPWRREQ_POLARITY = 0x1 << 15, 618 PMC_CNTRL_CPUPWRREQ_OE = 0x1 << 16, 619 PMC_CNTRL_INTR_POLARITY = 0x1 << 17, 620 PMC_CNTRL_FUSE_OVERRIDE = 0x1 << 18, 621 PMC_CNTRL_CPUPWRGOOD_EN = 0x1 << 19, 622 PMC_CNTRL_CPUPWRGOOD_SEL_SHIFT = 20, 623 PMC_CNTRL_CPUPWRGOOD_SEL_MASK = 624 0x3 << PMC_CNTRL_CPUPWRGOOD_SEL_SHIFT 625 }; 626 627 enum { 628 PMC_DDR_PWR_EMMC_MASK = 1 << 1, 629 PMC_DDR_PWR_VAL_MASK = 1 << 0, 630 }; 631 632 enum { 633 PMC_DDR_CFG_PKG_MASK = 1 << 0, 634 PMC_DDR_CFG_IF_MASK = 1 << 1, 635 PMC_DDR_CFG_XM0_RESET_TRI_MASK = 1 << 12, 636 PMC_DDR_CFG_XM0_RESET_DPDIO_MASK = 1 << 13, 637 }; 638 639 enum { 640 PMC_NO_IOPOWER_MEM_MASK = 1 << 7, 641 PMC_NO_IOPOWER_MEM_COMP_MASK = 1 << 16, 642 }; 643 644 enum { 645 PMC_POR_DPD_CTRL_MEM0_ADDR0_CLK_SEL_DPD_MASK = 1 << 0, 646 PMC_POR_DPD_CTRL_MEM0_ADDR1_CLK_SEL_DPD_MASK = 1 << 1, 647 PMC_POR_DPD_CTRL_MEM0_HOLD_CKE_LOW_OVR_MASK = 1 << 31, 648 }; 649 650 enum { 651 PMC_CNTRL2_HOLD_CKE_LOW_EN = 0x1 << 12 652 }; 653 654 enum { 655 PMC_OSC_EDPD_OVER_XOFS_SHIFT = 1, 656 PMC_OSC_EDPD_OVER_XOFS_MASK = 657 0x3f << PMC_OSC_EDPD_OVER_XOFS_SHIFT 658 }; 659 660 enum { 661 PMC_CMD_HOLD_LOW_BR00_11_MASK = 0x0007FF80, 662 DPD_OFF = 1 << 30, 663 DPD_ON = 2 << 30, 664 }; 665 666 enum { 667 PMC_GPIO_RAIL_AO_SHIFT = 21, 668 PMC_GPIO_RAIL_AO_MASK = (1 << PMC_GPIO_RAIL_AO_SHIFT), 669 PMC_GPIO_RAIL_AO_DISABLE = (0 << PMC_GPIO_RAIL_AO_SHIFT), 670 PMC_GPIO_RAIL_AO_ENABLE = (1 << PMC_GPIO_RAIL_AO_SHIFT), 671 672 PMC_AUDIO_RAIL_AO_SHIFT = 18, 673 PMC_AUDIO_RAIL_AO_MASK = (1 << PMC_AUDIO_RAIL_AO_SHIFT), 674 PMC_AUDIO_RAIL_AO_DISABLE = (0 << PMC_AUDIO_RAIL_AO_SHIFT), 675 PMC_AUDIO_RAIL_AO_ENABLE = (1 << PMC_AUDIO_RAIL_AO_SHIFT), 676 677 PMC_SDMMC3_RAIL_AO_SHIFT = 13, 678 PMC_SDMMC3_RAIL_AO_MASK = (1 << PMC_SDMMC3_RAIL_AO_SHIFT), 679 PMC_SDMMC3_RAIL_AO_DISABLE = (0 << PMC_SDMMC3_RAIL_AO_SHIFT), 680 PMC_SDMMC3_RAIL_AO_ENABLE = (1 << PMC_SDMMC3_RAIL_AO_SHIFT), 681 }; 682 683 #endif /* _TEGRA210_PMC_H_ */ 684