1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _SOC_ELKHARTLAKE_PMC_H_ 4 #define _SOC_ELKHARTLAKE_PMC_H_ 5 6 /* PCI Configuration Space (D31:F2): PMC */ 7 #define PWRMBASE 0x10 8 #define ABASE 0x40 9 10 /* Memory mapped IO registers in PMC */ 11 #define GEN_PMCON_A 0x1020 12 #define DC_PP_DIS (1 << 30) 13 #define DSX_PP_DIS (1 << 29) 14 #define AG3_PP_EN (1 << 28) 15 #define SX_PP_EN (1 << 27) 16 #define ALLOW_ICLK_PLL_SD_INC0 (1 << 26) 17 #define GBL_RST_STS (1 << 24) 18 #define DISB (1 << 23) 19 #define ALLOW_OPI_PLL_SD_INC0 (1 << 22) 20 #define MEM_SR (1 << 21) 21 #define ALLOW_SPXB_CG_INC0 (1 << 20) 22 #define ALLOW_L1LOW_C0 (1 << 19) 23 #define MS4V (1 << 18) 24 #define ALLOW_L1LOW_OPI_ON (1 << 17) 25 #define SUS_PWR_FLR (1 << 16) 26 #define PME_B0_S5_DIS (1 << 15) 27 #define PWR_FLR (1 << 14) 28 #define ALLOW_L1LOW_BCLKREQ_ON (1 << 13) 29 #define DIS_SLP_X_STRCH_SUS_UP (1 << 12) 30 #define SLP_S3_MIN_ASST_WDTH_MASK (3 << 10) 31 #define SLP_S3_MIN_ASST_WDTH_60USEC (0 << 10) 32 #define SLP_S3_MIN_ASST_WDTH_1MS (1 << 10) 33 #define SLP_S3_MIN_ASST_WDTH_50MS (2 << 10) 34 #define SLP_S3_MIN_ASST_WDTH_2S (3 << 10) 35 #define HOST_RST_STS (1 << 9) 36 #define ESPI_SMI_LOCK (1 << 8) 37 #define S4MAW_MASK (3 << 4) 38 #define S4MAW_1S (1 << 4) 39 #define S4MAW_2S (2 << 4) 40 #define S4MAW_3S (3 << 4) 41 #define S4MAW_4S (0 << 4) 42 #define S4ASE (1 << 3) 43 #define PER_SMI_SEL_MASK (3 << 1) 44 #define SMI_RATE_64S (0 << 1) 45 #define SMI_RATE_32S (1 << 1) 46 #define SMI_RATE_16S (2 << 1) 47 #define SMI_RATE_8S (3 << 1) 48 #define SLEEP_AFTER_POWER_FAIL (1 << 0) 49 50 #define GEN_PMCON_B 0x1024 51 #define SLP_STR_POL_LOCK (1 << 18) 52 #define ACPI_BASE_LOCK (1 << 17) 53 #define PM_DATA_BAR_DIS (1 << 16) 54 #define WOL_EN_OVRD (1 << 13) 55 #define BIOS_PCI_EXP_EN (1 << 10) 56 #define PWRBTN_LVL (1 << 9) 57 #define SMI_LOCK (1 << 4) 58 #define RTC_BATTERY_DEAD (1 << 2) 59 60 #define ETR 0x1048 61 #define CF9_LOCK (1 << 31) 62 #define CF9_GLB_RST (1 << 20) 63 64 #define SSML 0x104C 65 #define SSML_SSL_DS (0 << 0) 66 #define SSML_SSL_EN (1 << 0) 67 68 #define SSMC 0x1050 69 #define SSMC_SSMS (1 << 0) 70 71 #define SSMD 0x1054 72 #define SSMD_SSD_MASK (0xffff << 0) 73 74 #define PRSTS 0x1810 75 76 #define S3_PWRGATE_POL 0x1828 77 #define S3DC_GATE_SUS (1 << 1) 78 #define S3AC_GATE_SUS (1 << 0) 79 80 #define S4_PWRGATE_POL 0x182c 81 #define S4DC_GATE_SUS (1 << 1) 82 #define S4AC_GATE_SUS (1 << 0) 83 84 #define S5_PWRGATE_POL 0x1830 85 #define S5DC_GATE_SUS (1 << 15) 86 #define S5AC_GATE_SUS (1 << 14) 87 88 #define DSX_CFG 0x1834 89 #define REQ_CNV_NOWAKE_DSX (1 << 4) 90 #define REQ_BATLOW_DSX (1 << 3) 91 #define DSX_EN_WAKE_PIN (1 << 2) 92 #define DSX_DIS_AC_PRESENT_PD (1 << 1) 93 #define DSX_EN_LAN_WAKE_PIN (1 << 0) 94 #define DSX_CFG_MASK (0x1f << 0) 95 96 #define PMSYNC_TPR_CFG 0x18C4 97 #define PCH2CPU_TPR_CFG_LOCK (1 << 31) 98 #define PCH2CPU_TT_EN (1 << 26) 99 100 #define PCH_PWRM_ACPI_TMR_CTL 0x18FC 101 #define ACPI_TIM_DIS (1 << 1) 102 #define GPIO_GPE_CFG 0x1920 103 #define GPE0_DWX_MASK 0xf 104 #define GPE0_DW_SHIFT(x) (4*(x)) 105 106 #define PMC_GPP_B 0x0 107 #define PMC_GPP_T 0x1 108 #define PMC_GPP_D 0x2 109 #define PMC_GPP_A 0x3 110 #define PMC_GPP_R 0x4 111 #define PMC_GPP_V 0x5 112 #define PMC_GPD 0x6 113 #define PMC_GPP_H 0x7 114 #define PMC_GPP_U 0x8 115 #define PMC_VGPIO 0x9 116 #define PMC_GPP_F 0xA 117 #define PMC_GPP_C 0xB 118 #define PMC_GPP_E 0xC 119 #define PMC_GPP_G 0xD 120 #define PMC_GPP_S 0xE 121 122 #define GBLRST_CAUSE0 0x1924 123 #define GBLRST_CAUSE0_THERMTRIP (1 << 5) 124 #define GBLRST_CAUSE1 0x1928 125 126 #define SLP_S0_RES 0x193c 127 128 #define CPPMVRIC 0x1B1C 129 #define XTALSDQDIS (1 << 22) 130 131 #define IRQ_REG ACTL 132 #define SCI_IRQ_ADJUST 0 133 #define ACTL 0x1BD8 134 #define PWRM_EN (1 << 8) 135 #define ACPI_EN (1 << 7) 136 #define SCI_IRQ_SEL (7 << 0) 137 138 #define SCIS_IRQ9 0 139 #define SCIS_IRQ10 1 140 #define SCIS_IRQ11 2 141 #define SCIS_IRQ20 4 142 #define SCIS_IRQ21 5 143 #define SCIS_IRQ22 6 144 #define SCIS_IRQ23 7 145 #endif 146