1 /*
2 * Copyright (c) 2012-2015 Etnaviv Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #ifndef H_ETNA_INTERNAL
25 #define H_ETNA_INTERNAL
26
27 #include <assert.h>
28 #include <stdbool.h>
29 #include <stdint.h>
30
31 #include "hw/common.xml.h"
32 #include "hw/common_3d.xml.h"
33 #include "hw/state.xml.h"
34 #include "hw/state_3d.xml.h"
35
36 #include "drm/etnaviv_drmif.h"
37
38 #include "pipe/p_state.h"
39
40 #define ETNA_NUM_INPUTS (16)
41 #define ETNA_NUM_VARYINGS 16
42 #define ETNA_NUM_LOD (14)
43 #define ETNA_NUM_LAYERS (6)
44 #define ETNA_MAX_UNIFORMS (256)
45 #define ETNA_MAX_CONST_BUF 16
46 #define ETNA_MAX_PIXELPIPES 2
47
48 /* All RS operations must have width%16 = 0 */
49 #define ETNA_RS_WIDTH_MASK (16 - 1)
50 /* RS tiled operations must have height%4 = 0 */
51 #define ETNA_RS_HEIGHT_MASK (3)
52 /* PE render targets must be aligned to 64 bytes */
53 #define ETNA_PE_ALIGNMENT (64)
54
55 /* These demarcate the margin (fixp16) between the computed sizes and the
56 value sent to the chip. These have been set to the numbers used by the
57 Vivante driver on gc2000. They used to be -1 for scissor right and bottom. I
58 am not sure whether older hardware was relying on these or they were just a
59 guess. But if so, these need to be moved to the _specs structure.
60 */
61 #define ETNA_SE_SCISSOR_MARGIN_RIGHT (0x1119)
62 #define ETNA_SE_SCISSOR_MARGIN_BOTTOM (0x1111)
63 #define ETNA_SE_CLIP_MARGIN_RIGHT (0xffff)
64 #define ETNA_SE_CLIP_MARGIN_BOTTOM (0xffff)
65
66 /* GPU chip 3D specs */
67 struct etna_specs {
68 /* supports SUPERTILE (64x64) tiling? */
69 unsigned can_supertile : 1;
70 /* needs z=(z+w)/2, for older GCxxx */
71 unsigned vs_need_z_div : 1;
72 /* can use VS_RANGE, PS_RANGE registers*/
73 unsigned has_shader_range_registers : 1;
74 /* has the new sin/cos/log functions */
75 unsigned has_new_transcendentals : 1;
76 /* has no limit on the number of constant sources per instruction */
77 unsigned has_no_oneconst_limit : 1;
78 /* has V4_COMPRESSION */
79 unsigned v4_compression : 1;
80 /* supports single-buffer rendering with multiple pixel pipes */
81 unsigned single_buffer : 1;
82 /* has unified uniforms memory */
83 unsigned has_unified_uniforms : 1;
84 /* can load shader instructions from memory */
85 unsigned has_icache : 1;
86 /* ASTC texture support (and has associated states) */
87 unsigned tex_astc : 1;
88 /* has BLT engine instead of RS */
89 unsigned use_blt : 1;
90 /* supports seamless cube map */
91 unsigned seamless_cube_map : 1;
92 /* number of bits per TS tile */
93 unsigned bits_per_tile;
94 /* clear value for TS (dependent on bits_per_tile) */
95 uint32_t ts_clear_value;
96 /* base of vertex texture units */
97 unsigned vertex_sampler_offset;
98 /* number of fragment sampler units */
99 unsigned fragment_sampler_count;
100 /* number of vertex sampler units */
101 unsigned vertex_sampler_count;
102 /* maximum number of vertex element configurations */
103 unsigned vertex_max_elements;
104 /* vertex shader memory address*/
105 uint32_t vs_offset;
106 /* pixel shader memory address*/
107 uint32_t ps_offset;
108 /* vertex shader uniforms address*/
109 uint32_t vs_uniforms_offset;
110 /* pixel shader uniforms address*/
111 uint32_t ps_uniforms_offset;
112 /* vertex/fragment shader max instructions */
113 uint32_t max_instructions;
114 /* maximum number of VS outputs */
115 unsigned max_vs_outputs;
116 /* maximum number of varyings */
117 unsigned max_varyings;
118 /* maximum vertex uniforms */
119 unsigned max_vs_uniforms;
120 /* maximum pixel uniforms */
121 unsigned max_ps_uniforms;
122 /* maximum texture size */
123 unsigned max_texture_size;
124 /* maximum texture size */
125 unsigned max_rendertarget_size;
126 /* available pixel pipes */
127 unsigned pixel_pipes;
128 /* number of render targets */
129 unsigned num_rts;
130 /* architecture version of NN cores */
131 unsigned nn_core_version;
132 };
133
134 /* Compiled Gallium state. All the different compiled state atoms are woven
135 * together and uploaded only when it is necessary to synchronize the state,
136 * for example before rendering. */
137
138 /* Compiled pipe_blend_color */
139 struct compiled_blend_color {
140 float color[4];
141 uint32_t PE_ALPHA_BLEND_COLOR;
142
143 struct {
144 uint32_t PE_ALPHA_COLOR_EXT0;
145 uint32_t PE_ALPHA_COLOR_EXT1;
146 } rt[PIPE_MAX_COLOR_BUFS];
147 };
148
149 /* Compiled pipe_stencil_ref */
150 struct compiled_stencil_ref {
151 uint32_t PE_STENCIL_CONFIG[2];
152 uint32_t PE_STENCIL_CONFIG_EXT[2];
153 };
154
155 /* Compiled pipe_viewport_state */
156 struct compiled_viewport_state {
157 uint32_t PA_VIEWPORT_SCALE_X;
158 uint32_t PA_VIEWPORT_SCALE_Y;
159 uint32_t PA_VIEWPORT_SCALE_Z;
160 uint32_t PA_VIEWPORT_OFFSET_X;
161 uint32_t PA_VIEWPORT_OFFSET_Y;
162 uint32_t PA_VIEWPORT_OFFSET_Z;
163 uint32_t SE_SCISSOR_LEFT;
164 uint32_t SE_SCISSOR_TOP;
165 uint32_t SE_SCISSOR_RIGHT;
166 uint32_t SE_SCISSOR_BOTTOM;
167 uint32_t PE_DEPTH_NEAR;
168 uint32_t PE_DEPTH_FAR;
169 };
170
171 /* Compiled pipe_framebuffer_state */
172 struct compiled_framebuffer_state {
173 unsigned ps_output_remap[8];
174 uint8_t num_rt;
175 uint32_t GL_MULTI_SAMPLE_CONFIG;
176 uint32_t PE_COLOR_FORMAT;
177 uint32_t PE_DEPTH_CONFIG;
178 struct etna_reloc PE_DEPTH_ADDR;
179 struct etna_reloc PE_PIPE_DEPTH_ADDR[ETNA_MAX_PIXELPIPES];
180 uint32_t PE_DEPTH_STRIDE;
181 uint32_t PE_HDEPTH_CONTROL;
182 uint32_t PE_DEPTH_NORMALIZE;
183 float depth_mrd;
184 struct etna_reloc PE_COLOR_ADDR;
185 struct etna_reloc PE_PIPE_COLOR_ADDR[ETNA_MAX_PIXELPIPES];
186 uint32_t PE_COLOR_STRIDE;
187 uint32_t PE_MEM_CONFIG;
188 uint32_t RA_MULTISAMPLE_UNK00E04;
189 uint32_t RA_MULTISAMPLE_UNK00E10[VIVS_RA_MULTISAMPLE_UNK00E10__LEN];
190 uint32_t RA_CENTROID_TABLE[VIVS_RA_CENTROID_TABLE__LEN];
191 uint32_t TS_MEM_CONFIG;
192 uint32_t TS_DEPTH_CLEAR_VALUE;
193 struct etna_reloc TS_DEPTH_STATUS_BASE;
194 struct etna_reloc TS_DEPTH_SURFACE_BASE;
195 uint32_t TS_COLOR_CLEAR_VALUE;
196 uint32_t TS_COLOR_CLEAR_VALUE_EXT;
197 struct etna_reloc TS_COLOR_STATUS_BASE;
198 struct etna_reloc TS_COLOR_SURFACE_BASE;
199 uint32_t PE_LOGIC_OP;
200 uint32_t PS_CONTROL;
201 uint32_t PS_CONTROL_EXT;
202 uint32_t PS_OUTPUT_REG2;
203 struct etna_reloc PE_RT_COLOR_ADDR[7];
204 struct etna_reloc PE_RT_PIPE_COLOR_ADDR[7][ETNA_MAX_PIXELPIPES];
205 uint32_t PE_RT_CONFIG[7];
206 uint32_t RT_TS_MEM_CONFIG[7];
207 uint32_t RT_TS_COLOR_CLEAR_VALUE[7];
208 uint32_t RT_TS_COLOR_CLEAR_VALUE_EXT[7];
209 struct etna_reloc RT_TS_COLOR_STATUS_BASE[7];
210 struct etna_reloc RT_TS_COLOR_SURFACE_BASE[7];
211 bool msaa_mode; /* adds input (and possible temp) to PS */
212 };
213
214 /* Compiled context->create_vertex_elements_state */
215 struct compiled_vertex_elements_state {
216 unsigned num_elements;
217 uint32_t FE_VERTEX_ELEMENT_CONFIG[VIVS_FE_VERTEX_ELEMENT_CONFIG__LEN];
218 uint32_t NFE_GENERIC_ATTRIB_CONFIG0[VIVS_NFE_GENERIC_ATTRIB__LEN];
219 uint32_t NFE_GENERIC_ATTRIB_SCALE[VIVS_NFE_GENERIC_ATTRIB__LEN];
220 uint32_t NFE_GENERIC_ATTRIB_CONFIG1[VIVS_NFE_GENERIC_ATTRIB__LEN];
221 unsigned num_buffers;
222 uint32_t NFE_VERTEX_STREAMS_VERTEX_DIVISOR[VIVS_NFE_VERTEX_STREAMS__LEN];
223 uint32_t FE_VERTEX_STREAM_CONTROL[VIVS_NFE_VERTEX_STREAMS__LEN];
224 };
225
226 /* Compiled context->set_vertex_buffer result */
227 struct compiled_set_vertex_buffer {
228 struct etna_reloc FE_VERTEX_STREAM_BASE_ADDR;
229 };
230
231 /* Compiled linked VS+PS shader state */
232 struct compiled_shader_state {
233 uint32_t RA_CONTROL;
234 uint32_t PA_ATTRIBUTE_ELEMENT_COUNT;
235 uint32_t PA_CONFIG;
236 uint32_t PA_SHADER_ATTRIBUTES[VIVS_PA_SHADER_ATTRIBUTES__LEN];
237 int pa_shader_attributes_states;
238 uint32_t VS_END_PC;
239 uint32_t VS_OUTPUT_COUNT; /* number of outputs if point size per vertex disabled */
240 uint32_t VS_OUTPUT_COUNT_PSIZE; /* number of outputs of point size per vertex enabled */
241 uint32_t VS_INPUT_COUNT;
242 uint32_t VS_TEMP_REGISTER_CONTROL;
243 uint32_t VS_OUTPUT[8];
244 uint32_t VS_INPUT[4];
245 uint32_t VS_LOAD_BALANCING;
246 uint32_t VS_START_PC;
247 uint32_t PS_END_PC;
248 uint32_t PS_OUTPUT_REG[2];
249 uint32_t PS_INPUT_COUNT;
250 uint32_t PS_INPUT_COUNT_MSAA; /* Adds an input */
251 uint32_t PS_TEMP_REGISTER_CONTROL;
252 uint32_t PS_TEMP_REGISTER_CONTROL_MSAA; /* Adds a temporary if needed to make space for extra input */
253 uint32_t PS_START_PC;
254 uint32_t GL_VARYING_TOTAL_COMPONENTS;
255 uint32_t GL_VARYING_NUM_COMPONENTS[2];
256 uint32_t GL_VARYING_COMPONENT_USE[4];
257 uint32_t GL_HALTI5_SHADER_ATTRIBUTES[VIVS_GL_HALTI5_SHADER_ATTRIBUTES__LEN];
258 int halti5_shader_attributes_states;
259 uint32_t GL_HALTI5_SH_SPECIALS;
260 uint32_t FE_HALTI5_ID_CONFIG;
261 unsigned vs_inst_mem_size;
262 unsigned ps_inst_mem_size;
263 uint32_t *VS_INST_MEM;
264 uint32_t *PS_INST_MEM;
265 struct etna_reloc PS_INST_ADDR;
266 struct etna_reloc VS_INST_ADDR;
267 unsigned writes_z:1;
268 unsigned uses_discard:1;
269 };
270
271 /* Helpers to assist creating and setting bitarrays (eg, for varyings).
272 * field_size must be a power of two, and <= 32. */
273 #define DEFINE_ETNA_BITARRAY(name, num, field_size) \
274 uint32_t name[(num) * (field_size) / 32]
275
276 static inline void
etna_bitarray_set(uint32_t * array,size_t array_size,size_t field_size,size_t index,uint32_t value)277 etna_bitarray_set(uint32_t *array, size_t array_size, size_t field_size,
278 size_t index, uint32_t value)
279 {
280 size_t shift = (index * field_size) % 32;
281 size_t offset = (index * field_size) / 32;
282
283 assert(index < array_size * 32 / field_size);
284 assert(value < 1 << field_size);
285
286 array[offset] |= value << shift;
287 }
288
289 #define etna_bitarray_set(array, field_size, index, value) \
290 etna_bitarray_set((array), ARRAY_SIZE(array), field_size, index, value)
291
292 #endif
293