1 /** @file 2 3 Copyright (c) 2020, Intel Corporation. All rights reserved.<BR> 4 5 Redistribution and use in source and binary forms, with or without modification, 6 are permitted provided that the following conditions are met: 7 8 * Redistributions of source code must retain the above copyright notice, this 9 list of conditions and the following disclaimer. 10 * Redistributions in binary form must reproduce the above copyright notice, this 11 list of conditions and the following disclaimer in the documentation and/or 12 other materials provided with the distribution. 13 * Neither the name of Intel Corporation nor the names of its contributors may 14 be used to endorse or promote products derived from this software without 15 specific prior written permission. 16 17 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 21 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 THE POSSIBILITY OF SUCH DAMAGE. 28 29 This file is automatically generated. Please do NOT modify !!! 30 31 **/ 32 33 #ifndef __FSPSUPD_H__ 34 #define __FSPSUPD_H__ 35 36 #include <FspUpd.h> 37 38 #pragma pack(1) 39 40 41 /** FSP-S Configuration 42 **/ 43 typedef struct { 44 45 /** Offset 0x0020 - PCIe Controller 0 Bifurcation 46 Configure PCI Express controller 0 bifurcation. 47 0:X2X2X2X2, 1:X2X2X4, 2:X4X2X2, 3:X4X4, 4:X8 48 **/ 49 UINT8 PcdBifurcationPcie0; 50 51 /** Offset 0x0021 - PCIe Controller 1 Bifurcation 52 Configure PCI Express controller 1 bifurcation. 53 0:X2X2X2X2, 1:X2X2X4, 2:X4X2X2, 3:X4X4, 4:X8 54 **/ 55 UINT8 PcdBifurcationPcie1; 56 57 /** Offset 0x0022 - Active Core Count 58 Select # of Active Cores (Default: 0, 0:ALL, 1..15 = 1..15 Cores) 59 0:ALL, 1:1, 2:2, 3:3, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 60 14:14, 15:15 61 **/ 62 UINT8 PcdActiveCoreCount; 63 64 /** Offset 0x0023 65 **/ 66 UINT32 PcdCpuMicrocodePatchBase; 67 68 /** Offset 0x0027 69 **/ 70 UINT32 PcdCpuMicrocodePatchSize; 71 72 /** Offset 0x002B - PCIe Controller 0 73 Enable / Disable PCI Express controller 0 74 $EN_DIS 75 **/ 76 UINT8 PcdEnablePcie0; 77 78 /** Offset 0x002C - PCIe Controller 1 79 Enable / Disable PCI Express controller 1 80 $EN_DIS 81 **/ 82 UINT8 PcdEnablePcie1; 83 84 /** Offset 0x002D - Embedded Multi-Media Controller (eMMC) 85 Enable / Disable Embedded Multi-Media controller 86 $EN_DIS 87 **/ 88 UINT8 PcdEnableEmmc; 89 90 /** Offset 0x002E - LAN Controllers 91 Enable / Disable LAN controllers, refer to FSP Integration Guide for details. 92 0:Disable LAN 0 & LAN 1, 1:Enable LAN 0 & LAN 1, 2:Disable LAN 1 only 93 **/ 94 UINT8 PcdEnableGbE; 95 96 /** Offset 0x002F 97 **/ 98 UINT32 PcdFiaMuxConfigRequestPtr; 99 100 /** Offset 0x0033 101 **/ 102 UINT8 UnusedUpdSpace0[4]; 103 104 /** Offset 0x0037 - PCIe Root Port 0 DeEmphasis 105 Desired DeEmphasis level for PCIE root port 106 0:6dB, 1:3.5dB 107 **/ 108 UINT8 PcdPcieRootPort0DeEmphasis; 109 110 /** Offset 0x0038 - PCIe Root Port 1 DeEmphasis 111 Desired DeEmphasis level for PCIE root port 112 0:6dB, 1:3.5dB 113 **/ 114 UINT8 PcdPcieRootPort1DeEmphasis; 115 116 /** Offset 0x0039 - PCIe Root Port 2 DeEmphasis 117 Desired DeEmphasis level for PCIE root port 118 0:6dB, 1:3.5dB 119 **/ 120 UINT8 PcdPcieRootPort2DeEmphasis; 121 122 /** Offset 0x003A - PCIe Root Port 3 DeEmphasis 123 Desired DeEmphasis level for PCIE root port 124 0:6dB, 1:3.5dB 125 **/ 126 UINT8 PcdPcieRootPort3DeEmphasis; 127 128 /** Offset 0x003B - PCIe Root Port 4 DeEmphasis 129 Desired DeEmphasis level for PCIE root port 130 0:6dB, 1:3.5dB 131 **/ 132 UINT8 PcdPcieRootPort4DeEmphasis; 133 134 /** Offset 0x003C - PCIe Root Port 5 DeEmphasis 135 Desired DeEmphasis level for PCIE root port 136 0:6dB, 1:3.5dB 137 **/ 138 UINT8 PcdPcieRootPort5DeEmphasis; 139 140 /** Offset 0x003D - PCIe Root Port 6 DeEmphasis 141 Desired DeEmphasis level for PCIE root port 142 0:6dB, 1:3.5dB 143 **/ 144 UINT8 PcdPcieRootPort6DeEmphasis; 145 146 /** Offset 0x003E - PCIe Root Port 7 DeEmphasis 147 Desired DeEmphasis level for PCIE root port 148 0:6dB, 1:3.5dB 149 **/ 150 UINT8 PcdPcieRootPort7DeEmphasis; 151 152 /** Offset 0x003F 153 **/ 154 UINT8 UnusedUpdSpace1; 155 156 /** Offset 0x0040 157 **/ 158 UINT32 PcdEMMCDLLConfigPtr; 159 160 /** Offset 0x0044 - Disable Monitor MWAIT 161 Enable / Disable the Monitor-MWAIT Instruction 162 $EN_DIS 163 **/ 164 UINT8 PcdDisableMonitorFSM; 165 166 /** Offset 0x0045 167 **/ 168 UINT8 UnusedUpdSpace2[155]; 169 170 /** Offset 0x00E0 171 **/ 172 UINT8 ReservedSiliconInitUpd[16]; 173 } FSPS_CONFIG; 174 175 /** Fsp S UPD Configuration 176 **/ 177 typedef struct { 178 179 /** Offset 0x0000 180 **/ 181 FSP_UPD_HEADER FspUpdHeader; 182 183 /** Offset 0x0020 184 **/ 185 FSPS_CONFIG FspsConfig; 186 187 /** Offset 0x00F0 188 **/ 189 UINT8 UnusedUpdSpace3[14]; 190 191 /** Offset 0x00FE 192 **/ 193 UINT16 UpdTerminator; 194 } FSPS_UPD; 195 196 #pragma pack() 197 198 #endif 199