| /external/llvm/lib/CodeGen/AsmPrinter/ |
| D | DbgValueHistoryCalculator.cpp | 226 if (unsigned PrevReg = Result.getRegisterForVar(Var)) in calculateDbgValueHistory() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SILowerI1Copies.cpp | 817 unsigned PrevReg, unsigned CurReg) { in buildMergeLaneMasks()
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| D | SILowerI1Copies.cpp | 822 unsigned PrevReg, unsigned CurReg) { in buildMergeLaneMasks()
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| /external/llvm/lib/Target/Sparc/AsmParser/ |
| D | SparcAsmParser.cpp | 500 MCOperand PrevReg = MCOperand::createReg(Sparc::G0); in expandSET() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/ |
| D | ModuloSchedule.cpp | 562 unsigned PrevReg = 0; in generateExistingPhis() local
1145 unsigned PrevReg) { in rewriteScheduledInstr()
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| D | RegAllocFast.cpp | 884 MCPhysReg PrevReg = LRI->PhysReg; in defineLiveThroughVirtReg() local
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| D | MachinePipeliner.cpp | 2143 unsigned PrevReg = getLoopPhiReg(*Phi, MI->getParent()); in canUseLastOffsetValue() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | ModuloSchedule.cpp | 562 unsigned PrevReg = 0; in generateExistingPhis() local
1139 unsigned PrevReg) { in rewriteScheduledInstr()
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| D | RegAllocGreedy.cpp | 809 unsigned RAGreedy::canReassign(LiveInterval &VirtReg, unsigned PrevReg) { in canReassign()
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| D | MachinePipeliner.cpp | 2113 unsigned PrevReg = getLoopPhiReg(*Phi, MI->getParent()); in canUseLastOffsetValue() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/AsmParser/ |
| D | SparcAsmParser.cpp | 537 MCOperand PrevReg = MCOperand::createReg(Sparc::G0); in expandSET() local
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Sparc/AsmParser/ |
| D | SparcAsmParser.cpp | 603 MCOperand PrevReg = MCOperand::createReg(Sparc::G0); in expandSET() local
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| /external/llvm/lib/CodeGen/ |
| D | MachinePipeliner.cpp | 2670 unsigned PrevReg = 0; in generateExistingPhis() local
3249 unsigned NewReg, unsigned PrevReg) { in rewriteScheduledInstr()
3327 unsigned PrevReg = getLoopPhiReg(*Phi, MI->getParent()); in canUseLastOffsetValue() local
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| D | RegAllocGreedy.cpp | 662 unsigned RAGreedy::canReassign(LiveInterval &VirtReg, unsigned PrevReg) { in canReassign()
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 1119 int PrevReg = *RegList.List->begin(); in isRegList16() local
4647 unsigned PrevReg = Mips::NoRegister; in parseRegisterList() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 1406 int PrevReg = *RegList.List->begin(); in isRegList16() local
6594 unsigned PrevReg = Mips::NoRegister; in parseRegisterList() local
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 1426 int PrevReg = *RegList.List->begin(); in isRegList16() local
6787 unsigned PrevReg = Mips::NoRegister; in parseRegisterList() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 4394 unsigned PrevReg = FirstReg; in tryParseMatrixTileList() local
4492 int64_t PrevReg = FirstReg; in tryParseVectorList() local
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 2982 int64_t PrevReg = FirstReg; in parseVectorList() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 3354 int64_t PrevReg = FirstReg; in tryParseVectorList() local
|