1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * Based on radeon_winsys.h which is:
6 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
7 * Copyright 2010 Marek Olšák <maraeo@gmail.com>
8 *
9 * SPDX-License-Identifier: MIT
10 */
11
12 #ifndef RADV_RADEON_WINSYS_H
13 #define RADV_RADEON_WINSYS_H
14
15 #include <stdbool.h>
16 #include <stdint.h>
17 #include <stdio.h>
18 #include <stdlib.h>
19 #include <string.h>
20 #include "util/u_math.h"
21 #include "util/u_memory.h"
22 #include <vulkan/vulkan.h>
23 #include "amd_family.h"
24
25 struct radeon_info;
26 struct vk_sync_type;
27 struct vk_sync_wait;
28 struct vk_sync_signal;
29
30 enum radeon_bo_domain { /* bitfield */
31 RADEON_DOMAIN_GTT = 2,
32 RADEON_DOMAIN_VRAM = 4,
33 RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT,
34 RADEON_DOMAIN_GDS = 8,
35 RADEON_DOMAIN_OA = 16,
36 };
37
38 enum radeon_bo_flag { /* bitfield */
39 RADEON_FLAG_GTT_WC = (1 << 0),
40 RADEON_FLAG_CPU_ACCESS = (1 << 1),
41 RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
42 RADEON_FLAG_VIRTUAL = (1 << 3),
43 RADEON_FLAG_VA_UNCACHED = (1 << 4),
44 RADEON_FLAG_IMPLICIT_SYNC = (1 << 5),
45 RADEON_FLAG_NO_INTERPROCESS_SHARING = (1 << 6),
46 RADEON_FLAG_READ_ONLY = (1 << 7),
47 RADEON_FLAG_32BIT = (1 << 8),
48 RADEON_FLAG_PREFER_LOCAL_BO = (1 << 9),
49 RADEON_FLAG_ZERO_VRAM = (1 << 10),
50 RADEON_FLAG_REPLAYABLE = (1 << 11),
51 RADEON_FLAG_DISCARDABLE = (1 << 12),
52 };
53
54 enum radeon_ctx_priority {
55 RADEON_CTX_PRIORITY_INVALID = -1,
56 RADEON_CTX_PRIORITY_LOW = 0,
57 RADEON_CTX_PRIORITY_MEDIUM,
58 RADEON_CTX_PRIORITY_HIGH,
59 RADEON_CTX_PRIORITY_REALTIME,
60 };
61
62 enum radeon_ctx_pstate {
63 RADEON_CTX_PSTATE_NONE = 0,
64 RADEON_CTX_PSTATE_STANDARD,
65 RADEON_CTX_PSTATE_MIN_SCLK,
66 RADEON_CTX_PSTATE_MIN_MCLK,
67 RADEON_CTX_PSTATE_PEAK,
68 };
69
70 enum radeon_value_id {
71 RADEON_ALLOCATED_VRAM,
72 RADEON_ALLOCATED_VRAM_VIS,
73 RADEON_ALLOCATED_GTT,
74 RADEON_TIMESTAMP,
75 RADEON_NUM_BYTES_MOVED,
76 RADEON_NUM_EVICTIONS,
77 RADEON_NUM_VRAM_CPU_PAGE_FAULTS,
78 RADEON_VRAM_USAGE,
79 RADEON_VRAM_VIS_USAGE,
80 RADEON_GTT_USAGE,
81 RADEON_GPU_TEMPERATURE,
82 RADEON_CURRENT_SCLK,
83 RADEON_CURRENT_MCLK,
84 };
85
86 struct radeon_cmdbuf {
87 /* These are uint64_t to tell the compiler that buf can't alias them.
88 * If they're uint32_t the generated code needs to redundantly
89 * store and reload them between buf writes. */
90 uint64_t cdw; /* Number of used dwords. */
91 uint64_t max_dw; /* Maximum number of dwords. */
92 uint64_t reserved_dw; /* Number of dwords reserved through radeon_check_space() */
93 uint32_t *buf; /* The base pointer of the chunk. */
94 };
95
96 #define RADEON_SURF_TYPE_MASK 0xFF
97 #define RADEON_SURF_TYPE_SHIFT 0
98 #define RADEON_SURF_TYPE_1D 0
99 #define RADEON_SURF_TYPE_2D 1
100 #define RADEON_SURF_TYPE_3D 2
101 #define RADEON_SURF_TYPE_CUBEMAP 3
102 #define RADEON_SURF_TYPE_1D_ARRAY 4
103 #define RADEON_SURF_TYPE_2D_ARRAY 5
104 #define RADEON_SURF_MODE_MASK 0xFF
105 #define RADEON_SURF_MODE_SHIFT 8
106
107 #define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_##field##_SHIFT) & RADEON_SURF_##field##_MASK)
108 #define RADEON_SURF_SET(v, field) (((v)&RADEON_SURF_##field##_MASK) << RADEON_SURF_##field##_SHIFT)
109 #define RADEON_SURF_CLR(v, field) ((v) & ~(RADEON_SURF_##field##_MASK << RADEON_SURF_##field##_SHIFT))
110
111 enum radeon_bo_layout {
112 RADEON_LAYOUT_LINEAR = 0,
113 RADEON_LAYOUT_TILED,
114 RADEON_LAYOUT_SQUARETILED,
115
116 RADEON_LAYOUT_UNKNOWN
117 };
118
119 /* Tiling info for display code, DRI sharing, and other data. */
120 struct radeon_bo_metadata {
121 /* Tiling flags describing the texture layout for display code
122 * and DRI sharing.
123 */
124 union {
125 struct {
126 enum radeon_bo_layout microtile;
127 enum radeon_bo_layout macrotile;
128 unsigned pipe_config;
129 unsigned bankw;
130 unsigned bankh;
131 unsigned tile_split;
132 unsigned mtilea;
133 unsigned num_banks;
134 unsigned stride;
135 bool scanout;
136 } legacy;
137
138 struct {
139 /* surface flags */
140 unsigned swizzle_mode : 5;
141 bool scanout;
142 uint32_t dcc_offset_256b;
143 uint32_t dcc_pitch_max;
144 bool dcc_independent_64b_blocks;
145 bool dcc_independent_128b_blocks;
146 unsigned dcc_max_compressed_block_size;
147 } gfx9;
148 } u;
149
150 /* Additional metadata associated with the buffer, in bytes.
151 * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
152 * Supported by amdgpu only.
153 */
154 uint32_t size_metadata;
155 uint32_t metadata[64];
156 };
157
158 struct radeon_winsys_ctx;
159
160 struct radeon_winsys_bo {
161 uint64_t va;
162 uint64_t size;
163 /* buffer is created with AMDGPU_GEM_CREATE_VM_ALWAYS_VALID */
164 bool is_local;
165 bool vram_no_cpu_access;
166 /* buffer is added to the BO list of all submissions */
167 bool use_global_list;
168 enum radeon_bo_domain initial_domain;
169 };
170
171 struct radv_winsys_submit_info {
172 enum amd_ip_type ip_type;
173 int queue_index;
174 unsigned cs_count;
175 unsigned initial_preamble_count;
176 unsigned continue_preamble_count;
177 unsigned postamble_count;
178 struct radeon_cmdbuf **cs_array;
179 struct radeon_cmdbuf **initial_preamble_cs;
180 struct radeon_cmdbuf **continue_preamble_cs;
181 struct radeon_cmdbuf **postamble_cs;
182 bool uses_shadow_regs;
183 };
184
185 /* Kernel effectively allows 0-31. This sets some priorities for fixed
186 * functionality buffers */
187 enum {
188 RADV_BO_PRIORITY_APPLICATION_MAX = 28,
189
190 /* virtual buffers have 0 priority since the priority is not used. */
191 RADV_BO_PRIORITY_VIRTUAL = 0,
192
193 RADV_BO_PRIORITY_METADATA = 10,
194 /* This should be considerably lower than most of the stuff below,
195 * but how much lower is hard to say since we don't know application
196 * assignments. Put it pretty high since it is GTT anyway. */
197 RADV_BO_PRIORITY_QUERY_POOL = 29,
198
199 RADV_BO_PRIORITY_DESCRIPTOR = 30,
200 RADV_BO_PRIORITY_UPLOAD_BUFFER = 30,
201 RADV_BO_PRIORITY_FENCE = 30,
202 RADV_BO_PRIORITY_SHADER = 31,
203 RADV_BO_PRIORITY_SCRATCH = 31,
204 RADV_BO_PRIORITY_CS = 31,
205 };
206
207 struct radv_winsys_gpuvm_fault_info {
208 uint64_t addr;
209 uint32_t status;
210 uint32_t vmhub;
211 };
212
213 enum radv_cs_dump_type {
214 RADV_CS_DUMP_TYPE_IBS,
215 RADV_CS_DUMP_TYPE_CTX_ROLLS,
216 };
217
218 struct radeon_winsys {
219 void (*destroy)(struct radeon_winsys *ws);
220
221 void (*query_info)(struct radeon_winsys *ws, struct radeon_info *gpu_info);
222
223 uint64_t (*query_value)(struct radeon_winsys *ws, enum radeon_value_id value);
224
225 bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset, unsigned num_registers, uint32_t *out);
226
227 const char *(*get_chip_name)(struct radeon_winsys *ws);
228
229 bool (*query_gpuvm_fault)(struct radeon_winsys *ws, struct radv_winsys_gpuvm_fault_info *fault_info);
230
231 VkResult (*buffer_create)(struct radeon_winsys *ws, uint64_t size, unsigned alignment, enum radeon_bo_domain domain,
232 enum radeon_bo_flag flags, unsigned priority, uint64_t address,
233 struct radeon_winsys_bo **out_bo);
234
235 void (*buffer_destroy)(struct radeon_winsys *ws, struct radeon_winsys_bo *bo);
236 void *(*buffer_map)(struct radeon_winsys *ws, struct radeon_winsys_bo *bo, bool use_fixed_addr, void *fixed_addr);
237
238 VkResult (*buffer_from_ptr)(struct radeon_winsys *ws, void *pointer, uint64_t size, unsigned priority,
239 struct radeon_winsys_bo **out_bo);
240
241 VkResult (*buffer_from_fd)(struct radeon_winsys *ws, int fd, unsigned priority, struct radeon_winsys_bo **out_bo,
242 uint64_t *alloc_size);
243
244 bool (*buffer_get_fd)(struct radeon_winsys *ws, struct radeon_winsys_bo *bo, int *fd);
245
246 bool (*buffer_get_flags_from_fd)(struct radeon_winsys *ws, int fd, enum radeon_bo_domain *domains,
247 enum radeon_bo_flag *flags);
248
249 void (*buffer_unmap)(struct radeon_winsys *ws, struct radeon_winsys_bo *bo, bool replace);
250
251 void (*buffer_set_metadata)(struct radeon_winsys *ws, struct radeon_winsys_bo *bo, struct radeon_bo_metadata *md);
252 void (*buffer_get_metadata)(struct radeon_winsys *ws, struct radeon_winsys_bo *bo, struct radeon_bo_metadata *md);
253
254 VkResult (*buffer_virtual_bind)(struct radeon_winsys *ws, struct radeon_winsys_bo *parent, uint64_t offset,
255 uint64_t size, struct radeon_winsys_bo *bo, uint64_t bo_offset);
256
257 VkResult (*buffer_make_resident)(struct radeon_winsys *ws, struct radeon_winsys_bo *bo, bool resident);
258
259 VkResult (*ctx_create)(struct radeon_winsys *ws, enum radeon_ctx_priority priority, struct radeon_winsys_ctx **ctx);
260 void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
261
262 bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx, enum amd_ip_type amd_ip_type, int ring_index);
263
264 int (*ctx_set_pstate)(struct radeon_winsys_ctx *ctx, uint32_t pstate);
265
266 enum radeon_bo_domain (*cs_domain)(const struct radeon_winsys *ws);
267
268 struct radeon_cmdbuf *(*cs_create)(struct radeon_winsys *ws, enum amd_ip_type amd_ip_type, bool is_secondary);
269
270 void (*cs_destroy)(struct radeon_cmdbuf *cs);
271
272 void (*cs_reset)(struct radeon_cmdbuf *cs);
273
274 bool (*cs_chain)(struct radeon_cmdbuf *cs, struct radeon_cmdbuf *next_cs, bool pre_en);
275
276 void (*cs_unchain)(struct radeon_cmdbuf *cs);
277
278 VkResult (*cs_finalize)(struct radeon_cmdbuf *cs);
279
280 void (*cs_grow)(struct radeon_cmdbuf *cs, size_t min_size);
281
282 VkResult (*cs_submit)(struct radeon_winsys_ctx *ctx, const struct radv_winsys_submit_info *submit,
283 uint32_t wait_count, const struct vk_sync_wait *waits, uint32_t signal_count,
284 const struct vk_sync_signal *signals);
285
286 void (*cs_add_buffer)(struct radeon_cmdbuf *cs, struct radeon_winsys_bo *bo);
287
288 void (*cs_execute_secondary)(struct radeon_cmdbuf *parent, struct radeon_cmdbuf *child, bool allow_ib2);
289
290 void (*cs_execute_ib)(struct radeon_cmdbuf *cs, struct radeon_winsys_bo *bo, const uint64_t va, const uint32_t cdw,
291 const bool predicate);
292
293 void (*cs_chain_dgc_ib)(struct radeon_cmdbuf *cs, uint64_t va, uint32_t cdw, uint64_t trailer_va,
294 const bool predicate);
295
296 void (*cs_dump)(struct radeon_cmdbuf *cs, FILE *file, const int *trace_ids, int trace_id_count,
297 enum radv_cs_dump_type type);
298
299 void (*cs_annotate)(struct radeon_cmdbuf *cs, const char *marker);
300
301 void (*cs_pad)(struct radeon_cmdbuf *cs, unsigned leave_dw_space);
302
303 void (*dump_bo_ranges)(struct radeon_winsys *ws, FILE *file);
304
305 void (*dump_bo_log)(struct radeon_winsys *ws, FILE *file);
306
307 int (*get_fd)(struct radeon_winsys *ws);
308
309 const struct vk_sync_type *const *(*get_sync_types)(struct radeon_winsys *ws);
310 };
311
312 static inline void
radeon_emit(struct radeon_cmdbuf * cs,uint32_t value)313 radeon_emit(struct radeon_cmdbuf *cs, uint32_t value)
314 {
315 assert(cs->cdw < cs->reserved_dw);
316 cs->buf[cs->cdw++] = value;
317 }
318
319 static inline void
radeon_emit_direct(struct radeon_cmdbuf * cs,uint32_t offset,uint32_t value)320 radeon_emit_direct(struct radeon_cmdbuf *cs, uint32_t offset, uint32_t value)
321 {
322 assert(offset < cs->reserved_dw);
323 cs->buf[offset] = value;
324 }
325
326 static inline void
radeon_emit_array(struct radeon_cmdbuf * cs,const uint32_t * values,unsigned count)327 radeon_emit_array(struct radeon_cmdbuf *cs, const uint32_t *values, unsigned count)
328 {
329 assert(cs->cdw + count <= cs->reserved_dw);
330 memcpy(cs->buf + cs->cdw, values, count * 4);
331 cs->cdw += count;
332 }
333
334 static inline uint64_t
radv_buffer_get_va(const struct radeon_winsys_bo * bo)335 radv_buffer_get_va(const struct radeon_winsys_bo *bo)
336 {
337 return bo->va;
338 }
339
340 static inline bool
radv_buffer_is_resident(const struct radeon_winsys_bo * bo)341 radv_buffer_is_resident(const struct radeon_winsys_bo *bo)
342 {
343 return bo->use_global_list || bo->is_local;
344 }
345
346 static inline void
radv_cs_add_buffer(struct radeon_winsys * ws,struct radeon_cmdbuf * cs,struct radeon_winsys_bo * bo)347 radv_cs_add_buffer(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, struct radeon_winsys_bo *bo)
348 {
349 if (radv_buffer_is_resident(bo))
350 return;
351
352 ws->cs_add_buffer(cs, bo);
353 }
354
355 static inline void *
radv_buffer_map(struct radeon_winsys * ws,struct radeon_winsys_bo * bo)356 radv_buffer_map(struct radeon_winsys *ws, struct radeon_winsys_bo *bo)
357 {
358 return ws->buffer_map(ws, bo, false, NULL);
359 }
360
361 #endif /* RADV_RADEON_WINSYS_H */
362