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Searched defs:RC1 (Results 1 – 11 of 11) sorted by relevance

/external/okhttp/
DCHANGELOG.md538 #### API Changes
602 #### Implementation changes
/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/
DHexagonGenInsert.cpp340 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1), &RC2 = CM.lookup(VR2); in operator ()() local
357 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1); in operator ()() local
DHexagonBitSimplify.cpp342 bool HexagonBitSimplify::isEqual(const BitTracker::RegisterCell &RC1, in isEqual()
/external/llvm/lib/Target/Hexagon/
DHexagonGenInsert.cpp316 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1), &RC2 = CM.lookup(VR2); in operator ()() local
334 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1); in operator ()() local
DHexagonBitSimplify.cpp268 bool HexagonBitSimplify::isEqual(const BitTracker::RegisterCell &RC1, in isEqual()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonGenInsert.cpp341 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1), &RC2 = CM.lookup(VR2); in operator ()() local
358 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1); in operator ()() local
DHexagonBitSimplify.cpp314 bool HexagonBitSimplify::isEqual(const BitTracker::RegisterCell &RC1, in isEqual()
/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/
DRegAllocFast.cpp1246 const TargetRegisterClass &RC1 = *MRI->getRegClass(Reg1); in allocateInstruction() local
/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp864 auto RC1 = MRI.getRegClass(SrcReg1); in PPCEmitCmp() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp867 auto RC1 = MRI.getRegClass(SrcReg1); in PPCEmitCmp() local
/external/llvm/utils/TableGen/
DCodeGenRegisters.cpp1873 CodeGenRegisterClass *RC1 = RC; in inferCommonSubClass() local