1 /*
2 * Copyright 2009 Nicolai Haehnle.
3 * SPDX-License-Identifier: MIT
4 */
5
6 #ifndef RADEON_PROGRAM_CONSTANTS_H
7 #define RADEON_PROGRAM_CONSTANTS_H
8
9 typedef enum {
10 RC_SATURATE_NONE = 0,
11 RC_SATURATE_ZERO_ONE,
12 RC_SATURATE_MINUS_PLUS_ONE
13 } rc_saturate_mode;
14
15 typedef enum {
16 RC_TEXTURE_2D_ARRAY,
17 RC_TEXTURE_1D_ARRAY,
18 RC_TEXTURE_CUBE,
19 RC_TEXTURE_3D,
20 RC_TEXTURE_RECT,
21 RC_TEXTURE_2D,
22 RC_TEXTURE_1D
23 } rc_texture_target;
24
25 typedef enum {
26 /**
27 * Used to indicate unused register descriptions and
28 * source register that use a constant swizzle.
29 */
30 RC_FILE_NONE = 0,
31 RC_FILE_TEMPORARY,
32
33 /**
34 * Input register.
35 *
36 * \note The compiler attaches no implicit semantics to input registers.
37 * Fragment/vertex program specific semantics must be defined explicitly
38 * using the appropriate compiler interfaces.
39 */
40 RC_FILE_INPUT,
41
42 /**
43 * Output register.
44 *
45 * \note The compiler attaches no implicit semantics to input registers.
46 * Fragment/vertex program specific semantics must be defined explicitly
47 * using the appropriate compiler interfaces.
48 */
49 RC_FILE_OUTPUT,
50 RC_FILE_ADDRESS,
51
52 /**
53 * Indicates a constant from the \ref rc_constant_list .
54 */
55 RC_FILE_CONSTANT,
56
57 /**
58 * Indicates a special register, see RC_SPECIAL_xxx.
59 */
60 RC_FILE_SPECIAL,
61
62 /**
63 * Indicates this register should use the result of the presubtract
64 * operation.
65 */
66 RC_FILE_PRESUB,
67
68 /**
69 * Indicates that the source index has been encoded as a 7-bit float.
70 */
71 RC_FILE_INLINE
72 } rc_register_file;
73
74 enum {
75 /** R500 fragment program ALU result "register" */
76 RC_SPECIAL_ALU_RESULT = 0,
77
78 /** Must be last */
79 RC_NUM_SPECIAL_REGISTERS
80 };
81
82 #define RC_REGISTER_INDEX_BITS 11
83 #define RC_REGISTER_MAX_INDEX (1 << RC_REGISTER_INDEX_BITS)
84
85 typedef enum {
86 RC_SWIZZLE_X = 0,
87 RC_SWIZZLE_Y,
88 RC_SWIZZLE_Z,
89 RC_SWIZZLE_W,
90 RC_SWIZZLE_ZERO,
91 RC_SWIZZLE_ONE,
92 RC_SWIZZLE_HALF,
93 RC_SWIZZLE_UNUSED
94 } rc_swizzle;
95
96 static inline int
is_swizzle_inline_constant(rc_swizzle swizzle)97 is_swizzle_inline_constant(rc_swizzle swizzle)
98 {
99 return swizzle >= RC_SWIZZLE_ZERO;
100 }
101
102 #define RC_MAKE_SWIZZLE(a, b, c, d) (((a) << 0) | ((b) << 3) | ((c) << 6) | ((d) << 9))
103 #define RC_MAKE_SWIZZLE_SMEAR(a) RC_MAKE_SWIZZLE((a), (a), (a), (a))
104 #define GET_SWZ(swz, idx) (((swz) >> ((idx) * 3)) & 0x7)
105 #define GET_BIT(msk, idx) (((msk) >> (idx)) & 0x1)
106 #define SET_SWZ(swz, idx, newv) \
107 do { \
108 (swz) = ((swz) & ~(7 << ((idx) * 3))) | ((newv) << ((idx) * 3)); \
109 } while (0)
110
111 #define RC_SWIZZLE_XYZW RC_MAKE_SWIZZLE(RC_SWIZZLE_X, RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_W)
112 #define RC_SWIZZLE_XYZ0 RC_MAKE_SWIZZLE(RC_SWIZZLE_X, RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_ZERO)
113 #define RC_SWIZZLE_XYZ1 RC_MAKE_SWIZZLE(RC_SWIZZLE_X, RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_ONE)
114 #define RC_SWIZZLE_XYZZ RC_MAKE_SWIZZLE(RC_SWIZZLE_X, RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_Z)
115 #define RC_SWIZZLE_XXXX RC_MAKE_SWIZZLE_SMEAR(RC_SWIZZLE_X)
116 #define RC_SWIZZLE_YYYY RC_MAKE_SWIZZLE_SMEAR(RC_SWIZZLE_Y)
117 #define RC_SWIZZLE_ZZZZ RC_MAKE_SWIZZLE_SMEAR(RC_SWIZZLE_Z)
118 #define RC_SWIZZLE_WWWW RC_MAKE_SWIZZLE_SMEAR(RC_SWIZZLE_W)
119 #define RC_SWIZZLE_0000 RC_MAKE_SWIZZLE_SMEAR(RC_SWIZZLE_ZERO)
120 #define RC_SWIZZLE_1111 RC_MAKE_SWIZZLE_SMEAR(RC_SWIZZLE_ONE)
121 #define RC_SWIZZLE_HHHH RC_MAKE_SWIZZLE_SMEAR(RC_SWIZZLE_HALF)
122 #define RC_SWIZZLE_UUUU RC_MAKE_SWIZZLE_SMEAR(RC_SWIZZLE_UNUSED)
123
124 /**
125 * \name Bitmasks for components of vectors.
126 *
127 * Used for write masks, negation masks, etc.
128 */
129 /*@{*/
130 #define RC_MASK_NONE 0
131 #define RC_MASK_X 1
132 #define RC_MASK_Y 2
133 #define RC_MASK_Z 4
134 #define RC_MASK_W 8
135 #define RC_MASK_XY (RC_MASK_X | RC_MASK_Y)
136 #define RC_MASK_XYZ (RC_MASK_X | RC_MASK_Y | RC_MASK_Z)
137 #define RC_MASK_XYW (RC_MASK_X | RC_MASK_Y | RC_MASK_W)
138 #define RC_MASK_XYZW (RC_MASK_X | RC_MASK_Y | RC_MASK_Z | RC_MASK_W)
139 /*@}*/
140
141 typedef enum { RC_ALURESULT_NONE = 0, RC_ALURESULT_X, RC_ALURESULT_W } rc_write_aluresult;
142
143 typedef enum {
144 RC_PRESUB_NONE = 0,
145
146 /** 1 - 2 * src0 */
147 RC_PRESUB_BIAS,
148
149 /** src1 - src0 */
150 RC_PRESUB_SUB,
151
152 /** src1 + src0 */
153 RC_PRESUB_ADD,
154
155 /** 1 - src0 */
156 RC_PRESUB_INV
157 } rc_presubtract_op;
158
159 typedef enum {
160 RC_OMOD_MUL_1,
161 RC_OMOD_MUL_2,
162 RC_OMOD_MUL_4,
163 RC_OMOD_MUL_8,
164 RC_OMOD_DIV_2,
165 RC_OMOD_DIV_4,
166 RC_OMOD_DIV_8,
167 RC_OMOD_DISABLE
168 } rc_omod_op;
169
170 static inline int
rc_presubtract_src_reg_count(rc_presubtract_op op)171 rc_presubtract_src_reg_count(rc_presubtract_op op)
172 {
173 switch (op) {
174 case RC_PRESUB_BIAS:
175 case RC_PRESUB_INV:
176 return 1;
177 case RC_PRESUB_ADD:
178 case RC_PRESUB_SUB:
179 return 2;
180 default:
181 return 0;
182 }
183 }
184
185 #define RC_SOURCE_NONE 0x0
186 #define RC_SOURCE_RGB 0x1
187 #define RC_SOURCE_ALPHA 0x2
188
189 typedef enum { RC_PRED_DISABLED, RC_PRED_SET, RC_PRED_INV } rc_predicate_mode;
190
191 #endif /* RADEON_PROGRAM_CONSTANTS_H */
192